CN101609819B - lead frame chip packaging structure and manufacturing method thereof - Google Patents
lead frame chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN101609819B CN101609819B CN2008101290538A CN200810129053A CN101609819B CN 101609819 B CN101609819 B CN 101609819B CN 2008101290538 A CN2008101290538 A CN 2008101290538A CN 200810129053 A CN200810129053 A CN 200810129053A CN 101609819 B CN101609819 B CN 101609819B
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- China
- Prior art keywords
- pins
- pin
- strutting piece
- lead frame
- chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
The invention relates to a lead frame chip packaging structure comprising a plurality of pins, a plurality of chips, a plurality of lead wires, a supporting part and a packaging colloid, wherein the pins include a plurality of inner pins and a plurality of outer pins; the chips are arranged on parts of the inner pins; the lead wires electrically connect the chips to other inner pins; the supporting part is bonded to the backs of the inner pins and is provided with a groove, and an opening of the groove is back to the inner pins; and the packaging colloid wraps the pins, the chips, the lead wires and the supporting part, is filled in the groove and exposes out of parts of the outer pins and parts of the surface of the supporting part. Besides, the invention also discloses a method for manufacturing the lead frame chip packaging structure to enhance the packaging quality of the chips.
Description
Technical field
The relevant a kind of lead frame chip encapsulation technology of the present invention, particularly a kind of lead frame chip packaging structure and manufacture method thereof that strengthens the chip-packaging structure quality.
Background technology
The purpose of encapsulation is to give chip and system to produce the effect of mechanical strength that contends with in operational environment.Yet in the operation of envelope mould, it is poor that mold pressing produces a vertical mould flowing pressure, the structure of this stress in being coated on packing colloid, the configuration that may disperse and originally locate, cause as lead frame be exposed to packing colloid, chip displacement, and the routing skew cause defectives such as electrical short circuit, thereby chip is scrapped.
Fig. 1 a is depicted as known semiconductor encapsulating structure schematic diagram.The pin 160 of this encapsulating structure comprises that one has the lead frame of a plurality of long pins 161 and short pin 165, and long pin 161 and 165 formation of short pin, one gap, glutinous first chip 100 of being located on the long pin 161, and first chip 100 is to be arranged in the gap; One glutinous second chip of being located on first chip 100 101; First and second chip 100,101 of a plurality of confessions is electrically connected to the lead 130 of long pin 161 and short pin 165; And coat first chip 100, second chip 101, lead 130 and long and short pin 161,165 packing colloid 150 partly, so as to forming the stack architecture of a plurality of chips, promote the encapsulating products electrical functionality.
Yet, seeing also Fig. 1 b, it is the generalized section of semiconductor package when encapsulating mold pressing procedure of displayed map 1a; In aforementioned structure, no matter be carrying single-chip or a plurality of chip, it only gives supporting chip by the monolateral long pin 161 that is connected to the lead frame intercell connector, come the bearing semiconductor chip strong and can't have connection rib that four limits are connected to intercell connector as the chip carrier of traditional lead frame, therefore, it is in the encapsulation mold process, produce downforce if the mould flowing pressure is uneven slightly, to cause chip position to sink, even make long pin 161 expose outside packing colloid 150 because of pin support force deficiency, moreover, also may be because of mould stream impact, cause lead 130 to pull and rupture, cause the encapsulating products disabler.
Fig. 2 a is known another kind of semiconductor packaging structure, it comprises many pins 260 and a chip bearing seat 210 of a lead frame, the inner of many pins 260 limits a middle section, and chip bearing seat 210 is to be positioned at middle section and to be connected with lead frame by a plurality of supporting ribs 220.Lead frame be characterised in that chip bearing seat 210 four corners lower surface or in supporting rib 220 that chip bearing seat 210 4 corners are connected on have a plurality of downward projections 280, shown in Fig. 2 b.
Continue above-mentionedly, please refer to Fig. 2 b, wherein display chip 200 and lead frame 201, in the encapsulation back along the cornerwise cross section view of chip.In the encapsulation process of this chip, normally chip 200 is attached on the chip bearing seat 210 with adhesion layer, and sealing plastic column glue is formed packing colloid in the die cavity of mould.This known lead frame, in encapsulation process, projection 280 on the chip bearing seat 210 is to lean with the die cavity bottom surface of mould to contact, and can increase the steadiness of chip bearing seat 210, can improve the location of envelope mould injecting glue process chips load bearing seat 210 and chip 200.Yet in the envelope mould injecting glue process, the longitudinal stress of generation and chip 200 weight are disperseed to bear by four above-mentioned corner projections 280, and by pressure formula P=F/A as can be known, the pressure of little loaded area is big, so load is very heavy.
Summary of the invention
In order to address the above problem, one of the object of the invention provides a kind of lead frame chip packaging structure and manufacture method thereof, the particularly a kind of lead frame chip packaging structure of strutting piece under interior pin that be provided with, wherein, this strutting piece is to stick in the lower surface of interior pin with the fixing position of pin, support force in the time of can improving routing is to strengthen the routing quality.
One of the object of the invention provides a kind of lead frame chip packaging structure and manufacture method thereof, wherein mould is that directly contact holds the deformation that vertical mould flowing pressure difference of producing when strutting piece firmly encapsulates with firm support is brought, the big loaded area of performance strutting piece reaches the benefit of bearing pressure for a short time, remain potted the chip non-migration in the colloid, and improve problems such as not short circuit of gold thread, effectively improve the Chip Packaging quality.
In order to achieve the above object, a kind of lead frame chip packaging structure according to an aspect of the present invention, comprise: a plurality of pins, it is made up of many interior pins and many outer pins, its China and foreign countries' pin limits one first horizontal plane, and interior pin connects outer pin and bend horizontal-extending downwards to limit one second horizontal plane; A plurality of chips are arranged on the interior pin of part; Many leads, it electrically connects chip pin in other; One strutting piece, it sticks the back in interior pin, and wherein strutting piece has a groove, and the opening of groove is interior dorsad pin; And a packing colloid, the part surface that it coats pin, chip, lead, strutting piece and fills up groove and expose outer pin of part and strutting piece.
In order to achieve the above object, a kind of lead frame chip packaging manufacturing method according to a further aspect of the invention, comprise: a plurality of pins are provided, wherein pin is made up of many interior pins and many outer pins, its China and foreign countries' pin limits one first horizontal plane, and interior pin connects outer pin and bend horizontal-extending downwards to limit one second horizontal plane; Stick the lower surface of a strutting piece in interior pin, wherein strutting piece has a groove, and the opening of groove is interior dorsad pin; The upper surface of a plurality of chips of storehouse pin in part; Many leads are electrically connected at chip pin in other; Provide a mould to form a die cavity and to expose the outer pin of part, wherein mould contacts strutting piece; And inject a packing colloid to coat pin, chip, lead, strutting piece and to fill up groove and expose the part surface of outer pin of part and strutting piece.
Description of drawings
Fig. 1 a and Fig. 1 b are known semiconductor encapsulating structure generalized section.
Fig. 2 a is depicted as another known semiconductor package schematic top plan view.
Fig. 2 b is depicted as another known semiconductor package generalized section.
Fig. 3 is according to a lead frame chip packaging structure generalized section of the present invention.
Fig. 4 a, Fig. 4 b, Fig. 4 c, Fig. 4 d, Fig. 4 e and Fig. 4 f are depicted as each step structural profile schematic diagram of the lead frame chip packaging manufacturing method according to the present invention.
Embodiment
Shown in Figure 3 is the lead frame chip packaging structure generalized section of one embodiment of the invention.In present embodiment, lead frame chip packaging structure comprises: a plurality of pins 360, a plurality of chips 300, many lead 340, one strutting pieces 370 and a packing colloid 350.Pin 360, it is made up of many interior pins 365 and many outer pins 361, and its China and foreign countries' pin 361 limits one first horizontal plane, and interior pin 365 connects outer pin 361 and bend horizontal-extending downwards to limit one second horizontal plane.Chip 300 is arranged on the interior pin 365 of part.Lead 340, its electrically connect chip 300 to other in pin 365.Strutting piece 370, it sticks in the back of interior pin 365, and wherein strutting piece 370 has a groove 375, and the opening of groove 375 is interior dorsad pins 365.Packing colloid 350, the part surface that it coats pin 360, chip 300, lead 340, strutting piece 370 and fills up groove 375 and expose outer pin 361 of part and strutting piece 370.
Above-mentioned explanation continues, in present embodiment, packing colloid 350 is by a mould (not shown) institute model, this mould is the part lower surface that contact holds strutting piece 370, in other words, in the injecting glue process, mould not only provides the pin 360 of a shell with coated wire frame chip structure, chip 300 and lead 340, more can bring into play the effect of the part lower surface that holds strutting piece 370, and in strutting piece 370 is arranged under the pin 365 to provide support, so, the vertical mould flowing pressure that produces in the encapsulation process of can contending with is poor, bear more chip stack, so can effectively promote the Chip Packaging quality.
In the lead frame chip packaging structure of the foregoing description, the upper surface of its chips 300 is active surfaces, also comprise on it a plurality of weld pad (not shown) for lead 340 as gold thread, pin 365 in electrically connecting.In present embodiment, the material of strutting piece 370 is a non-conductive material.In another embodiment, lead 340 electrically connect chips 300 to all in pin 365 (not shown).
Then, please refer to Fig. 4 a, Fig. 4 b, Fig. 4 c, Fig. 4 d, Fig. 4 e and Fig. 4 f.Fig. 4 a, Fig. 4 b, Fig. 4 c, Fig. 4 d, Fig. 4 e and Fig. 4 f are respectively each step structural profile schematic diagram of the lead frame chip packaging manufacturing method of one embodiment of the invention.At first, please refer to Fig. 4 a, as shown in the figure, a plurality of pins 360 are provided, wherein pin 360 is made up of many interior pins 365 and many outer pins 361, its China and foreign countries' pin 361 limits one first horizontal plane, and interior pin 365 connects outer pin 361 and bend horizontal-extending downwards to limit one second horizontal plane.With reference to figure 4b, stick a strutting piece 370 in the lower surface of interior pin 365 again, wherein strutting piece 370 has a groove 375, and the opening of groove 375 is interior dorsad pins 365.Then, with reference to figure 4c, the upper surface of a plurality of chips 300 of storehouse pin 365 in part.Secondly, please refer to Fig. 4 d, many leads 340 electrically connect chips 300 to other in pin 365.The firm support of pin 365 in wherein strutting piece 370 can provide makes that interior pin 365 can be not crooked because of external force in the process of chip 300 and routing is set.Please refer to Fig. 4 e again, provide a mould 351 to form a die cavity and to expose the outer pin 361 of part, wherein mould 351 contacts strutting piece 370.At last, please refer to Fig. 4 f, inject a packing colloid 350 to coat pin 360, chip 300, lead 340, strutting piece 370 and to fill up groove 375 and expose the part surface of outer pin 361 of part and strutting piece 370.Can make strutting piece 370 can support interior pin 365 on the one hand like this, contact holds mould 351 on the one hand, provides in the support force or encapsulation process of routing, and the vertical mould flowing pressure that overcomes generation is poor, improve the location of packing colloid inner structure, effectively promote the Chip Packaging quality.
The above-mentioned explanation that continues, in present embodiment, the upper surface of chip 300 is active surfaces, also comprise on it a plurality of weld pad (not shown) for lead 340 as gold thread, pin 365 in electrically connecting.Among the another embodiment, lead 340 electrically connect chips 300 to all in pin 365 (not shown).
Comprehensively above-mentioned, lead frame chip packaging structure of the present invention and manufacture method thereof provide a kind of strutting piece be arranged in lead frame chip packaging structure on the pin, wherein, strutting piece is the lower surface of pin in sticking in, supporting interior pin, when routing is provided, an effective support force.In addition, strutting piece connects to conflict in the envelope mold process and holds mould, make packing colloid fill up the groove of strutting piece and expose the part surface of part outer pin and strutting piece, it is poor to overcome the vertical mould flowing pressure that comes self-styled mould mold pressing to produce, bring into play big loaded area and reach the benefit of bearing pressure for a short time, structure in the packing colloid of location avoids deformation, to promote the quality of Chip Packaging.
Above-described embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes person skilled in the art scholar can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with it, be every change that is equal to or replacement of doing according to disclosed spirit, must be encompassed in the claim of the present invention.
Claims (7)
1. lead frame chip packaging structure comprises:
A plurality of pins, it is made up of many interior pins and many outer pins, and wherein these outer pins limit one first horizontal plane, and pin connects these outer pins and bends horizontal-extending downwards to limit one second horizontal plane in these;
A plurality of chips are arranged on these interior pins of part;
Many leads, it electrically connects these chips pin in other these;
One strutting piece, it sticks the back of pin in these, and wherein this strutting piece has a groove, and the opening of this groove is pins in these dorsad; And
One packing colloid, the part surface that it coats these pins, these chips, these leads, this strutting piece and fills up this groove and expose these outer pins of part and this strutting piece.
2. lead frame chip packaging structure according to claim 1 is characterized in that the upper surface of these chips has a plurality of weld pads.
3. lead frame chip packaging structure according to claim 2 is characterized in that these leads electrically connect these weld pads and these interior pins of described part.
4. lead frame chip packaging structure according to claim 1, the material that it is characterized in that this strutting piece is a non-conductive material.
5. lead frame chip packaging manufacturing method comprises:
A plurality of pins are provided, and these pins are made up of many interior pins and many outer pins, and wherein these outer pins limit one first horizontal plane, and pin connects these outer pins and bends horizontal-extending downwards to limit one second horizontal plane in these;
The lower surface that sticks strutting piece pin in these, wherein this strutting piece has a groove, and the opening of this groove is pins in these dorsad;
The a plurality of chips of storehouse are in part upper surface of pin in these;
Many leads electrically connect these chips pin in other these;
Provide a mould to form a die cavity and to expose these outer pins of part, wherein this mould contacts this strutting piece; And
Inject a packing colloid to coat these pins, these chips, these leads, this strutting piece and to fill up this groove and expose the part surface of part these outer pins and this strutting piece.
6. lead frame chip packaging manufacturing method according to claim 5 is characterized in that a plurality of weld pads are arranged at the upper surface of these chips.
7. lead frame chip packaging manufacturing method according to claim 6 is characterized in that these leads electrically connect these weld pads and these interior pins of described part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101290538A CN101609819B (en) | 2008-06-20 | 2008-06-20 | lead frame chip packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101290538A CN101609819B (en) | 2008-06-20 | 2008-06-20 | lead frame chip packaging structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101609819A CN101609819A (en) | 2009-12-23 |
| CN101609819B true CN101609819B (en) | 2011-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101290538A Expired - Fee Related CN101609819B (en) | 2008-06-20 | 2008-06-20 | lead frame chip packaging structure and manufacturing method thereof |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937898A (en) * | 2010-08-12 | 2011-01-05 | 苏州固锝电子股份有限公司 | Rectifier structure for moisture protection |
| US20120103668A1 (en) * | 2010-10-28 | 2012-05-03 | Great Team Backend Foundry, Inc. | Chip Package |
| CN102655133A (en) * | 2011-03-04 | 2012-09-05 | 三星半导体(中国)研究开发有限公司 | Chip packaging component and manufacturing method for same |
| CN105449088B (en) * | 2015-12-17 | 2019-02-05 | 深圳市万兴锐科技有限公司 | LED lead frame and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035985A (en) * | 1999-07-19 | 2001-02-09 | Denso Corp | Semiconductor device sealed with resin |
| CN1354518A (en) * | 2000-11-17 | 2002-06-19 | 矽品精密工业股份有限公司 | Multiwafer integrated circuit package structure |
-
2008
- 2008-06-20 CN CN2008101290538A patent/CN101609819B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035985A (en) * | 1999-07-19 | 2001-02-09 | Denso Corp | Semiconductor device sealed with resin |
| CN1354518A (en) * | 2000-11-17 | 2002-06-19 | 矽品精密工业股份有限公司 | Multiwafer integrated circuit package structure |
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| Publication number | Publication date |
|---|---|
| CN101609819A (en) | 2009-12-23 |
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Granted publication date: 20111207 Termination date: 20130620 |