CN101599806B

CN101599806B - Precise clock recovery method using clock predicting technique

Info

Publication number: CN101599806B
Application number: CN2009100999857A
Authority: CN
Inventors: 朱仁昌
Original assignee: Hangzhou Zailing Electronic Technology Co Ltd
Current assignee: ZHEJIANG NEW ZAILING TECHNOLOGY CO., LTD.
Priority date: 2009-06-25
Filing date: 2009-06-25
Publication date: 2012-07-04
Anticipated expiration: 2029-06-25
Also published as: CN101599806A

Abstract

The invention belongs to the network communication technical field, in particular to a precise clock recovery method using a clock predicting technique in a packed switching network. In the precise clock recovery method using the clock predicting technique, when data packet can not timely arrive owing to network reasons, irregular clock signals same to clock numbers carried by clock information are generated according to input clock and a clock predicting circuit automatically generates a data packet arrival signal so as to ensure output clock. The precise clock recovery method effectively solves problem of unpredictable time delay encountered in a packet switching network of the TDM business.

Description

Adopt the precise clock recovery method of clock predicting technique

Technical field

The invention belongs to the network communications technology field, refer in particular to a kind of precise clock recovery method that in packet switching network, adopts clock predicting technique.

Background technology

Packet switching network is a kind of network that connects between any place that provides.Network packet from many users is sent to packet switching network, and on this network, they can be passed to any remote place that links to each other with network.

Like Fig. 1; In that (professional hereinafter to be referred as TDM) has accurate timing because TDM service; So when in packet switching network, carrying the TDM business, (when each long data packet was regular length, the moment that each packet sends can be thought a clock information to the clock information of the transmitter side of packet switching network; Receiver side is received that the moment of data also can be thought and is clock information) be uniformly, see Fig. 1 (a); Because packet switching network is to adopt store and forward message mode; Adding that data at other transfer of data shared bandwidths of transmission course neutralization, when with other data packet competition bandwidth, may produce unpredictable delay; So the clock information that receives at receiver side is uneven, see Fig. 1 (b); Because what packet switching network bore is transfer function, we must adopt one uneven clock information reverted to uniform clock information, see Fig. 1 (c).

Main employing is synchronous residual time mark clock recovery method at present; Chinese patent CN01115556.6 carries out the method and the circuit of resetting source service clock with residual time mark method, and the data source end must have identical standard time clock with destination end, owing to need to adopt device such as analog phase-locked look; So complex structure; Cost is higher, if data-bag lost secondly can cause the mistake of clock recovery.

Chinese patent 03122833.X mentions the production method that relates to the TDM service recovered clock; Be applied to the TDM service transmission of packet network; Through the filling extent of monitoring TDM service data in buffer; Judge whether the source clock is within the catching range, if then will adjust frequency is reduced into current adjust frequency half the; If not, whether the filling extent of then judging buffer greater than reference value, if greater than the central value of current recovered clock would be added current adjusting frequency; If less than the central value of current recovered clock would be deducted current adjusting frequency; The output recovered clock, and continue to catch, equal adjustable minimum frequency up to adjusting frequency.This technology only need be imported the packet that need carry out clock recovery, can recover corresponding stable tranmitting data register; The present invention need not adopt high-precision network clocking as a reference, does not need the analog phase-locked look device of complex and expensive yet, and the packet jitter that Network Transmission is caused has very strong filtering effect.But the recovered clock of this patent is constantly to drift about along with the length of inter-packet gap, so be not fully uniform clock.

Summary of the invention

In order to overcome the above problems, the present invention provide a kind of can the short time and stably with source clock synchronization, simple in structure, recover more accurate a kind of precise clock recovery method that adopts clock predicting technique.

A kind of precise clock recovery method that adopts clock predicting technique; When packet owing to the network reason can not arrive on time; Clock Forecasting Methodology according to the identical irregular clock signal of the entrained clock number of clock generating of importing and clock information; The clock prediction circuit produces a packet arriving signal automatically to guarantee the output clock, and this method comprises the steps:

1) when circuit receives a packet, packet is added counting;

2) when the reception package counting facility was non-vanishing, irregular clock generator circuit produced the clock of 1000ppm;

3) because each packet carries the established data number, when the bag long counter reaches the data number that packet carries, produces a signal, make the count value of reception package counting facility subtract one; When the value that receives package counting facility was 0, expression had produced enough clock pulse signals.At this moment, irregular clock generator just stops to produce clock pulse signal;

4) the clock prediction circuit is according to the packet time interval of receiving in the past; Predict the moment that next packet arrives; Do not arrive when the moment of packet in prediction arrival, circuit produces a packet arriving signal automatically, receives package counting facility this signal is counted; Just begin produce clock pulse signal because the reception package counting facility has been not 0 irregular clock generator this moment;

5) after the clock prediction circuit has produced the packet arriving signal, when this moment, the authentic data bag arrived,, receive package counting facility not to this packet arriving signal counting for fear of repeating to produce clock.

Further, said packet carries clock information (for example sequence number).

Further, through the chock smotthing circuit irregular clock is carried out smoothing processing, the clock of output is evenly distributed on time-domain.

Further, the digital dock phase-locked loop circuit is for further processing to the output clock of chock smotthing circuit, makes it to satisfy the requirement of shaking and drifting about in the communication system.

Further, its use occasion comprises Ethernet, IP network, MPLS, ATM, frame relay packet switching network.

Further, in programmable logic chip, adopt Digital Logical Circuits to realize clock recovery.

Further, carrier time division multiplexing service in the packet switching network.

Beneficial effect of the present invention: the present invention has solved the unpredictable problem of time-delay that the TDM business runs into effectively in packet switching network, makes the TDM business can accurately recover clock through behind the packet switching network.

Description of drawings

Fig. 1 clock in packet switching network sends the sketch map that receives and recover

Fig. 2 clock prediction circuit fundamental diagram

Embodiment

The present invention adopts Digital Logical Circuits in programmable logic chip (being FPGA), in the professional clock recovery of the TDM of the middle carrying of packet switching network an accurate method being provided.

The operation principle of clock prediction circuit is seen Fig. 2:

● when circuit receives a packet (being clock information), packet is added counting, see Fig. 2-1;

● when the reception package counting facility shown in Fig. 2-1 is non-vanishing, the clock of irregular clock generator (seeing Fig. 2-5) circuit generation+1000ppm;

● because each packet carries the established data number, when bag long counter (seeing Fig. 2-6) reaches the data number that packet carries, produces a signal, make the count value of reception package counting facility (seeing Fig. 2-1) subtract one; When the value that receives package counting facility was 0, expression had produced enough clock pulse signals.At this moment, irregular clock generator just stops to produce clock pulse signal; Said packet carries sequence number isochronon information.

● chock smotthing circuit (seeing Fig. 2-3) carries out smoothing processing to irregular clock, and the clock of output is evenly distributed on time-domain;

● the clock prediction circuit is according to the packet time interval of receiving in the past; Predict the moment that next packet arrives; Do not arrive when the moment of packet in prediction arrival, circuit produces a packet arriving signal automatically, receives package counting facility (seeing Fig. 2-1) this signal is counted; Just begin produce clock pulse signal because the reception package counting facility has been not 0 irregular clock generator (seeing Fig. 2-5) this moment.Circuit smoothing circuit (seeing Fig. 2-3) is because by continuous relatively irregular clock input, so can produce clock output relatively stably;

● after the clock prediction circuit has produced the packet arriving signal, when this moment, the authentic data bag arrived,, receive package counting facility (seeing Fig. 2-1) not to this packet arriving signal counting for fear of repeating to produce clock;

● the digital dock phase-locked loop circuit of seeing Fig. 2-4 is for further processing to the output clock of chock smotthing circuit (seeing Fig. 2-3), makes it to satisfy the requirement of shake and drift in the communication system;

The dotted line of Fig. 1 (c) is the clock information that adopts the clock prediction circuit to produce.

Certain use occasion of the present invention includes but not limited to grouping switching networks such as Ethernet, IP network, MPLS, ATM, frame relay.Implementation method includes but not limited in programmable logic chip (being FPGA) or in asic chip, realize that Digital Logical Circuits realizes clock recovery.

Claims

1. precise clock recovery method that adopts clock predicting technique; Packet it is characterized in that: when can not arrive owing to the network reason on time; The clock generating clock number identical irregular clock signal entrained according to input with clock information; The clock prediction circuit produces a packet arriving signal automatically to guarantee the output clock accuracy, and this method comprises the steps:

1) when circuit receives a packet, packet is added counting;

3) because each packet carries the established data number, when the bag long counter reaches the data number that packet carries, produces a signal, make the count value of reception package counting facility subtract one; When the value that receives package counting facility was 0, expression had produced enough clock pulse signals; At this moment, irregular clock generator just stops to produce clock pulse signal;

2. the precise clock recovery method of employing clock predicting technique according to claim 1 is characterized in that: said packet carries clock information.

3. the precise clock recovery method of employing clock predicting technique according to claim 1 is characterized in that: through the chock smotthing circuit irregular clock is carried out smoothing processing, the clock of output is evenly distributed on time-domain.

4. according to the precise clock recovery method of claim 1 or 3 described employing clock predicting techniques; It is characterized in that: the digital dock phase-locked loop circuit is for further processing to the output clock of chock smotthing circuit, makes it to satisfy the requirement of shaking and drifting about in the communication system.

5. the precise clock recovery method of employing clock predicting technique according to claim 1 is characterized in that: its use occasion comprises Ethernet, IP network, MPLS, ATM, frame relay packet switching network.

6. the precise clock recovery method of employing clock predicting technique according to claim 1 is characterized in that: in programmable logic chip, adopt Digital Logical Circuits to realize clock recovery.

7. the precise clock recovery method of employing clock predicting technique according to claim 1 is characterized in that: carrier time division multiplexing service in packet switching network.