CN101594363B - Full-speed wired remote-transmission module - Google Patents
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Abstract
The invention discloses a full-speed wired remote-transmission module, which comprises two parts of an SOPC and an SHDSL processor, wherein the SOPC is in charge of finishing the interaction with the SHDSL process through a CPU soft-core NIOS II, processing forwarding management information, controlling the logic of the entire remote-transmission module from a starting state to a synchronous state, and providing three service data interfaces and a route of management information interface for a user; and the SHDSL is in charge of finishing the extended TC-PAM modulation based on G.991.2, G.994.1 and G.997.1 protocols of an ITU organization at a digital front end, and achieving twisted-pair transmission at a bidirectional symmetrical load rate of between 128 and 8,192 kbit/s per second. The full-speed wired remote-transmission module has the following advantages: the problems that the conventional remote-transmission module has the defect caused by adopting two techniques of the SHDSL and a VDSL and line interference and can hardly finish the interlocking of clocks at a master end and a slave end are solved; and in the aspect of transmission distance, the remote-transmission moduleimproves the transmission distance to a large extent compared with the conventional remote-transmission module when the transmission rate is same, thus the full-speed wired remote-transmission modulecan reach the transmission distance of between 1 and 10 kilometers through a light coated wire.
Description
Technical field
Present technique relates to the SHDSL technical standard, relates in particular to a kind of full-speed wired remote-transmission module.
Background technology
In some specific application, the DSL technology not only solves professional access, and simultaneously also for relay transmission provides means, this just needs to select to provide the DSL technology of bi-directional symmetrical rate of loading.In the following speed of 4Mbit/s, the SHDSL technology is best selection.When the user proposed the demand of the following speed of the above 8Mbit/s of 4Mbit/s, because the high-transmission rate of loading that G.991.2 ITU demarcates in agreement and the appendix thereof is 5696kbit/s, most of solutions adopted the VDSL technology.VDSL adopts the MCM-DMT of multi-carrier modulation technology or the SCM-QAM of single-carrier modulated technology, and SHDSL adopts the pulse amplitude modulation technology (TC-PAM) of grid coding.Comparatively speaking, the SHDSL technology can realize farther transmission range, and the VDSL technology then can reach higher transmission rate.Traditional remote-transmission module adopts SHDSL and two kinds of technology of VDSL to realize the Double-strand transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading, but adopt this two kinds of Technology Needs two covers to realize circuit, thus aspect integrated level, power consumption and the cost of system Shortcomings.
The present invention adopts SHDSL standard implementation full rate Double-strand transmission, has both solved the deficiency of above-mentioned traditional remote-transmission module, and aspect transmission range, during with identical speed rates, comparing traditional remote-transmission module also has largely lifting.
Summary of the invention
Full-speed wired remote-transmission module disclosed in this invention, mainly consisted of by SOPC (programmable system on chip) and SHDSL processor two large divisions, SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of professional number a tree name interfaces and one road interface of management for the user; The SHDSL processor digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the Double-strand transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.
The SOPC central processing unit mainly by the soft nuclear of CPU NIOS II, UART (asynchronous serial data) transmitting-receiving, ethernet mac, AAL5 is adaptive, AAL2 is adaptive and the hardware program such as interface processing forms: the soft nuclear of CPU NIOS II be responsible for finishing with the SHDSL processor alternately, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime; UART finishes the transmitting-receiving of asynchronous serial data; Ethernet mac is finished the MAC layer function of Ethernet access; It is adaptive that AAL5 finishes the cell of Ethernet data; It is adaptive that AAL2 finishes the cell of voice bitstream.By the processing of these programs, for the user provides three kinds of data-interfaces: transparent bitstream interface, Ethernet interface, cable voice port.Bitstream interface is directly passed through the TDM Interface realization transparent transmission of SHDSL processor; Ethernet interface both can directly by the MII Interface realization access of SHDSL processor, also can be adapted to cell by the UTOPIA Interface realization access of SHDSL processor; Cable voice port is through being adapted to ATM cell by the UTOPIA Interface realization access of SHDSL processor after the digital coding.Management information is transmitted by DSP embedded processing passage EOC.
SHDSL processor part mainly is comprised of unit such as embedded microprocessor, data-interface, clock unit, digital front-end, AFE (analog front end), circuit drivings: embedded microprocessor is responsible for finishing the parsing to cpu command, the processing of EOC message, to the configuration of other processing unit, and cooperate with the NIOS processor finish that circuit is shaken hands, process that pretrigger, nuclear start to synchronous data mode.Data interface unit is in charge of data transmission rate, frame synchronizing signal source, data loopback mode, sampled level and sampling clock edge, the read-write time-delay of slip buffering area etc.DSL becomes/separates frame unit according to ITU agreement regulation G.991.2, with data and EOC message maps to the SHDSL frame, otherwise decomposite data flow and EOC message from the SHDSL frame.Digital front-end has comprised Trellis encoder, Viterbi decoder, scrambler, precoder, frequency spectrum shaping device, Echo Cancellation algorithm unit, near-end cross algorithm unit etc., and digital front-end is responsible for finishing encoding and decoding and the modulation /demodulation of SHDSL frame.Clock unit is controlled the source of reference symbol clock according to the configuration of embedded microprocessor, and provides clock source to data interface unit, framing solution frame unit, data processing unit; In the application of this module, the symbol send-receive clock of CO end and cpe end all is synchronized with on the local crystal oscillator clock of CO end, but the clock phase-locked loop that finally is sent to data-interface is in the time receiving of remote data interface clock, and its phase demodulation information source is in dynamic filling bit information.AFE (analog front end) is finished automatic gain control, filter, D and D/A converter, circuit driving, synthesizer.By these functional modules, digital modulation signals is by the analog signal that converts to of digital to analog converter highly linear, and the circuit driver module through having strong driving force and low distortion characteristic is delivered on the DSL twisted-pair feeder by synthesizer at last again.At receiving terminal, analog input converts digital signal through behind the automatic gain controller to by analog to digital converter.
In order to realize full-speed wired remote-transmission, the present invention adopt based on the ITU tissue G.991.2, G.994.1, the TC-PAM modulation system of agreement regulation expansion G.997.1, modulation level is expanded to 64 TC-PAM: 5 Bit datas of each information symbol carrying this moment; Simultaneously according to ITU-T G.991.2 in the agreement to the regulation of the technical parameters such as handshake method, clock module, circuit gain, power spectral density, set up the G.991.2 transmission of the 8192kbit/s speed of protocol extension.The bracelet that wherein is in one's hands joint utilizes the expanding element in the performance inventory that defines in the agreement G.994.1, finishes the mutual of the data such as transmission rate that the principal and subordinate holds setting, each information symbol carrying bit number.
The below is take sending direction as example, flow chart of data processing to this module is further described, data processing division part needs data type to be processed to comprise management information data and business information data, wherein the business information data may have bitstream data, Ethernet data and voice-data signal: management information is by the access of UART interface, arrive the SHDSL processor through cpu bus, then be sent to the DSL framer, management information is as the EOC passage of EOC messages embedding in the DSL frame; When business is the bit stream form, directly be linked into the serial data interface of SHDSL processor, in the DSL framer, according to the clock of bit stream with data allocations in each time slot of DSL frame; Ethernet data is adapted to the AAL5 cell again through ethernet mac layer among the FPGA, then delivers to the SHDSL processor by the UTOPIA interface, the SHDSL processor with the load distribution in the cell in the DSL frame slot; And voice data is adapted to the AAL2 cell after encoding, and delivers to the DSL framer by the UTOPIA interface, and load is carried by the DSL time slot.
In the SHDSL processor, the DSL frame makes its randomization through scrambler, then delivers to and finishes the TC-PAM modulation in the TCM encoder, then comes balanced signal loss in the line by precoder, then process frequency spectrum shaping device is finished the reformation shape to the signal frequency parameter, delivers on the circuit at last.
The data of receive direction are treated to the inverse operation of sending direction.
The software control flow process of this module is, software section, according to ITU G.991.2 to the regulation of SHDSL setting up procedure, the initialization of SHDSL processor experience, pretrigger, start a series of states, reach at last stable data pattern: at first, NIOSII is as master controller, firmware downloads and the start-up course of control SHDSL processor, by the CRC check code in the firmware, detect the integrality of download firmware, after DSP started smoothly, master controller sent order notice DSP and enters init state, then send configuration parameter to DSP with the form of message, the type that wherein mainly comprises data-interface, characteristic, clock mode, DSL framing solution frame parameter, the parameter of modulating unit, selection of principal and subordinate's end etc.; Subsequently, NIOS II notice DSP enters pre-actuated state, and at this moment, DSP according to G.994.1 agreement and opposite end communication of ITU, if two ends are consistent in parameter configuration such as transmission rate, clock mode, modulating modes, shake hands the parameter of configuration just can finish smoothly; Then DSP shakes hands success message behind master controller in transmission, enter the nuclear starting state: in the nuclear start-up course, the DSP of principal and subordinate's end links up the data rate that obtains to shake hands, under the clock of data-interface drives, the activation signal that comes mutual ITU G.991.2 to stipulate in the agreement with the 2-PAM modulation system, principal and subordinate end all correct finish the nuclear start-up course after, DSP will formally enter data pattern: at first by the data-interface parameter of before configuration and the clock of the synchronous opposite end of clock module, then always according to ITU regulation G.991.2, the framing of complete paired data, modulation, demodulation, separate the work of frame; To the data pattern process, if there is mistake, DSP will report the master controller error reason from the pretrigger of DSP, after NIOS II receives, DSP be put get back to init state, again finish above-mentioned start-up course operation.
When the circuit stable transfer, NIOS II is with the input of poll UART mouth, when input message is arranged, pass to DSP with inputting the form of data with message, then DSP crosses the EOC passage with these data communication devices and is sent to the opposite end, after receiving the successful message of opposite end reception, DSP also will inform master controller with form of message; Simultaneously, also can detect whether the EOC data are arranged from the SHDSL frame that receives at DSP, just send it to NIOS II if having, NIOS II is sent to UART with these data and exports to host computer.
Useful technique effect of the present invention is: the present invention adopts the full-speed wired remote-transmission module of the single standard implementation of SHDSL, not only solve traditional remote-transmission module and need to adopt SHDSL and two kinds of existing deficiencies of technology of VDSL and line-hit and the difficult problems such as interlocking of finishing principal and subordinate two ends clock of traditional remote-transmission module, and aspect transmission range, with identical speed rates the time, its transmission range is compared traditional remote-transmission module also largely lifting, makes this module just can reach the transmission distance of 1～10km by light-duty insulate line.
Description of drawings
Fig. 1, full-speed wired remote-transmission module pie graph;
Fig. 2, flow chart of data processing figure;
Fig. 3, software control flow chart;
Embodiment
Below in conjunction with relevant drawings, full-speed wired remote-transmission module disclosed in this invention is further described in detail: full-speed wired remote-transmission module of the present invention mainly is made of SOPC and SHDSL processor two large divisions: SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of professional number a tree name interfaces and one road interface of management for the user; The SHDSL processor digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the Double-strand transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.
The SOPC central processing unit mainly by the soft nuclear of CPU NIOS II, UART transmitting-receiving, ethernet mac, AAL5 is adaptive, AAL2 is adaptive and the hardware program such as interface processing forms: the soft nuclear of CPU NIOS II is responsible for finishing mutual with the SHDSL processor, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime; UART finishes the transmitting-receiving of asynchronous serial data; Ethernet mac is finished the MAC layer function of Ethernet access; It is adaptive that AAL5 finishes the cell of Ethernet data; It is adaptive that AAL2 finishes the cell of voice bitstream.By the processing of these programs, this module provides three kinds of data-interfaces for the user: transparent bitstream interface, Ethernet interface, cable voice port and one road interface of management.Bitstream interface is directly passed through the TDM Interface realization transparent transmission of SHDSL processor; Ethernet interface both can directly by the MII Interface realization access of SHDSL processor, also can be adapted to cell by the UTOPIA Interface realization access of SHDSL processor; Cable voice port is through being adapted to ATM cell by the UTOPIA Interface realization access of SHDSL processor after the digital coding; Management information is transmitted by the treatment channel EOC of DSP.
SHDSL processor part mainly is comprised of unit such as embedded microprocessor, data-interface, clock unit, digital front-end, AFE (analog front end), circuit drivings: embedded microprocessor is responsible for finishing the parsing to cpu command, the processing of EOC message, to the configuration of other processing unit, and cooperate with the NIOS processor finish that circuit is shaken hands, process that pretrigger, nuclear start to synchronous data mode; Data interface unit is in charge of data transmission rate, frame synchronizing signal source, data loopback mode, sampled level and sampling clock edge, the read-write time-delay of slip buffering area etc.; DSL becomes/separates frame unit according to ITU agreement regulation G.991.2, with data and EOC message maps to the SHDSL frame, otherwise decomposite data flow and EOC message from the SHDSL frame; Digital front-end has comprised Trellis encoder, Viterbi decoder, scrambler, precoder, frequency spectrum shaping device, Echo Cancellation algorithm unit, near-end cross algorithm unit etc., is responsible for finishing encoding and decoding and the modulation /demodulation of SHDSL frame; Clock unit is according to the configuration of embedded microprocessor, control the source of reference symbol clock, and provide clock source to data interface unit, framing solution frame unit, data processing unit, in the application of this module, the symbol send-receive clock of CO end and cpe end all is synchronized with on the local crystal oscillator clock of CO end, but finally be sent to the clock phase-locked loop of data-interface in the time receiving of remote data interface clock, its phase demodulation information source is in dynamic filling bit information; AFE (analog front end) is finished automatic gain control, filter, D and D/A converter, circuit driving, synthesizer; By these functional modules, digital modulation signals is by the analog signal that converts to of digital to analog converter highly linear, and the circuit driver module through having strong driving force and low distortion characteristic is delivered on the DSL twisted-pair feeder by synthesizer at last again; At receiving terminal, analog input converts digital signal through behind the automatic gain controller to by analog to digital converter.
In order to realize full-speed wired remote-transmission, the present invention adopt based on the ITU tissue G.991.2, G.994.1, the TC-PAM modulation system of agreement regulation expansion G.997.1, modulation level is expanded to 64 TC-PAM: 5 Bit datas of each information symbol carrying this moment; Simultaneously according to ITU-T G.991.2 in the agreement to the regulation of the technical parameters such as handshake method, clock module, circuit gain, power spectral density, set up the G.991.2 transmission of the 8192kbit/s speed of protocol extension; The bracelet that wherein is in one's hands joint utilizes the expanding element in the performance inventory that defines in the agreement G.994.1, finishes the mutual of the data such as transmission rate that the principal and subordinate holds setting, each information symbol carrying bit number.
Problem for convenience of explanation, the present embodiment is take sending direction as example, flow chart of data processing to this module is described as follows: data processing division part needs data type to be processed to comprise management information data and business information data, wherein the business information data may have bitstream data, Ethernet data and voice-data signal: management information is by the access of UART interface, arrive the SHDSL processor through cpu bus, then be sent to the DSL framer, management information is as the EOC passage of EOC messages embedding in the DSL frame; When business is the bit stream form, directly be linked into the serial data interface of SHDSL processor, in the DSL framer, according to the clock of bit stream with data allocations in each time slot of DSL frame; Ethernet data is adapted to the AAL5 cell again through ethernet mac layer among the FPGA, then delivers to the SHDSL processor by the UTOPIA interface, the SHDSL processor with the load distribution in the cell in the DSL frame slot; And voice data is adapted to the AAL2 cell after encoding, and delivers to the DSL framer by the UTOPIA interface, and load is carried by the DSL time slot.
In the SHDSL processor, the DSL frame makes its randomization through scrambler, then delivers to and finishes the TC-PAM modulation in the TCM encoder, then comes balanced signal loss in the line by precoder, then process frequency spectrum shaping device is finished the reformation shape to the signal frequency parameter, delivers on the circuit at last.
For the data processing section of receive direction, the briefly namely inverse operation of process of transmitting.
The software control flow process of this module as shown in Figure 3, software section, according to ITU G.991.2 to the regulation of SHDSL setting up procedure, the initialization of SHDSL processor experience, pretrigger, start a series of states, reach at last stable data pattern: at first, NIOS II is as master controller, firmware downloads and the start-up course of control SHDSL processor, by the CRC check code in the firmware, detect the integrality of download firmware, after DSP started smoothly, master control sent order notice DSP and enters init state, then send configuration parameter to DSP with the form of message, the type that wherein mainly comprises data-interface, characteristic, clock mode, DSL framing solution frame parameter, the parameter of modulating unit, selection of principal and subordinate's end etc.; Subsequently, NIOS II notice DSP enters pre-actuated state, and at this moment, DSP according to G.994.1 agreement and opposite end communication of ITU, if two ends are consistent in parameter configuration such as transmission rate, clock mode, modulating modes, shake hands the parameter of configuration just can finish smoothly; Then DSP shakes hands success message behind master controller in transmission, enter the nuclear starting state: in the nuclear start-up course, the DSP of principal and subordinate's end links up the data rate that obtains to shake hands, under the clock of data-interface drives, the activation signal that comes mutual ITU G.991.2 to stipulate in the agreement with the 2-PAM modulation system, principal and subordinate end all correct finish the nuclear start-up course after, DSP will formally enter data pattern: at first by the data-interface parameter of before configuration and the clock of the synchronous opposite end of clock module, then always according to ITU regulation G.991.2, the framing of complete paired data, modulation, demodulation, separate the work of frame; To the data pattern process, if there is mistake, DSP will report the master controller error reason from the pretrigger of DSP, after NIOS II receives, DSP be put get back to init state, again finish above-mentioned start-up course operation.
When the circuit stable transfer, NIOS II is with the input of poll UART mouth, when input message is arranged, pass to DSP with inputting the form of data with message, then DSP crosses the EOC passage with these data communication devices and is sent to the opposite end, after receiving the successful message of opposite end reception, DSP also will inform master controller with form of message; Simultaneously, also can detect whether the EOC data are arranged from the SHDSL frame that receives at DSP, just send it to NIOS II if having, NIOS II is sent to UART with these data and exports to host computer.
Claims (6)
1. full-speed wired remote-transmission module, it is characterized in that: this module comprises SOPC and SHDSL processor two major parts, SOPC is responsible for finishing mutual with the SHDSL processor by the soft nuclear of CPU NIOS II, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime, and provide three kinds of business datum interfaces and one road interface of management for the user; SHDSL digital front-end be responsible for finishing based on the ITU tissue G.991.2, G.994.1, the G.997.1 TC-PAM modulation of agreement regulation expansion, realize the Double-strand transmission of 128kbit/s to 8192kbit/s bi-directional symmetrical rate of loading.
2. full-speed wired remote-transmission module according to claim 1, it is characterized in that: the hardware program of SOPC central processing unit mainly by the soft nuclear of CPU NIOS II, UART transmitting-receiving, ethernet mac, AAL5 is adaptive, AAL2 is adaptive and interface is processed and formed: the soft nuclear of CPU NIOS II is responsible for finishing mutual with the SHDSL processor, be responsible for processing forward management information, and control the logic of whole remote-transmission module between from the starting state to the synchronous regime; UART finishes the transmitting-receiving of asynchronous serial data; Ethernet mac is finished the MAC layer function of Ethernet access; It is adaptive that AAL5 finishes the cell of Ethernet data; It is adaptive that AAL2 finishes the cell of voice bitstream; The processing of the hardware program by the SOPC central processing unit, for the user provides three kinds of business datum interfaces: transparent bitstream interface, Ethernet interface, cable voice port, bitstream interface be the TDM Interface realization transparent transmission by the SHDSL processor directly; Ethernet interface both can directly by the MII Interface realization access of SHDSL processor, also can be adapted to cell by the UTOPIA Interface realization access of SHDSL processor; Cable voice port is through being adapted to ATM cell by the UTOPIA Interface realization access of SHDSL processor after the digital coding; Management information is by the embedded processing passage EOC transmission of DSP.
3. full-speed wired remote-transmission module according to claim 1, it is characterized in that: the Component units of SHDSL processor part is mainly driven by embedded microprocessor, data-interface, clock unit, digital front-end, AFE (analog front end), circuit and forms: embedded microprocessor is responsible for finishing the parsing to cpu command, the processing of EOC message, to the configuration of other processing unit, and cooperate with NIOS II processor finish that circuit is shaken hands, process that pretrigger, nuclear start to synchronous data mode; Data interface unit is in charge of data transmission rate, frame synchronizing signal source, data loopback mode, sampled level and sampling clock edge, the read-write time-delay of slip buffering area; DSL becomes/separates frame unit according to ITU agreement regulation G.991.2, with data and EOC message maps to the SHDSL frame, otherwise decomposite data flow and EOC message from the SHDSL frame; Digital front-end has comprised Trellis encoder, Viterbi decoder, scrambler, precoder, frequency spectrum shaping device, Echo Cancellation algorithm unit and near-end cross algorithm unit, finishes encoding and decoding and the modulation /demodulation of SHDSL frame; Clock unit is controlled the source of reference symbol clock according to the configuration of embedded microprocessor, and provides clock source to data interface unit, framing solution frame unit, data processing unit; AFE (analog front end) comprises that automatic gain control, filter, D and D/A converter, circuit drive and synthesizer, and by the processing of AFE (analog front end), digital modulation signals is by the analog signal that converts to of digital to analog converter highly linear; Circuit driver module through having strong driving force and low distortion characteristic is delivered on the DSL twisted-pair feeder by synthesizer at last again; At receiving terminal, analog input converts digital signal through behind the automatic gain controller to by analog to digital converter.
4. full-speed wired remote-transmission module according to claim 1, it is characterized in that: adopt based on the ITU tissue G.991.2, G.994.1, the TC-PAM modulation system of G.997.1 agreement regulation expansion is: modulation level is expanded to 64 TC-PAM, 5 Bit datas of each information symbol carrying this moment, simultaneously according to ITU-T G.991.2 in the agreement to the regulation of the technical parameter of handshake method, clock module, circuit gain, power spectral density, set up the G.991.2 transmission of the 8192kbit/s speed of protocol extension; The bracelet that wherein is in one's hands joint utilizes the expanding element in the performance inventory that defines in the agreement G.994.1, finishes the mutual of transmission rate that the principal and subordinate holds setting, each information symbol carrying bit number.
5. full-speed wired remote-transmission module according to claim 1, it is characterized in that: the flow chart of data processing of this module sending direction is: data processing division part needs data type to be processed to comprise management information data and business information data, wherein the business information data are divided into bitstream data, Ethernet data and voice-data signal: management information is by the access of UART interface, arrive the SHDSL processor through cpu bus, then be sent to the DSL framer, management information is as the EOC passage of EOC messages embedding in the DSL frame; When business is the bit stream form, directly be linked into the serial data interface of SHDSL processor, in the DSL framer, according to the clock of bit stream with data allocations in each time slot of DSL frame; Ethernet data is adapted to the AAL5 cell again through ethernet mac layer among the FPGA, then delivers to the SHDSL processor by the UTOPIA interface, the SHDSL processor with the load distribution in the cell in the DSL frame slot; And voice data is adapted to the AAL2 cell after encoding, and delivers to the DSL framer by the UTOPIA interface, and load is carried by the DSL time slot;
In the SHDSL processor, the DSL frame makes its randomization through scrambler, then delivers to and finishes the TC-PAM modulation in the TCM encoder, then comes balanced signal loss in the line by precoder, then process frequency spectrum shaping device is finished the reformation shape to the signal frequency parameter, delivers at last on the circuit;
Flow chart of data processing for receive direction is the inverse operation of direction of transfer flow chart of data processing.
6. full-speed wired remote-transmission module according to claim 1, it is characterized in that: the software control flow process of this module is: software section, according to ITU G.991.2 to the regulation of SHDSL setting up procedure, the initialization of SHDSL processor experience, pretrigger, start a series of states, reach at last stable data pattern: at first, the NIOS II is as master controller, firmware downloads and the start-up course of control SHDSL processor, by the CRC check code in the firmware, detect the integrality of download firmware, after DSP started smoothly, master control sent order notice DSP and enters init state, then sent configuration parameter to DSP with the form of message, the type that wherein mainly comprises data-interface, characteristic, clock mode, DSL framing solution frame parameter, the selection of the parameter of modulating unit and principal and subordinate's end; Subsequently, NIOS II notice DSP enters pre-actuated state, at this moment, DSP is with the parameter of configuration, according to G.994.1 agreement and opposite end communication of ITU, if the parameter configuration of two ends on transmission rate, clock mode, modulating mode is consistent, shakes hands and just can finish smoothly; Then DSP shakes hands success message behind master controller in transmission, enter the nuclear starting state: in the nuclear start-up course, the DSP of principal and subordinate's end links up the data rate that obtains to shake hands, under the clock of data-interface drives, the activation signal that comes mutual ITU G.991.2 to stipulate in the agreement with the 2-PAM modulation system, principal and subordinate end all correct finish the nuclear start-up course after, DSP will formally enter data pattern: the type of the data-interface of configuration before at first passing through, the clock of characteristic and the synchronous opposite end of clock mode, then always according to ITU regulation G.991.2, the framing of complete paired data, modulation, demodulation, separate the work of frame; To the data pattern process, if there is mistake, DSP will report the master controller error reason from the pretrigger of DSP, after the NIOS II receives, DSP be put get back to init state, again finish above-mentioned start-up course operation;
When the circuit stable transfer, the NIOS II is with the input of poll UART mouth, when input message is arranged, pass to DSP with inputting the form of data with message, then DSP will input data communication device and cross the EOC passage and be sent to the opposite end, after receiving the successful message of opposite end reception, DSP also will inform master controller with form of message; Simultaneously, also can detect whether the EOC data are arranged from the SHDSL frame that receives at DSP, just send it to the NIOS II if having, the NIOS II is sent to UART with the EOC data and exports to host computer.
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| CN103780781B (en) * | 2012-10-25 | 2017-06-23 | 四川灵通电讯有限公司 | Spreading rate SHDSL transport modules |
| CN104598431A (en) * | 2014-12-19 | 2015-05-06 | 合肥彩象信息科技有限公司 | Remote positioning method based on FPGA |
| CN104410764B (en) * | 2014-12-22 | 2017-10-03 | 四川灵通电讯有限公司 | A kind of multi-thread SHDSL transport modules and implementation method to adaptive convergence |
| CN105915314B (en) * | 2016-04-14 | 2019-01-15 | 西安电子科技大学 | A kind of collaboration communication coding/decoding system and method based on Ethernet interface |
| CN106209342B (en) * | 2016-08-25 | 2022-10-18 | 四川灵通电讯有限公司 | System for realizing low-frequency clock transmission in xDSL transmission system |
| CN110336760B (en) * | 2019-05-10 | 2022-01-21 | 西南计算机有限责任公司 | Portable communication interface box system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499740A (en) * | 2002-11-05 | 2004-05-26 | 阿尔卡特公司 | General network terminal |
| CN101110739A (en) * | 2007-07-03 | 2008-01-23 | 中兴通讯股份有限公司 | Method for implementing non-standard low-speed chain building on serial high bit rate digital subscriber line |
| CN101150437A (en) * | 2007-07-30 | 2008-03-26 | 中兴通讯股份有限公司 | Processing method based on asymmetric high-speed digital line processing chip |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499740A (en) * | 2002-11-05 | 2004-05-26 | 阿尔卡特公司 | General network terminal |
| CN101110739A (en) * | 2007-07-03 | 2008-01-23 | 中兴通讯股份有限公司 | Method for implementing non-standard low-speed chain building on serial high bit rate digital subscriber line |
| CN101150437A (en) * | 2007-07-30 | 2008-03-26 | 中兴通讯股份有限公司 | Processing method based on asymmetric high-speed digital line processing chip |
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