CN101593546A - SIC (semiconductor integrated circuit) with internal voltage generating circuit - Google Patents

Abstract

The invention provides a kind of SIC (semiconductor integrated circuit) with internal voltage generating circuit.Conductor integrated circuit device comprises: RAM, i.e. random access storage device; And interior power supply circuit (10).The RAM circuit comprises a plurality of RAM circuit blocks, i.e. RAM1 to RAMn.It is the selection RAM piece that RAM1 to RAMn selects that interior power supply circuit (10) offers voltage from a plurality of RAM circuit blocks, and wherein said voltage is corresponding to the arrangement position of selecting the RAM circuit block.

Description

SIC (semiconductor integrated circuit) with internal voltage generating circuit

Technical field

The present invention relates to a kind of conductor integrated circuit device, and more specifically to a kind of conductor integrated circuit device and control method thereof with internal voltage generating circuit.

Background technology

As conductor integrated circuit device, become known for driving the LCD driver IC (hereinafter, being called as lcd driver) of display panels (hereinafter, being called as the LCD panel).Lcd driver requires to be positioned in the periphery of LCD panel., compare with the chip of the SIC (semiconductor integrated circuit) of common imagination, the chip of lcd driver requires to have the not only long but also thin unbalanced shape of length breadth ratio for this reason.

Lcd driver comprises logical circuit, high-voltage drive circuit, is used to generate the interior power supply circuit and RAM (random access storage device) circuit of builtin voltage.The RAM circuit keeps the pixel control information with control LCD panel by using builtin voltage momently.Logical circuit, high-voltage drive circuit, interior power supply circuit and RAM circuit are positioned in the arrangement zone of chip.

With respect to the chip area (layout areas) of lcd driver, wherein arranged the occupancy in zone of RAM circuit higher.The RAM circuit usually by measure unit be divided into a plurality of RAM circuit blocks, considered the performance of RAM itself and the balance between the cost for this reason.Described a plurality of RAM circuit block is connected to the power supply node (will be described after a while) that differs from one another.In described a plurality of RAM circuit each comprise cell array matrix with ram cell, based on the address circuit of address selection ram cell and from selected ram cell reading of data read amplifying circuit.When the design lcd driver,,, can easily select to be installed in the quantity of the RAM circuit block on the lcd driver therefore based on the RAM capacity of lcd driver requirement because the RAM circuit is divided into described a plurality of RAM circuit block.

When the RAM circuit block is installed in the lcd driver, there is following problem.

The RAM circuit block is its area circuit block bigger with respect to the chip size of lcd driver.The chip form of lcd driver is restricted to not only long but also thin.Under this kind restriction, owing to do not have the so much candidate region that can arrange described a plurality of RAM circuit blocks, so described a plurality of RAM circuit block is aligned to straight line usually on chip.Therefore, it is also very long to be used for internal power source voltage is supplied with the internal electric source wiring of these RAM circuit blocks.For this reason, the dead resistance of internal electric source wiring increases.Therefore, this causes occurring being supplied to the problem of very important decline of the internal power source voltage of RAM circuit block when operation RAM circuit block.

The access speed of RAM circuit block is proportional with the internal power source voltage of the RAM circuit block that is supplied to it.When internal power source voltage was higher, access speed was very fast.On the other hand, when internal power source voltage was low, access speed was slower.

In the lcd driver that comprises described a plurality of RAM circuit blocks, when the access speed of these RAM circuit blocks differed greatly, this caused going wrong, and wherein can not be used to catch the logical circuit from the output data of these RAM circuit blocks with correct sequential operation.For this reason, the internal power source voltage of supplying with each RAM circuit block is required to be designed to approximately to equate.

Equally, because described a plurality of lcd drivers are arranged at the periphery of lcd driver, so from the low cost and the low-power viewpoint of whole liquid crystal display systems, the chip size of each lcd driver and operating current are required to design as far as possible for a short time.

Will be described in the technology of describing among the Japanese Patent Application Laid-Open JP-P 2006-318380A (corresponding US application US2006259800 (A1)) below.

The Circuits System of describing in JP-P 2006-318380A comprises a plurality of circuit units, is used to provide the power supply of a plurality of different voltages, a plurality of power selection circuit and control circuit.Provide described a plurality of power selection circuit corresponding to a plurality of circuit units.Described a plurality of power selection circuit selects to be supplied to the voltage of each circuit unit from described a plurality of different voltages.Based on described a plurality of circuit units mode of operation separately, thereby control circuit is controlled the voltage that described a plurality of power selection circuit selects to be supplied to each circuit unit.Each circuit unit uses the voltage of being selected by power selection circuit as the voltage of being supplied with by internal electric source.

Will be described in the Jap.P. spy below and open JP-A-Heisei, the technology of describing among the 05-266224.

At JP-A-Heisei, the SIC (semiconductor integrated circuit) of describing among the 05-266224 comprises that the voltage that reduces outer power voltage reduces circuit and a plurality of functional module, and the voltage of these a plurality of functional modules is to reduce the voltage that circuit generates by this voltage.Reduce in order to relax the undesired voltage that generates in the dead resistance of power-supply wiring, this SIC (semiconductor integrated circuit) comprises that each the voltage of special use that is used for functional module reduces circuit.

We have found that the following fact.

As mentioned above, because lcd driver has the restriction (not only long but also thin) of chip form, therefore a plurality of RAM circuit blocks are arranged to straight line, and it is very long to be used for internal power source voltage is supplied with the internal electric source wiring of these RAM circuit blocks.The dead resistance of internal electric source wiring depends on the distance between in interior power supply circuit and the RAM circuit block each.When certain RAM circuit block is arranged at position away from interior power supply circuit,, the internal power source voltage that is supplied to described RAM circuit block is descended by the operating current of RAM circuit block and the dead resistance of internal electric source wiring.Therefore, caused the problem that the access speed of RAM circuit block is worsened.

For example, there is the individual RAM circuit block of n (n is an integer) in the let us imagination, and arrange described n RAM circuit block in the following sequence, promptly in first to n RAM circuit block, n RAM circuit block is arranged at from the nearest RAM circuit block of interior power supply circuit with between interior power supply circuit RAM circuit block farthest.The internal electric source wiring is connected to interior power supply circuit, and n RAM circuit block is connected to the internal electric source wiring in parallel.In the internal electric source wiring, generate n dead resistance as the dead resistance that corresponds respectively to the arrangement position of n RAM circuit block.That is, by connected node n RAM circuit block connected full internal electric source wiring respectively, and between the connected node of internal electric source wiring, generate and n the corresponding n of a RAM circuit block dead resistance respectively.Under these circumstances, suppose between RAM circuit block that n RAM circuit block is arranged in order has minimum dead resistance and RAM circuit block with maximum dead resistance.In order to simplify explanation, suppose that all resistance values of n dead resistance equate here.Equally, in the operating current of n RAM circuit block each is defined as Iact, and n dead resistance be defined as R1, R2, R3,---, Rn-1 and Rn, and be defined as VINT1 by the internal power source voltage that interior power supply circuit is supplied with the internal electric source wiring.

Under these circumstances, represent to be applied in the internal power source voltage VINT1far of n RAM circuit block by following equation.

VINT1far

＝VINT1-Iact×(R1+R2+R3+---+Rn-1+Rn)

Equally, represent to be applied in the internal power source voltage VINT1near of a RAM circuit block by following equation.

VINT1near＝VINT1-Iact×R1

Therefore, represent poor Δ V between the internal power source voltage of a n RAM circuit block and a RAM circuit block as described below.

ΔV＝VINT1far-VINT1near

＝Iact×(R2+R3+---+Rn-1+Rn)

Therefore, the decline of the proportional internal power source voltage of difference between generation and the dead resistance.

As mentioned above, the access speed of RAM circuit block is proportional with the internal power source voltage that is applied in the RAM circuit block.When internal power source voltage was higher, access speed was very fast, and when internal power source voltage was low, access speed was slower.Therefore, by the dead resistance of internal electric source wiring and the operating current of RAM circuit block the internal power source voltage of the RAM circuit block that is applied in the current operation is descended.This makes falling quantity of voltages depend on the arrangement position of RAM circuit block and changes.Therefore, access speed changes, and this causes following problems, wherein depends on variable quantity, and being used for catching the logical circuit of output data from these RAM circuit blocks can not be with correct sequential operation.

For head it off, can consider to reduce the dead resistance of internal electric source wiring.But when the restriction that exists such as the not only long but also thin chip form of lcd driver, very difficult employing wherein makes the internal electric source wiring layout of thicker or broad that becomes in confined area.Temporarily, if only optimize the layout of internal electric source wiring from the viewpoint of the dead resistance that minimizes internal electric source wiring, the chip size of lcd driver is caught than bigger in the past so.Therefore, there is the possibility that occurs such as the unmatched other problem of size between manufacturing cost increase and lcd driver and the LCD panel.

As for such problem, according to the technology of describing among the JP-P 2006-318380A, when operation RAM circuit block, select circuit by internal electric source, handover the connection to the different internal electric source wiring that is set to than higher in the past internal power source voltage.Therefore, the descend decline of caused access speed of the internal power source voltage that is caused by the dead resistance of internal electric source wiring is minimized.

But in the technology of describing in JP-P 2006-318380A, each RAM circuit block requires internal electric source separately to select circuit.Because each internal electric source selects circuit and each RAM circuit block to combine, so circuit scale is extended, this causes occurring the extended problem of chip size.Equally, owing to require to be used to generate the interior power supply circuit of described a plurality of internal power source voltages, so the scale of interior power supply circuit is extended, this becomes the factor that chip size enlarges.Equally, for the internal power source voltage of described a plurality of generations is supplied with the RAM circuit block, arrange a plurality of internal electric source wirings, the factor that this layout area that also becomes the internal electric source wiring increases.

According at JP-A-Heisei, the technology of describing among the 05-266224, each in the RAM circuit block has its interior power supply circuit.Therefore, not having to generate the internal power source voltage that the dead resistance by the internal electric source wiring causes descends.

But, at JP-A-Heisei, the technology existing problems of describing among the 05-266224, owing to arranged interior power supply circuit for each RAM circuit block, so chip size is extended.Equally, the quantity of interior power supply circuit is increased, the problem that this operating current that causes occurring whole lcd driver is increased.

Summary of the invention

During the present invention seeks to address the above problem one or more perhaps made improvement to these problems at least in part.

In one embodiment, a kind of conductor integrated circuit device comprises: RAM (random access storage device) circuit, and this RAM (random access storage device) circuit is constructed to comprise a plurality of RAM circuit blocks; And interior power supply circuit, this interior power supply circuit is constructed to voltage is offered the selection RAM piece of selecting from a plurality of RAM circuit blocks, and wherein said voltage is corresponding to the arrangement position of selecting the RAM circuit block.

In another embodiment, be used to drive the LCD driver of display panels, comprise: RAM (random access storage device) circuit, this RAM (random access storage device) circuit is constructed to comprise a plurality of RAM circuit blocks; And interior power supply circuit, this interior power supply circuit is constructed to voltage is offered the selection RAM piece of selecting from a plurality of RAM circuit blocks, and wherein said voltage is corresponding to the arrangement position of selecting the RAM circuit block.

According to conductor integrated circuit device of the present invention, selected the RAM circuit block.At this moment, voltage occurs and descend, wherein determine the slippage of voltage (drop-out voltage) based on internal electric source dead resistance that connects up and the operating current of selecting the RAM circuit block between interior power supply circuit and the selection RAM circuit block.Determine dead resistance and drop-out voltage based on the arrangement position of selecting the RAM circuit block.Therefore, interior power supply circuit is supplied with voltage based on the arrangement position of selecting the RAM circuit block and is selected the RAM circuit block as output voltage.Therefore, according to conductor integrated circuit device of the present invention,, do not produce undesired decline in the selection RAM circuit block in current operation as its effect.Therefore, the performance of RAM circuit block does not worsen.Promptly, even make owing to the restriction of chip form is very strict from the viewpoint of the resistance that reduces the internal electric source wiring can not designing optimal layout, also following output voltage can be offered the selection RAM circuit block that is positioned at away from interior power supply circuit, wherein with described output voltage, access speed does not reduce.

Equally, according to conductor integrated circuit device of the present invention, owing to only in the period when the RAM circuit block is selected in operation, change the output level (output voltage) of ground control interior power supply circuit, so the increase of the operating current of interior power supply circuit can be suppressed minimum value for necessity.Equally, according to conductor integrated circuit device of the present invention, the lower resistance for the internal electric source wiring becomes thicker wiring width or broad as unnecessary not requiring.Therefore, can avoid the increase of chip size, and can realize that cost reduces.

Description of drawings

In conjunction with the accompanying drawings, according to the following description of some preferred embodiment, above and other illustrative aspects of the present invention, advantage and feature will be more obvious, wherein:

Fig. 1 is the view that illustrates according to the structure of the SIC (semiconductor integrated circuit) of the first embodiment of the present invention;

Fig. 2 be illustrate according to the first and second aspects of the present invention bleeder circuit and the view of the structure example of logical circuit;

Fig. 3 A and 3B are that each all illustrates as the operation according to the conductor integrated circuit device of the first embodiment of the present invention, the output voltage of RAM circuit block activation signal, interior power supply circuit and be applied in the sequential chart of the relation between the voltage of power port;

Fig. 4 is the view that illustrates according to the structure of the variation example 1 of the conductor integrated circuit device of the first embodiment of the present invention;

Fig. 5 is the view that is illustrated in according to the structure of the example of bleeder circuit in the variation example 1 of the conductor integrated circuit device of the first embodiment of the present invention and logical circuit;

Fig. 6 is the view that illustrates according to the structure of the variation example 2 of the conductor integrated circuit device of the first embodiment of the present invention;

Fig. 7 is the view that is illustrated in according to the structure of the example of bleeder circuit in the variation example 2 of the conductor integrated circuit device of the first embodiment of the present invention and logical circuit;

Fig. 8 is the view that illustrates according to the structure of the variation example 3 of the conductor integrated circuit device of the first embodiment of the present invention;

Fig. 9 is the view that is illustrated in according to the structure of the example of bleeder circuit in the variation example 3 of the conductor integrated circuit device of the first embodiment of the present invention and logical circuit;

Figure 10 is the operation that illustrates as according to a second embodiment of the present invention conductor integrated circuit device, the access speed of RAM circuit block and put on the figure of the relation between the supply voltage of RAM circuit block;

Figure 11 is the operation that illustrates as according to a second embodiment of the present invention conductor integrated circuit device, the output voltage of RAM circuit block activation signal, interior power supply circuit and put on the sequential chart of the relation between the voltage of power port;

Figure 12 is the view of structure that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown;

Figure 13 A and 13B are the views of structure of variation example 1 that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown;

Figure 14 A and 14B are the views of structure of variation example 2 that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown; And

Figure 15 A and 15B are the views of structure of variation example 3 that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown.

Embodiment

Will the present invention be described here with reference to illustrative examples now.Those skilled in the art will appreciate that and use teaching of the present invention can finish many alternate embodiments and the invention is not restricted to be used for task of explanation and the embodiment that illustrates.

Will describe conductor integrated circuit device according to an embodiment of the invention below with reference to the accompanying drawings in detail.

(first embodiment)

[structure]

Fig. 1 is the view that illustrates according to the structure of the conductor integrated circuit device of the first embodiment of the present invention.Conductor integrated circuit device comprises logical circuit 20, be used to drive the high-voltage drive circuit (not shown) of LCD panel, be used to generate the interior power supply circuit 10 and RAM (random access storage device) circuit of builtin voltage.The RAM circuit uses builtin voltage to be kept for controlling the control information of LCD panel pixels momently.Logical circuit 20, high-voltage drive circuit, interior power supply circuit 10 and RAM circuit are arranged in the arrangement region of chip.

The RAM circuit is divided into n the RAM circuit block RAM1 to RAMn (n is an integer) as a plurality of RAM circuit blocks.This n RAM circuit block RAM1 to RAMn is connected to the power port (will describe after a while) that differs from one another respectively.Among n RAM circuit block RAM1 to RAMn each comprises cell array matrix with ram cell, be used for based on the address circuit of address selection ram cell and be used for from selecting the amplifying circuit of reading of ram cell reading of data.

Here, suppose and arrange n RAM circuit block RAM1 to RAMn in the following sequence: start from from the nearest RAM circuit block RAM1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMn farthest.The internal electric source wiring is connected to interior power supply circuit 10.

In addition, n RAM circuit block RAM1 to RAMn is connected to the internal electric source wiring in parallel.In internal electric source wiring, n dead resistance R1 to Rn appears as dead resistance respectively corresponding to the arrangement position of n RAM circuit block RAM1 to RAMn.That is, n RAM circuit block RAM1 to RAMn is connected to the internal electric source wiring respectively by n power port VINT11 to VINT1n.Then, between the power port VINT11 to VINT1n of internal electric source wiring, occur respectively respectively and corresponding n dead resistance R1 to Rn of n RAM circuit block RAM1 to RAMn.Under these circumstances, suppose that n RAM circuit block RAM1 to RAMn arranged in the following sequence: start from minimum dead resistance R1 corresponding RAM circuit block RAM1 and end at the corresponding RAM circuit block of dead resistance (R1+---+Rn) RAMn with maximum.In order to simplify description, suppose that all resistance values of n dead resistance R1 to Rn equate here.

Interior power supply circuit 10 is provided between first power supply (power supply VCC) and the second source (ground connection) of its voltage less than first power supply that is used for service voltage, and is connected to output node 11.Interior power supply circuit 10 generates internal power source voltage VINT1 and it is supplied with the internal electric source wiring as output voltage V INT1 ' by output node 11.This interior power supply circuit 10 comprises internal electric source control circuit 12 and bleeder circuit 13.

Bleeder circuit 13 is provided between output node 11 and the ground connection and comprises first resistive element 14 and second resistive element 15 that is connected in series.First resistive element 14 is provided between output node 11 and the voltage division node 16, and second resistive element 15 is provided between voltage division node 16 and the ground connection.Bleeder circuit 13 is divided internal power source voltage VINT1 and is generated the voltage FB1 that divides by first resistive element 14 and second resistive element 15, and exports it to voltage division node 16.

Internal electric source control circuit 12 comprises differential amplifier circuit 17 and switch 18.Differential amplifier circuit 17 comprises two inputs and an output.Voltage division node 16 is connected to an input in two inputs of differential amplifier circuit 17, and the voltage FB1 that divides is provided so far.Reference voltage V REF is supplied to another input in two inputs of differential amplifier circuit 17.P type MOS transistor is used as switch 18.Switch 18 is provided between power supply VCC and the output node 11, and is connected to the output of differential amplifier circuit 17 at the grid of P type MOS transistor.When being low level " L ", the signal level of the output signal of exporting from differential amplifier circuit 17 connects switch 18 (conducting state).When being high level " H ", signal level cuts off switch (nonconducting state).

To be used to provide the n signal line of RAM circuit block activation signal SEL1 to SELn to be connected to RAM circuit block RAM1 to RAMn respectively here.In addition, the n signal line also is connected to the input of logical circuit 20.The output of logical circuit 20 is connected to first resistive element 14 of the bleeder circuit 13 of interior power supply circuit 10 inside.Logical circuit 20 is supplied with bleeder circuit 13 by the voltage division control signal CVm (m is an integer, m=0 to n) that uses RAM circuit block activation signal SEL1 to SELn will describe after a while.

For example, be the situation of low level " L " from the signal level of all RAM circuit block activation signal SEL1 to SELn wherein, the signal level of a RAM circuit block activation signal is switched to high level " H ".In the present embodiment, definition is activation RAM circuit block when RAM circuit block activation signal is in high level " H ", and when RAM circuit block activation signal is in low level " L " deactivation RAM circuit block.Promptly, when all RAM circuit block RAM1 to RAMn are when being in nonselection mode, from RAM circuit block RAM1 to RAMn, select and the corresponding RAM circuit block of an aforesaid RAM circuit block activation signal (selecting the RAM circuit block), and select the RAM circuit block to become activation.

In interior power supply circuit 10, bleeder circuit 13 is divided internal power source voltage VINT1 and is generated the voltage FB1 that divides by first resistive element 14 and second resistive element 15.The voltage FB1 of differential amplifier circuit 17 benchmark voltage VREF in the internal electric source control circuit 12 and the division of output from bleeder circuit 13.If the voltage FB1 that divides is higher than reference voltage V REF, to be set to high level " H " low thereby internal power source voltage VINT1 becomes for the signal level of differential amplifier circuit 17 output signals so.Cut off switch 18 based on output signal " H ".If the voltage FB 1 that divides is lower than reference voltage V REF, so the signal level of differential amplifier circuit 17 output signals be set to low level " L " thus internal power source voltage VINT1 becomes height.Connect switch 18 based on output signal " L ".Like this, internal electric source control circuit 12 is adjusted internal power source voltage VINT1 based on voltage FB1 that divides and the comparative result between the reference voltage V REF.

As mentioned above, determine the voltage FB1 of division by the voltage division ratio between first resistive element 14 and second resistive element 15.Equally, select the RAM circuit block based on RAM circuit block activation signal SEL1 to SELn.Logical circuit 20 is supplied with bleeder circuit 13 with voltage division control signal CV0 to CVn, and wherein said voltage division control signal CV0 to CVn is provided with the voltage division ratio for the selection RAM circuit block based on RAM circuit block activation signal SEL1 to SELn.This voltage division ratio is different in RAM circuit block RAM1 to RAMn, and by which RAM circuit block is selected to determine this voltage division ratio as the fact of selecting the RAM circuit block from RAM circuit block RAM1 to RAMn.In order to be provided for selecting the voltage division ratio of RAM circuit block based on voltage division control signal CV0 to CVn, bleeder circuit 13 is adjusted the resistance value of first resistive element 14, and divide internal power source voltage VINT1 by first resistive element 14 and second resistive element 15, generate the voltage FB1 that divides then.

Fig. 2 is the view that the structure example of bleeder circuit 13 and logical circuit 20 is shown.

Logical circuit 20 comprises NOR logic gate 21.NOR logic gate 21 receives RAM circuit block activation signal SEL1 to SELn, carries out NOR (or non-) operation based on the signal level of RAM circuit block activation signal SEL1 to SELn, and exports voltage division control signal CV0 to bleeder circuit 13 as its result.Equally, logical circuit 20 exports RAM circuit block activation signal SEL1 to SELn to bleeder circuit 13 as voltage division control signal CV1 to CVn respectively.

Bleeder circuit 13 comprises first resistive element 14 and second resistive element 15, as mentioned above.First resistive element 14 is provided between output node 11 and the voltage division node 16.Second resistive element 15 is provided between voltage division node 16 and the ground connection.First resistive element 14 comprises (n+1) the individual current path parts that is connected in parallel between output node 11 and the voltage division node 16.In this (n+1) individual current path parts, the 0th current path parts comprises the transmission gate G20 that is provided between output node 11 and the voltage division node 16.First current path parts comprises: a resistor R B1 who is installed between output node 11 and the voltage division node 16; And be provided at transmission gate G21 between resistor R B1 and the voltage division node 16.Second current path parts is provided between output node 11 and the voltage division node 16 and comprises: two first to second resistor R B1 that are connected in series; And be provided at transmission gate G22 between the second resistor R B1 and the voltage division node 16.Remaining and top similar.Then, the n current path parts is provided between output node 11 and the voltage division node 16 and comprises: the n that is connected in series individual first is to n resistor R B1; And be provided at transmission gate G2n between n resistor R B1 and the voltage division node 16.Among the transmission gate G20 to G2n each is provided with the phase inverter between the grid of the grid of N type MOS transistor, P type MOS transistor and N type MOS transistor and P type MOS transistor.When the signal level of RAM circuit block activation signal SEL1 to SELn is high level " H ", connect transmission gate G20 to G2n respectively.In (n+1) individual current path parts, first corresponds respectively to RAM circuit block RAM1 to RAMn to the n current path parts.

As mentioned above, when being the situation of low level " L " from the signal level of all RAM circuit block activation signal SEL1 to SELn wherein, when the signal level of a RAM circuit block activation signal is switched to high level " H ", select and the corresponding RAM circuit block of an aforesaid RAM circuit block activation signal (selecting the RAM circuit block) from RAM circuit block RAM1 to RAMn.Under these circumstances, in the middle of (n+1) individual current path parts, connect and the transmission gate (conduction state) of selecting the corresponding current path parts of RAM circuit block (selection current path parts).

[operation]

As the operation according to the conductor integrated circuit device of the first embodiment of the present invention, in order to simplify description, the quantity of having described the RAM circuit block in the wherein current operation is one situation.Here, the operating current of RAM circuit block is defined as Iact.

At first, situation about wherein selecting from the nearest RAM circuit block RAM1 of interior power supply circuit 10 has been described.

When the signal level of all RAM circuit block activation signal SEL1 to SELn was low level " L ", the signal level of the NOR logic gate 21 voltage division control signal CV0 by logical circuit 20 inside was set to high level " H ".For this reason, in first resistive element 14 of the bleeder circuit 13 of interior power supply circuit 10, the transmission gate G20 of the 0th current path parts is in conducting state.Because the signal level of other voltage division control signal CV1 to CVm is low level " L ", transmission gate G21 to G2n is in nonconducting state.At this moment, as the voltage FB1 that divides, internal power source voltage VINT1 is supplied to voltage division node 16.Therefore, when not selecting the RAM circuit block, the internal electric source control circuit 12 in the interior power supply circuit 10 is set to the voltage identical with reference voltage V REF as the internal power source voltage VINT1 of its output voltage V INT1 '.

Next, in order to select RAM circuit block RAM1, the signal level of RAM circuit block activation signal SEL1 is switched to high level " H ".At this moment, RAM circuit block RAM1 is activated.Equally, by NOR logic gate 21 in the logical circuit 20, the signal level of voltage division control signal CV0 is switched to low level " L ".For this reason, in first resistive element 14 of the bleeder circuit 13 of interior power supply circuit 10, cut off the transmission gate G20 of the 0th current path parts.Because the signal level of RAM circuit block activation signal SEL1 is high level " H ", so connect the transmission gate G21 of first current path parts.Transmission gate G22 to G2n is in nonconducting state.At this moment, bleeder circuit 13 is switched to by the resistor R B1 of first current path parts and the voltage division ratio of determining as the ratio between the resistor R B2 of second resistive element 15.Therefore, when selecting RAM circuit block RAM1, become ((RB1+RB2)/RB2) with respect to the voltage division ratio of RAM circuit block RAM1.Then, 12 outputs of internal electric source control circuit in the interior power supply circuit 10 than the high internal power source voltage VINT1 of reference voltage V REF as output voltage V INT1 ', VINT1 '=VREF * ((RB1+RB2)/RB2) wherein.

When having selected the RAM circuit block, based on interior power supply circuit with select the dead resistance of the internal electric source wiring between the power port of RAM circuit block and select the operating current of RAM circuit block to determine to want the degree of reformed magnitude of voltage.

When selecting RAM circuit block RAM1, with (the Iact * R1) accordingly, generate drop-out voltage that multiply by the corresponding dead resistance R1 acquisition of the RAM circuit block RAM1 that connects up with internal electric source by operating current Iact with RAM circuit block RAM1.Therefore, as for the voltage of the power port VINT11 that is applied to RAM circuit block RAM1, from being that the internal power source voltage VINT1 of the output voltage of interior power supply circuit 10 descends and (the corresponding drop-out voltage of Iact * R1).Therefore, when selecting RAM circuit block RAM1, change to height corresponding to the output voltage of this time general who has surrendered interior power supply circuit 10.That is, when selecting RAM circuit block RAM1, the value of determining resistor R B1 makes the voltage division ratio of bleeder circuit 13 corresponding to the voltage change of being wanted.Under these circumstances, the value of determining resistor R B1 makes the output voltage V INT1 ' of interior power supply circuit 10 become following voltage, wherein with (Iact * R1) corresponding drop-out voltage is added into internal power source voltage VINT1, that is, (VINT1+ (Iact * R1)).

Therefore, when selecting RAM circuit block RAM1, interior power supply circuit 10 outputs (VINT1+ (Iact * R1)) are as its output voltage V INT1 '.Therefore, even generate decline by the dead resistance of internal electric source wiring and the operating current of RAM circuit block itself, voltage VINT1 also is applied to the power port VINT11 of RAM circuit block RAM1.Like this,, also can obtain lcd driver, wherein not worsen the access speed of RAM circuit block RAM1 even the voltage that the dead resistance that existence is connected up by internal electric source causes descends.

The situation of selection when farthest RAM circuit block RAMn of interior power supply circuit 10 will be described below.

In order to select RAM circuit block RAMn, the signal level of RAM circuit block activation signal SELn is switched to high level " H ".At this moment, RAM circuit block RAMn is activated.Equally, by the NOR logic gate 21 of logical circuit 20 inside, the signal level of voltage division control signal CV0 is set to low level " L ".Therefore, in first resistive element 14 of the bleeder circuit 13 in interior power supply circuit 10, cut off the transmission gate G20 of the 0th current path parts.Because the signal level of RAM circuit block activation signal SELn is high level " H ", so connect the transmission gate G2n of n current path parts.Transmission gate G21 to G2n-1 is in nonconducting state.At this moment, bleeder circuit 13 is switched by n resistor R B1 of n current path parts and the voltage division ratio of determining as the ratio between the resistor R B2 of second resistive element 15.Therefore, when selecting RAM circuit block RAMn, become (((RB1 * n)+RB2)/RB2) with respect to the voltage division ratio of RAM circuit block RAMn.Internal electric source control circuit 12 output VINT1 '=VREF in the interior power supply circuit 10 (((RB1 * n)+RB2)/RB2) as output voltage V INT1 '.Under these circumstances, when selecting RAM circuit block RAM1, output voltage V INT1 ' is higher than output voltage V INT1 '=VREF (voltage of (RB1+RB2)/RB2).

When selecting RAM circuit block RAMn, with (Iact * (R1+R2+R3+---+Rn-1+Rn) generate drop-out voltage accordingly wherein will multiply by the operating current Iact of RAM circuit block RAMn with the corresponding dead resistance of RAM circuit block RAMn (R1+R2+R3+---+Rn-1+Rn) of internal electric source wiring.Therefore, as for the voltage of the power port VINT1n that is applied to RAM circuit block RAMn, from being that the internal power source voltage VINT1 of the output voltage of interior power supply circuit 10 descends and (Iact * (R1+R2+R3+--+Rn-1+Rn)) corresponding drop-out voltage.Therefore, when selecting RAM circuit block RAMn, descend, the output voltage of interior power supply circuit 10 is changed to height corresponding to this.That is, when selecting RAM circuit block RAM1, (value of RB1 * n) makes the voltage division ratio of bleeder circuit 13 corresponding to the voltage change of being wanted can to determine resistor.Under these circumstances, (value of RB1 * n) makes the output voltage V INT1 ' of interior power supply circuit 10 become following voltage to determine resistor, wherein be added into internal power source voltage VINT1 with (Iact * (R1+R2+R3+---+Rn-1+Rn)) corresponding drop-out voltage, promptly, (VINT1+ (Iact * (R1+R2+R3+---+Rn-1+Rn)).

Therefore, when selecting RAM circuit block RAMn, interior power supply circuit 10 output VINT1+ (Iact * (R1+R2+R3+---+Rn-1+Rn)) as its output voltage V INT1 '.Therefore, even generate decline by the dead resistance of internal electric source wiring and the operating current of RAM circuit block itself, voltage VINT1 also is applied to the power port VINT1n of RAM circuit block RAMn.Like this, promptly very big even the time even the voltage that is caused by the dead resistance of internal electric source wiring descends away from the position arrangement RAM circuit block of interior power supply circuit 10, also can obtain the lcd driver that the access speed of RAM circuit block RAMn wherein not have deterioration.

Fig. 3 A is the operation that illustrates as according to the conductor integrated circuit device of the first embodiment of the present invention, the output voltage V INT1 ' of RAM circuit block activation signal SEL1 to SELn, interior power supply circuit 10 and be applied to the sequential chart of the relation between the voltage of power port VINT11 to VINT1n.Here, the transverse axis express time, Z-axis is represented voltage, and " VCCINT " is corresponding to internal power source voltage VINT1.Change the output voltage V INT1 ' of interior power supply circuit 10 according to the operational state change ground of RAM circuit block.When the RAM circuit block of selecting and operate was RAM circuit block RAM1, control consistently was applied to the output voltage V INT1 ' of power port VINT11 to VINT1n and does not descend.

First embodiment has been described about being arranged at from the RAM circuit block RAM1 of the nearest position of interior power supply circuit 10 and being arranged at from the RAM circuit block RAMn of interior power supply circuit 10 position farthest.Similarly, under the same mode of thinking, as shown in Fig. 3 B, the present invention can also be applied to being arranged at the RAM circuit block RAM2 to RAMn-1 between them.

[effect]

Effect according to the conductor integrated circuit device of the first embodiment of the present invention will be described below.

Conductor integrated circuit device according to the first embodiment of the present invention comprises: the RAM circuit that is divided into RAM circuit block RAM1 to RAMn; With interior power supply circuit 10.Select the RAM circuit block from RAM circuit block RAM1 to RAMn.At this moment, voltage occurs and descend, wherein, based on the dead resistance of the internal electric source wiring between interior power supply circuit 10 and the selection RAM circuit block; Determine the slippage of voltage (drop-out voltage) with the operating current of selecting the RAM circuit block.Determine dead resistance and drop-out voltage in the arrangement position of selecting the RAM circuit block.Therefore, interior power supply circuit 10 will be selected the RAM circuit block as output voltage V INT1 ' supply based on the voltage of the arrangement position of selecting the RAM circuit block.Therefore, according to the conductor integrated circuit device of the first embodiment of the present invention,, in current operation, do not generate undesired decline for selection RAM circuit block as its effect.Therefore, do not worsen the performance of RAM circuit block RAM1 to RAMn.Promptly, even because the restriction on chip form is strict, from the resistance viewpoint that reduces the internal electric source wiring can not designing optimal layout, the output voltage V INT1 ' that also can not reduce access speed supplies with the selection RAM memory circuitry piece away from interior power supply circuit 10.Equally, conductor integrated circuit device according to the first embodiment of the present invention, owing to only change the output level (output voltage V INT1 ') of ground control interior power supply circuit 10 in the period when selecting RAM memory circuitry piece, so the increase in the operating current of interior power supply circuit 10 can be suppressed to necessary minimum value when operation.Equally, according to the conductor integrated circuit device of the first embodiment of the present invention, and compared in the past, the lower resistance for the internal electric source wiring does not require wiring width thickening (wide) as unnecessary.Therefore, avoid the increase of chip size, and realize that cost reduces.

According to the conductor integrated circuit device of the first embodiment of the present invention, arrange RAM circuit block RAM1 to RAMn in order: start from from the nearest RAM circuit block RAM1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMn farthest.As mentioned above, for RAM circuit block RAM1 to RAMn, generate drop-out voltage accordingly with their arrangement position.Therefore, in order to reach aforesaid effect, in interior power supply circuit 10, be each setting and the corresponding n of a dead resistance voltage among the RAM circuit block RAM1 to RAMn.That is, increase n voltage in order: start from the minimum corresponding voltage of dead resistance (R1) and end at the corresponding voltage of dead resistance (R1+---+Rn) with maximum.In the present embodiment, increase n voltage in order: start from from the nearest voltage of interior power supply circuit 10 and end at from interior power supply circuit 10 voltage farthest.When selecting the RAM circuit block, interior power supply circuit 10 is selected the RAM circuit block with the voltage based on the position of selecting the RAM circuit block in n the voltage as output voltage V INT1 ' supply.Therefore, according to the conductor integrated circuit device of the first embodiment of the present invention, can reach aforesaid effect.

Conductor integrated circuit device according to the first embodiment of the present invention, in order further to reach aforesaid effect, interior power supply circuit 10 comprises bleeder circuit 13, and this bleeder circuit 13 can generate n the voltage division ratio (first resistive element 14 ((n+1) individual current path parts) and second resistive element 15) that is used to be provided with n voltage.Here, n voltage division ratio (first to the n current path parts and second resistive element 15) corresponds respectively to RAM circuit block RAM1 to RAMn.When selecting the RAM circuit block, interior power supply circuit 10 is selected from n voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio, and with in the middle of n the voltage with select the corresponding voltage of voltage division ratio as output voltage V INT1 ' supply selection RAM circuit block.Therefore, according to the conductor integrated circuit device of the first embodiment of the present invention, can obtain aforesaid effect.

According to the conductor integrated circuit device of the first embodiment of the present invention, when selecting RAM circuit block RAM1 to RAMn, RAM circuit block activation signal SEL1 to SELn is supplied to RAM circuit block RAM1 to RAMn respectively.Therefore, in order to obtain aforesaid effect, logical circuit 20 selects the RAM circuit block activation signal of RAM circuit block will be used to select and select the voltage division control signal CVm of the corresponding selection voltage division of RAM circuit block ratio to export bleeder circuit 13 to based on being used to.At this moment, bleeder circuit 13 is selected from n voltage division ratio based on voltage division control signal CVm and is selected the corresponding selection voltage division of RAM circuit block ratio.Interior power supply circuit 10 with in the middle of n the voltage with select the corresponding voltage of voltage division ratio as output voltage V INT1 ' supplys selection RAM circuit block.Therefore, according to the conductor integrated circuit device of the first embodiment of the present invention, can obtain aforesaid effect.

According to the conductor integrated circuit device of the first embodiment of the present invention, interior power supply circuit 10 is connected to the internal electric source wiring and generates internal power source voltage VINT1.In order RAM circuit block RAM1 to RAMn is connected in parallel internal electric source wiring: start from from the nearest RAM circuit block RAM1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMn farthest.In the internal electric source wiring, generate arrangement place corresponding dead resistance R1 to Rn respectively with RAM circuit block RAM1 to RAMn.When selecting respectively and operate RAM circuit block RAM1 to RAMn, in RAM circuit block RAM1 to RAMn, generate respectively by the operating current of RAM circuit block RAM1 to RAMn and the dead resistance between interior power supply circuit 10 and the RAM circuit block RAM1 to RAMn and cause n drop-out voltage.Therefore, in order further to obtain aforesaid effect, n voltage is the voltage that has wherein added internal power source voltage VINT1 and n drop-out voltage respectively.

Particularly, the resistance value of dead resistance R1 to Rn that corresponds respectively to the arrangement place of RAM circuit block RAM1 to RAMn is defined as R1 to Rn.The current value of the operating current of each among the RAM circuit block RAM1 to RAMn is defined as Iact.The magnitude of voltage of internal power source voltage VINT1 is defined as VINT1.Equally, select the RAM circuit block to be defined as jRAM circuit block RAMj.Here, j is an integer, is equal to, or greater than 1 and be equal to or less than n.Equally, in the middle of n voltage, the voltage that is used for jRAM circuit block RAMj is defined as output voltage V INT1 '.Under these circumstances, by following equation (1) expression output voltage V INT1 '.

[equation 1]

$\mathrm{<figure-callout\; id="1"\; label="VINT"\; filenames="A2009101456340048H1.png,A2009101456340049H1.png"\; state="\{\{state\}\}">VINT</figure-callout>}{1}^{\&prime;}=\mathrm{<figure-callout\; id="1"\; label="VINT"\; filenames="A2009101456340048H1.png,A2009101456340049H1.png"\; state="\{\{state\}\}">VINT</figure-callout>}1+(\mathrm{Iact}\&times;\underset{i=1}{\overset{j}{\mathrm{\&Sigma;}}}\mathrm{Ri})$

Therefore, according to the conductor integrated circuit device of the first embodiment of the present invention, can obtain aforesaid effect.

Explanation in passing, in conductor integrated circuit device, following mechanism has been described, wherein according to the first embodiment of the present invention, for n the RAM circuit block that is provided in the lcd driver, based on the output voltage V INT1 ' that selects the RAM circuit block with n level control interior power supply circuit 10.But, be not limited thereto kind of a situation.As variation example, can in the scope of internal power source voltage of allowing and access speed, reduce control progression (in Figure 10, will describe situation) according to the conductor integrated circuit device of the first embodiment of the present invention.

Variation example according to the conductor integrated circuit device of the first embodiment of the present invention has been described here.

Fig. 4 is the view that illustrates according to the structure of the variation example 1 of the conductor integrated circuit device of the first embodiment of the present invention.Fig. 5 illustrates the view that changes the structure of the example of bleeder circuit 13 and logical circuit 20 in the example 1.

In variation example 1 according to the conductor integrated circuit device of the first embodiment of the present invention, suppose that first to n (n is an integer) RAM circuit block RAM1 to RAMn forms the individual RAM circuit block group of x (x is the integer less than n), and N RAM circuit block belongs in x the RAM circuit block group each.Here, N is the integer that satisfies n=x * N.Therefore, when definition during N=2, x RAM circuit block group be expressed as respectively RAM circuit block RAM1 to RAM2, RAM3 to RAM4,---and RAMn-1 to RAMn.Arrange in order these RAM circuit blocks RAM1 to RAM2,---and RAMn-1 to RAMn: start from from the nearest RAM circuit block RAM1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMn farthest.Under these circumstances, in the internal electric source wiring that is connected to interior power supply circuit 10, correspond respectively to RAM circuit block RAM1 to RAM2,--and the arrangement of RAMn-1 to RAMn ground dot generation dead resistance R1 to R2,---and Rn-1 to Rn.Therefore, for RAM circuit block RAM1 to RAM2,---and RAMn-1 to RAMn corresponding to their arrangement place, generates drop-out voltage.Therefore, in order to obtain aforesaid effect, in interior power supply circuit 10, for RAM circuit block RAM1 to RAM2,---and RAMn-1 to RAMn in each (each in the RAM circuit block group) be provided with and the corresponding x of dead resistance voltage.That is, increase x voltage in order: start from the minimum corresponding voltage of dead resistance (R1+R2) and end at the corresponding voltage of dead resistance (R1+---+Rn) with maximum.In the present embodiment, increase x voltage in order: start from from the nearest voltage of interior power supply circuit 10 and end at from interior power supply circuit 10 voltage farthest.When selecting the RAM circuit block, interior power supply circuit 10 will be selected the RAM circuit block with the corresponding voltage in position of selecting the RAM circuit block as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, according to the variation example 1 of the conductor integrated circuit device of the first embodiment of the present invention, control progression can be reduced to x (x=(1/2) * n) from n.

In variation example 1 according to the conductor integrated circuit device of the first embodiment of the present invention, in order further to obtain aforesaid effect, interior power supply circuit 10 comprises bleeder circuit 13, and this bleeder circuit 13 can generate x voltage division ratio (first resistive element 14 ((x+1) individual current path parts) and second resistive element 15) so that x voltage to be set.Here, x voltage division ratio (first to the x current path parts and second resistive element 15) correspond respectively to RAM circuit block RAM1 to RAM2,---and RAMn-1 to RAMn.When selecting the RAM circuit block, interior power supply circuit 10 is selected from x voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio, and will select the RAM circuit block with selecting the corresponding voltage of voltage division ratio as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 1 according to the conductor integrated circuit device of the first embodiment of the present invention can obtain aforesaid effect.

In variation example 1 according to the conductor integrated circuit device of the first embodiment of the present invention, when RAM circuit block RAM1 to RAM2,---and RAMn-1 to RAMn when selected, RAM circuit block activation signal SEL1 to SEL2,--and SELn-1 to SELn supplied with respectively RAM circuit block RAM1 to RAM2,---and RAMn-1 to RAMn.Particularly, as shown in Figure 5, logical circuit 20 further comprises: NOR logic gate 22-1 to 22-x; And phase inverter (inverse gate) 23-1 to 23-x.NOR logic gate 22-1 to 22-x receive respectively RAM circuit block activation signal SEL1 to SEL2,---and SELn-1 to SELn.NOR logic gate 22-1 to 22-x based on RAM circuit block activation signal SEL1 to SEL2,---and the signal level of SELn-1 to SELn carry out NOR (or non-) operation respectively.Afterwards, NOR logic gate 22-1 to 22-x exports their result to phase inverter 23-1 to 23-x respectively.Phase inverter 23-1 to 23-x changes aforesaid result and exports it to NOR logic gate 21.Phase inverter 23-1 to 23-x also exports their transformation result to bleeder circuit 13 respectively as voltage division control signal CV2 to CVn.NOR logic gate 21 receives voltage division control signal CV2 to CVn, carries out the NOR operation based on the signal level of voltage division control signal CV2 to CVn, exports voltage division control signal CV0 to bleeder circuit 13 as its result then.First resistive element 14 in the bleeder circuit 13 comprises (x+1) individual current path parts, should (x+1) individual current path parts be connected in parallel so that x voltage to be set.Therefore, in order to obtain aforesaid effect, based on the RAM circuit block activation signal that is used to select the RAM circuit block, logical circuit 20 will be used to select and select the voltage division control signal CVm of the corresponding selection voltage division of RAM circuit block ratio to export bleeder circuit 13 to.At this moment, based on voltage division control signal CVm, bleeder circuit 13 is selected from x voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio.Interior power supply circuit 10 will be selected the RAM circuit block with selecting the corresponding voltage of voltage division ratio as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 1 according to the conductor integrated circuit device of the first embodiment of the present invention can obtain aforesaid effect.

Fig. 6 is the view that illustrates according to the structure of the variation example 2 of the conductor integrated circuit device of the first embodiment of the present invention.Fig. 7 is the view of structure that the example of the bleeder circuit 13 that changes in the example 2 and logical circuit 20 is shown.

In variation example 2 according to the conductor integrated circuit device of the first embodiment of the present invention, suppose that first to n (n is an integer) RAM circuit block RAM1 to RAMn forms the individual RAM circuit block group of x (x is the integer less than n), and N RAM circuit block belongs in x the RAM circuit block group each.Here, N is the integer that satisfies n=x * N.Therefore, when having defined N=4, x RAM circuit block group be expressed as respectively RAM circuit block group RAM1 to RAM4, RAM5 to RAM8,---and RAMn-3 to RAMn.Arrange in order RAM circuit block RAM1 to RAM4,---and RAMn-3 to RAMn: start from from the nearest RAM circuit block RAM1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMn farthest.Under these circumstances, in the internal electric source wiring that is connected to interior power supply circuit 10, correspond respectively to RAM circuit block RAM1 to RAM4,--and the arrangement of RAMn-3 to RAMn ground dot generation dead resistance R1 to R4,---and Rn-3 to Rn.Therefore, for RAM circuit block RAM1 to RAM4,---and RAMn-3 to RAMn produces drop-out voltage corresponding to their arrangement place.Therefore, in order to obtain aforesaid effect, in interior power supply circuit 10, for RAM circuit block RAM1 to RAM4,---and RAMn-3 to RAMn in each (each in the RAM circuit block group) be provided with a voltage with the corresponding x of dead resistance.That is, increase x voltage in order: start from the minimum corresponding voltage of dead resistance (R1+R2+R3+R4) and end at the corresponding voltage of dead resistance (R1+---+Rn) with maximum.In the present embodiment, increase x voltage in order: start from from the nearest voltage of interior power supply circuit 10 and end at from interior power supply circuit 10 voltage farthest.When selecting the RAM circuit block, interior power supply circuit 10 is selected the RAM circuit block with the corresponding voltage in position with selection RAM circuit block in the middle of x the voltage as output voltage V INT1 ' supply.Therefore, according to the variation example 2 of the conductor integrated circuit device of the first embodiment of the present invention, control progression can be reduced to x (x=(1/4) * n) from n.

In variation example 2 according to the conductor integrated circuit device of the first embodiment of the present invention, in order further to obtain aforesaid effect, interior power supply circuit 10 comprises bleeder circuit 13, and this bleeder circuit 13 can generate x voltage division ratio (first resistive element 14 ((x+1) individual current path parts) and second resistive element 15) so that x voltage to be set.Here, x voltage division ratio (first to the x current path parts and second resistive element 15) correspond respectively to RAM circuit block RAM1 to RAM4,---and RAMn-3 to RAMn.When selecting the RAM circuit block, interior power supply circuit 10 is selected from x voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio, and will select the RAM circuit block with selecting the corresponding voltage of voltage division ratio as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 2 according to the conductor integrated circuit device of the first embodiment of the present invention can obtain aforesaid effect.

In variation example 2 according to the conductor integrated circuit device of the first embodiment of the present invention, when select RAM circuit block RAM1 to RAM4,---and during RAMn-3 to RAMn, RAM circuit block activation signal SEL1 to SEL4,--and SELn-3 to SELn supplied with respectively RAM circuit block RAM1 to RAM4,---and RAMn-3 to RAMn.Particularly, as shown in Figure 7, logical circuit 20 further comprises: NOR logic gate 22-1 to 22-x; And phase inverter (inverse gate) 23-1 to 23-x.NOR logic gate 22-1 to 22-x receive respectively RAM circuit block activation signal SEL1 to SEL4,---and SELn-3 to SELn.Then, NOR logic gate 22-1 to 22-x respectively based on RAM circuit block activation signal SEL1 to SEL4,---and the signal level of SELn-3 to SELn carry out the NOR operation.Then, NOR logic gate 22-1 to 22-x exports their result to phase inverter 23-1 to 23-x respectively.Phase inverter 23-1 to 23-x changes aforesaid result and exports NOR logic gate 21 to.Phase inverter 23-1 to 23-x also exports their transformation result to bleeder circuit 13 respectively as voltage division control signal CV4 to CVn.NOR logic gate 21 receives voltage division control signal CV4 to CVn, carries out the NOR operation based on the signal level of voltage division control signal CV4 to CVn, exports voltage division control signal CV0 to bleeder circuit 13 as its result then.First resistive element 14 in the bleeder circuit 13 comprises and being connected in parallel so that (x+1) individual current path parts of x voltage to be set.Therefore, in order further to obtain aforesaid effect, based on the RAM circuit block activation signal that is used to select the RAM circuit block, logical circuit 20 will be used to select and select the voltage division control signal CVm of the corresponding selection voltage division of RAM circuit block ratio to export bleeder circuit 13 to.At this moment, based on voltage division control signal CVm, bleeder circuit 13 is selected from x voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio.Interior power supply circuit 10 will be selected the RAM circuit block with selecting the corresponding voltage of voltage division ratio as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 2 according to the conductor integrated circuit device of the first embodiment of the present invention can obtain aforesaid effect.

Fig. 8 is the view that illustrates according to the structure of the variation example 3 of the conductor integrated circuit device of the first embodiment of the present invention.Fig. 9 is the view of structure that the example of the bleeder circuit 13 that changes in the example 3 and logical circuit 20 is shown.

In variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention, suppose that first to n (n is an integer) RAM circuit block RAM1 to RAMn forms the individual RAM circuit block group of x (x is the integer less than n), and each the number of RAM circuit block that belongs in x the RAM circuit block group differs from one another.For example, x RAM circuit block group be expressed as respectively RAM circuit block group RAM1, RAM2 to RAM4,---and RAMn-3 to RAMn.Arrange in order RAM1, RAM2 to RAM4,---and RAMn-3 to RAMn: start from from the nearest RAM circuit block RAM1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMn farthest.Under these circumstances, in the internal electric source wiring that is connected to interior power supply circuit 10, correspond respectively to RAM circuit block RAM1, RAM2 to RAM4,--and the arrangement of RAMn-3 to RAMn ground dot generation dead resistance R1, R2 to R4,---and Rn-3 to Rn.Therefore, for RAM circuit block RAM1, RAM2 to RAM4,---and RAMn-3 to RAMn generates drop-out voltage accordingly with their arrangement place.Therefore, in order to obtain aforesaid effect, in interior power supply circuit 10, for RAM circuit block RAM1, RAM2 to RAM4,---and RAMn-3 to RAMn in each (each in the RAM circuit block group) be provided with a voltage with the corresponding x of dead resistance.That is, increase x voltage in order: start from the minimum corresponding voltage of dead resistance (R1) and end at the corresponding voltage of dead resistance (R1+---+Rn) with maximum.In the present embodiment, increase x voltage in order: start from from the nearest voltage of interior power supply circuit 10 and end at from interior power supply circuit 10 voltage farthest.When selecting the RAM circuit block, interior power supply circuit 10 will be selected the RAM circuit block with the corresponding voltage in position of selecting the RAM circuit block as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention can reduce to x from n with the quantity of controlled step.

In variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention, in order further to obtain aforesaid effect, interior power supply circuit 10 comprises bleeder circuit 13, and this bleeder circuit 13 can generate x voltage division ratio (first resistive element 14 ((x+1) individual current path parts) and second resistive element 15) so that x voltage to be set.Here, x voltage division ratio (first to the x current path parts and second resistive element 15) correspond respectively to RAM circuit block RAM1, RAM2 to RAM4,---and RAMn-3 to RAMn.When selecting the RAM circuit block, interior power supply circuit 10 is selected from x voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio, and will select the RAM circuit block with selecting the corresponding voltage of voltage division ratio as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention can obtain aforesaid effect.

In variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention, when select RAM circuit block RAM1, RAM2 to RAM4,---and during RAMn-3 to RAMn, RAM circuit block activation signal SEL1, SEL2 to SEL4,--and SELn-3 to SELn supplied with respectively RAM circuit block RAM1, RAM2 to RAM4,---and RAMn-3 to RAMn.Particularly, as shown in Figure 9, logical circuit 20 further comprises: NOR logic gate 22-1 to 22-y (in this case, y is the integer that satisfies y=x+1) and phase inverter (inverse gate) 23-1 to 23-y.In this case, logical circuit 20 exports RAM circuit block activation signal SEL1 to NOR logic gate 21 and bleeder circuit 13 as voltage division control signal CV1.NOR logic gate 22-1 to 22-y receive respectively RAM circuit block activation signal SEL2 to SEL4,---and SELn-3 to SELn.Then, NOR logic gate 22-1 to 22-y respectively based on RAM circuit block activation signal SEL2 to SEL4,---and the signal level of SELn-3 to SELn carry out the NOR operation.Then, NOR logic gate 22-1 to 22-y exports their result to phase inverter 23-1 to 23-y respectively.Phase inverter 23-1 to 23-y changes aforesaid result and exports NOR logic gate 21 to.Phase inverter 23-1 to 23-y also exports their transformation result to bleeder circuit 13 respectively as voltage division control signal CV4 to CVn.NOR logic gate 21 receives voltage division control signal CV1, CV4 to CVn, carries out the NOR operation based on the signal level of voltage division control signal CV1, CV4 to CVn, exports voltage division control signal CV0 to bleeder circuit 13 as its result then.First resistive element 14 in the bleeder circuit 13 comprises by in parallel so that the individual current path parts of x voltage (x+1) to be set.Therefore, in order further to obtain aforesaid effect, based on the RAM circuit block activation signal that is used to select the RAM circuit block, logical circuit 20 will be used to select and select the voltage division control signal CVm of the corresponding selection voltage division of RAM circuit block ratio to export bleeder circuit 13 to.At this moment, based on voltage division control signal CVm, bleeder circuit 13 is selected from x voltage division ratio and is selected the corresponding selection voltage division of RAM circuit block ratio.Interior power supply circuit 10 will be selected the RAM circuit block based on the voltage of selecting the voltage division ratio as output voltage V INT1 ' supply in the middle of x the voltage.Therefore, the variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention can obtain aforesaid effect.

In variation example 3 according to the conductor integrated circuit device of the first embodiment of the present invention, with have one, three,--, sequence arrangement RAM circuit block RAM1, RAM2 to RAM4 that the RAM circuit block group of four RAM circuit blocks is the same,---and RAMn-3 to RAMn respectively.But they are not limited thereto kind of a situation.The value that can depend on dead resistance changes these orders.

(second embodiment)

About the quantity of the current RAM circuit block of operating wherein is that one situation has been described first embodiment.But, conductor integrated circuit device has according to a second embodiment of the present invention been described about the situation that wherein has current a plurality of RAM circuit blocks of operating simultaneously.In a second embodiment, omitted the explanation that repeats with first embodiment.

[structure]

The structure of conductor integrated circuit device according to a second embodiment of the present invention and first embodiment's is similar.

[operation]

As the operation of according to a second embodiment of the present invention conductor integrated circuit device,, the situation that wherein has current two RAM circuit blocks operating has been described in order to simplify description.Here, the operating current of a RAM circuit block is defined as Iact.

In order to select RAM circuit block RAM1, RAM2, the signal level of RAM circuit block activation signal SEL1, SEL2 is switched into high level " H ".At this moment, RAM circuit block RAM1, RAM2 are activated.

Voltage FB1 that interior power supply circuit 10 is relatively divided and reference voltage V REF and adjustment internal power source voltage VINT1.As for the voltage FB1 that divides, by its voltage division ratio of voltage division control signal CV0 to CVm control from logical circuit 20 outputs.Described in first embodiment, in the period when selecting and operate the RAM circuit block, based on the slippage of the internal power source voltage when operating the RAM circuit block, interior power supply circuit 10 internal power source voltage VINT1 are set to height.Therefore, when a plurality of RAM circuit block of operation, require to determine the recruitment of change in voltage based on the balance between the whole performance of the performance of RAM circuit block and lcd driver.Below principle will be described.

Figure 10 is the figure that the access speed of RAM circuit block is shown and is applied to the relation between the supply voltage of RAM circuit block.Transverse axis is represented power source voltage Vcc int, and Z-axis is represented access speed tacc.The negative internal power source voltage dependence of the access speed of following oblique line (from left to bottom right) expression RAM circuit block.Symbol Vccint1 represents the lower limit based on the definite internal power source voltage of access speed.Symbol Vccint2 represents to allow in order to ensure structure transistorized life-span of circuit and reliability to be applied to the upper limit of the internal power source voltage of RAM circuit block.Symbol Δ Vccint represents the variable quantity of allowing of internal power source voltage Vccint.That is, Δ Vccint represents the upper limit of the scope of internal power source voltage Vccint.Symbol tacc1 represents the lower limit in order to ensure the access speed of the RAM circuit block of the performance of lcd driver.Symbol tacc2 represents the upper limit in order to ensure the access speed of the RAM circuit block of the performance of lcd driver.Symbol Δ Vtacc represents the variable quantity of allowing of the access speed tacc of RAM circuit block, this variable quantity is allowed for data being exported to the logical circuit that RAM circuit block and reception come from the data of RAM circuit block.That is, Δ Vtacc represents the upper limit of scope of the access speed tacc of RAM circuit block.

In the RAM circuit block, exist based on the access speed changes delta Vtacc that allows and definite internal power source voltage changes delta Vccint that allows.When operating a plurality of RAM circuit block simultaneously, the decline compensation rate of internal power source voltage (drop-out voltage) can be defined as making in the scope of the internal power source voltage of allowing and the access speed of allowing, descending.

Usually, in lower internal power source voltage, in many cases, the RAM circuit block has the less surplus relevant with circuit performance.Therefore, in the present embodiment,, compensated the performance that is arranged at away from the RAM circuit block RAM2 in the place of interior power supply circuit 10 as example.That is, compensated decline in the internal power source voltage of the power port that is applied in RAM circuit block RAM2.

In this example, based on the dead resistance (R1+R2) of the wiring of the internal electric source between the power port of operating current Iact * 2 of selecteed RAM circuit block RAM1, RAM2 and interior power supply circuit 10 and RAM circuit block RAM2, the decline compensation rate of internal power source voltage becomes (((Iact * 2) * R1)+(Iact * R2)).Under these circumstances, the internal power source voltage that is applied in the power port VINT11 of RAM circuit block RAM1 becomes (VINT1+ (Iact * R2)).Therefore, corresponding to (Iact * R2), be applied in the internal power source voltage height of RAM circuit block RAM1.Certainly, as mentioned above,, there is not the problem of circuit operation so in the scope of internal power source voltage of allowing and the access speed of allowing if internal power source voltage descends.If internal power source voltage does not descend, require to have imagination (will in the 3rd embodiment, describe this kind situation after a while) so such as in the operating current of RAM circuit block, descending and in the dead resistance of internal electric source wiring, descend or the like in scope.

Therefore, when selecting RAM circuit block RAM1, RAM2, interior power supply circuit 10 output voltages, wherein with ((the corresponding drop-out voltage of (Iact * 2) * R1)+(Iact * R2)) is added into internal power source voltage VINT1, that is, (((Iact * 2) * R1)+(Iact * R2)) is as output voltage V INT1 ' for VINT1+.Therefore, even generate drop-out voltage based on the dead resistance of internal electric source wiring and the operating current of RAM circuit block RAM1, RAM2, the voltage of VINT1 also is applied in the power port VINT12 away from the RAM circuit block RAM2 of internal electric source 13.Like this, even there is the decline of the voltage that the dead resistance by the internal electric source wiring causes, also can obtain the lcd driver that the access speed of RAM circuit block RAM2 wherein not have deterioration.

Figure 11 is the operation that illustrates as according to a second embodiment of the present invention conductor integrated circuit device, the output voltage V INT1 ' of RAM circuit block activation signal SEL1 to SELn, interior power supply circuit 10 and be applied in the sequential chart of the relation between the voltage of power port VINT11 to VINT1n.Here, the transverse axis express time, and Z-axis is represented voltage.Control the output voltage V INT1 ' of interior power supply circuit 10 based on the operational state change ground of RAM circuit block.When the RAM circuit block of selecting and operate was RAM circuit block RAM1, RAM2, control consistently was applied in the output voltage V INT1 ' of internal electric source port VINT12 to VINT1n and does not descend.

Second embodiment has been described about RAM circuit block RAM1, RAM2 and RAM circuit block RAMn-1, RAMn.But, under the similar mode of thinking, the present invention even can be applied to wherein existing the situation of operated a plurality of visits at the same time.

Equally, viewpoint from the scope that is provided with that reduces internal power source voltage, when activating a plurality of RAM circuit block simultaneously,, therefore require to be adjacent to arrange the RAM circuit block of operating simultaneously because the difference of the dead resistance between the internal electric source wiring can be very little in adjacent RAM circuit block.On the contrary, the adjacent RAM circuit block that requires optionally control to be simultaneously operated.But also as shown in Figure 10, if the drop-out voltage of internal power source voltage mates and descends in the variation range of allowing of internal power source voltage and access speed, control and treatment is not limited to select simultaneously all the time the control of adjacent RAM circuit block so.Therefore, when existing another to have the design content of higher priority, can optimize the arrangement and the selection operation of RAM circuit block based on priority.

As mentioned above, as second embodiment, the situation of wherein operating two RAM circuit blocks has simultaneously been described.But certainly, in the scope of aforementioned limitations, the present invention can be applied to wherein operating simultaneously the situation of three or more RAM circuit blocks.

[effect]

The effect of conductor integrated circuit device according to a second embodiment of the present invention will be described below.

According to a second embodiment of the present invention, conductor integrated circuit device comprises: the RAM circuit that is divided into RAM circuit block RAM1 to RAMn; With interior power supply circuit 10.From RAM circuit block RAM1 to RAMn, select to comprise the selection RAM circuit block of two or more RAM circuit blocks.At this moment, interior power supply circuit 10 will be selected the RAM circuit block as output voltage V INT1 ' supply based on the voltage in the arrangement place of selecting the RAM circuit block.Therefore, conductor integrated circuit device according to a second embodiment of the present invention obtains and the first embodiment similar effects.

Equally, according to a second embodiment of the present invention, except the effect of first embodiment, conductor integrated circuit device can also be applied to wherein operating simultaneously the situation of a plurality of RAM circuit blocks.Conductor integrated circuit device according to a second embodiment of the present invention, a plurality of RAM circuit blocks are simultaneously operated.Therefore, it is higher that data access speed can become, thereby make the performance of lcd driver can be higher.

(the 3rd embodiment)

As the idea of having explained in a second embodiment that in the scope of the internal power source voltage of allowing and the access speed of allowing, descends, the conductor integrated circuit device of a third embodiment in accordance with the invention has been described about the operating current that reduces the RAM circuit block and the method that reduces the dead resistance of internal electric source wiring.In the 3rd embodiment, omitted the description that repeats with first and second embodiment.

Figure 12 is the view of structure that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown.RAM circuit in this conductor integrated circuit device roughly is divided into two parts and is arranged as a plurality of RAM circuit blocks.This RAM circuit is divided into: n RAM circuit block RAMR1 to RAMRn (n is an integer) in the group; And the n in second group RAM circuit block RAML1 to RAMLn.

Suppose to start from n RAM circuit block RAMR1 to RAMRn in first group of the sequence arrangement of nearest RAM circuit block RAMR1 to the nRAM circuit block RAMRn of interior power supply circuit 10.Similarly, suppose to start from n RAM circuit block RAML1 to RAMLn in second group of the sequence arrangement of nearest RAM circuit block RAML1 to the nRAM circuit block RAMLn of interior power supply circuit 10.The internal electric source wiring is connected to interior power supply circuit 10.Power circuit 10 is arranged the internal electric source wiring internally, then it is branched into first and second internal wirings.In second and second group, arrange the wiring of first and second internal electric sources respectively.Compare with the dead resistance of lighting from branch, suppose that the internal electric source wiring is disposed between interior power supply circuit 10 and the take-off point with low relatively resistance.

N RAM circuit block RAMR1 to RAMRn in first group is connected to the wiring of first internal electric source in parallel.In first internal electric source wiring, n dead resistance RR1 to RRn conduct correspond respectively to n RAM circuit block RAMR1 to RAMRn in first group the arrangement place dead resistance and occur.That is, n RAM circuit block RAMR1 to RAMRn is connected to the wiring of first internal electric source respectively by n power port.Between the power port of first internal electric source wiring, generate respectively with first group in corresponding n dead resistance RR1 to RRn of n RAM circuit block RAMR1 to RAMRn.In order to simplify explanation, suppose that all resistance values all equate among n the dead resistance RR1 to RRn.

N RAM circuit block RAML1 to RAMLn in second group is connected to the wiring of second internal electric source in parallel.In second internal electric source wiring, n dead resistance RL1 to RLn conduct correspond respectively to n RAM circuit block RAML1 to RAMLn in second group the arrangement place dead resistance and occur.That is, n RAM circuit block RAML1 to RAMLn in second group is connected to the wiring of second internal electric source respectively by n power port.Between the power port of second internal electric source wiring, generate respectively with second group in corresponding n dead resistance RL1 to RLn of n RAM circuit block RAML1 to RAMLn.In order to simplify explanation, suppose that all resistance values all equate among n the dead resistance RL1 to RLn.

To be used for providing n the signal wire of RAM circuit block activation signal SELR1 to SELRn to be connected to first group n RAM circuit block RAMR1 to RAMRn here.N signal wire also is connected to the input of logical circuit 20.Similarly, will be used for providing n the signal wire of RAM circuit block activation signal SELL1 to SELLn to be connected to second group n RAM circuit block RAML1 to RAMLn respectively.N signal wire also is connected to the input of logical circuit 20.By using RAM circuit block activation signal SELR1 to SELRn and SELL1 to SELLn, logical circuit 20 is supplied with bleeder circuit 13 with voltage division control signal CVm (m satisfies 0 to n integer).

For example, n in first group RAM circuit block RAMR1 to RAMRn is corresponding to the n among first and second embodiment RAM circuit block RAM1 to RAMn, and RAM circuit block activation signal SELR1 to SELRn is corresponding to the RAM circuit block activation signal SEL1 to SELn among first and second embodiment.

Similarly, n in second group RAM circuit block RAML1 to RAMLn is corresponding to the n among first and second embodiment RAM circuit block RAM1 to RAMn, and RAM circuit block activation signal SELL1 to SELLn is corresponding to the RAM circuit block activation signal SEL1 to SELn among first and second embodiment.

[operation]

The operation of the conductor integrated circuit device of a third embodiment in accordance with the invention has been described about current two simultaneous situations of RAM circuit block of operating wherein.In order to simplify description, here, the operating current of a RAM circuit block is defined as Iact.

In order to select RAM circuit block RAMR1, RAML1, the signal level of RAM circuit block activation signal SELR1, SELL1 is switched into high level " H ".At this moment, RAM circuit block RAMR1, RAML1 are activated.

Based on dead resistance RR1, RL1 in the internal electric source wiring between the power port of the operating current Iact of the RAM circuit block RAMR1, the RAML1 that select and interior power supply circuit 10 and each RAM circuit block RAMR1, RAML1, the decline compensation rate of each internal power source voltage is (Iact * RR1) and in RAM circuit block RAML1 side be (Iact * RL1) in RAM circuit block RAMR1 side.

Here, the RAM circuit block of operation is arranged such that the dead resistance of internal electric source wiring equates simultaneously.Preferably, they are arranged such that falling quantity of voltages equates.Perhaps, can optionally operate the RAM circuit block that feasible dead resistance of operating wherein internal electric source wiring simultaneously equates.This kind structure can be simplified the decline compensation control of the output voltage that is used for interior power supply circuit.

Like this, in the 3rd embodiment, consider the decline compensation rate of the output voltage V INT1 ' that is used for interior power supply circuit 10, output voltage V INT1 ' is controlled to and equals the VINT1+ (VINT1+ of Iact * RR1) (Iact * RL1).Therefore, when selecting a plurality of RAM circuit block RAMR1, RAML1 simultaneously, the voltage of the power port that is applied in each RAM circuit block RAMR1, RAML1 is equated.

Equally, from interior power supply circuit 10 nearest RAM circuit block RAMR1, RAML1 the 3rd embodiment has been described by example.But,, similarly, the voltage of the power port that is applied in each RAM circuit block is equated even operate simultaneously from interior power supply circuit 10 RAM circuit block RAMRn, RAMLn farthest.

Equally, in the 3rd embodiment, because the RAM circuit block of operation is arranged in the internal electric source wiring that belongs to different system dispersedly simultaneously, be minimized so flow through the operating current of the RAM circuit block of a system, thereby be suppressed at decline in the internal power source voltage that generates in the circuit operation.Under situation based on the content of this principle, for example, except wherein as described herein the RAM circuit be divided into two groups the embodiment of layout, can also be applied to the layout that RAM circuit wherein is divided into three groups or more groups.

[effect]

The effect of the conductor integrated circuit device of a third embodiment in accordance with the invention will be described below.

The conductor integrated circuit device of a third embodiment in accordance with the invention, the RAM circuit comprises a plurality of groups: each group comprises a plurality of RAM circuit block RAM1 to RAMn among first and second embodiment.For example, the RAM circuit comprises: the RAM circuit block RAMR1 to RAMRn that is RAM circuit block RAM1 to RAMn in first group; And in second group the RAM circuit block RAML1 to RAMLn of RAM circuit block RAM1 to RAMn.Arrange the RAM circuit block RAMR1 to RAMRn in first group in order: start from from the nearest RAM circuit block RAMR1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMRn farthest.Similarly, arrange RAM circuit block RAML1 to RAMLn in second group in order: start from from the nearest RAM circuit block RAML1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMLn farthest.In the internal electric source wiring, correspond respectively to the arrangement ground dot generation dead resistance RR1 to RRn of the RAM circuit block RAMR1 to RAMRn in first group.Equally, in the internal electric source wiring, correspond respectively to the arrangement ground dot generation dead resistance RL1 to RLn of the RAM circuit block RAML1 to RAMLn in second group.Select the RAM circuit block to comprise at least one RAM circuit block in the middle of the RAM circuit block RAMR1 to RAMRn in first group; With second group in RAM circuit block RAML1 to RAMLn in the middle of at least one RAM circuit block.Therefore, the conductor integrated circuit device of a third embodiment in accordance with the invention as its effect, can reduce the operating current of RAM circuit block and the dead resistance of internal electric source wiring.

The conductor integrated circuit device of a third embodiment in accordance with the invention has been described about following method, wherein for the n that in lcd driver, provides a RAM circuit block, based on the output voltage V INT1 ' that selects the RAM circuit block at n step control interior power supply circuit 10.But, the invention is not restricted to this kind situation.As the variation example of the conductor integrated circuit device of a third embodiment in accordance with the invention, can in the scope of internal power source voltage of allowing and the access speed of allowing, reduce the quantity (in Figure 10, described should the fact) of controlled step.

Figure 13 A and Figure 13 B are the views of structure of variation example 1 that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown.

In the variation example 1 of the conductor integrated circuit device of a third embodiment in accordance with the invention, the RAM circuit comprises a plurality of groups; Each group comprise a plurality of RAM circuit block RAM1 to RAM2 in the variation example 1 among first embodiment,---and RAMn-1 to RAMn.For example, the RAM circuit comprises: be RAM circuit block RAM1 to RAM2,--and the RAM circuit block RAMR1 to RAMR2 of RAMn-1 to RAMn,---and RAMRn-1 to RAMRn in first group; Be RAM circuit block RAM1 to RAM2,--and the RAM circuit block RAML1 to RAML2 of RAMn-1 to RAMn,---and RAMLn-1 to RAMLn in second group.Arrange in order in first group RAM circuit block RAMR1 to RAMR2,---and RAMRn-1 to RAMRn: start from from the nearest RAM circuit block RAMR1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMRn farthest.Similarly, arrange in order in second group RAM circuit block RAML1 to RAML2,---and RAMLn-1 to RAMLn: start from from the nearest RAM circuit block RAML1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMLn farthest.In internal electric source wiring, correspond respectively to RAM circuit block RAMR1 to RAMR2 in first group,--and the arrangement of RAMRn-1 to RAMRn ground dot generation dead resistance RR1 to RR2,---and RRn-1 to RRn.Similarly, in the wiring of other internal electric source, correspond respectively to RAM circuit block RAML1 to RAML2 in second group,--and the arrangement of RAMLn-1 to RAMLn ground dot generation dead resistance RL1 to RL2,---and RLn-1 to RLn.Select the RAM circuit block comprise RAM circuit block RAMR1 to RAMR2 in first group,---and RAMRn-1 to RAMRn in the middle of at least one RAM circuit block; With second group in RAM circuit block RAML1 to RAML2,---and RAMLn-1 to RAMLn in the middle of at least one RAM circuit block.

Figure 14 A and Figure 14 B are the views of structure of variation example 2 that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown.

In the variation example 2 of the conductor integrated circuit device of a third embodiment in accordance with the invention, the RAM circuit comprises a plurality of groups; Each group comprise a plurality of RAM circuit block RAM1 to RAM4 in the variation example 2 among first embodiment,---and RAMn-3 to RAMn.For example, the RAM circuit comprises: be RAM circuit block RAM1 to RAM4,--and the RAM circuit block RAMR1 to RAMR4 of RAMn-3 to RAMn,---and RAMRn-3 to RAMRn in first group; Be RAM circuit block RAM1 to RAM4,--and the RAM circuit block RAML1 to RAML4 of RAMn-3 to RAMn,---and RAMLn-3 to RAMLn in second group.Arrange in order in first group RAM circuit block RAMR1 to RAMR4,---and RAMRn-3 to RAMRn: start from from the nearest RAM circuit block RAMR1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMRn farthest.Similarly, arrange in order in second group RAM circuit block RAML1 to RAML4,---and RAMLn-3 to RAMLn: start from from the nearest RAM circuit block RAML1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMLn farthest.In internal electric source wiring, correspond respectively to RAM circuit block RAMR1 to RAMR4 in first group,--and the arrangement of RAMRn-3 to RAMRn ground dot generation dead resistance RR1 to RR4,---and RRn-3 to RRn.Similarly, in the wiring of other internal electric source, correspond respectively to RAM circuit block RAML1 to RAML4 in second group,--and the arrangement of RAMLn-3 to RAMLn ground dot generation dead resistance RL1 to RL4,---and RLn-3 to RLn.Select the RAM circuit block comprise RAM circuit block RAMR1 to RAMR4 in first group,---and RAMRn-3 to RAMRn in the middle of at least one RAM circuit block; With second group in RAM circuit block RAML1 to RAML4,---and RAMLn-3 to RAMLn in the middle of at least one RAM circuit block.

Figure 15 A and Figure 15 B are the views of structure of variation example 3 that the conductor integrated circuit device of a third embodiment in accordance with the invention is shown.

In the variation example 3 of the conductor integrated circuit device of a third embodiment in accordance with the invention, the RAM circuit comprises a plurality of groups; Each group comprise a plurality of RAM circuit block RAM1, RAM2 to RAM4 in the variation example 3 among first embodiment,---and RAMn-3 to RAMn.For example, the RAM circuit comprises: be RAM circuit block RAM1, RAM2 to RAM4,--and RAM circuit block RAMR1, the RAMR2 to RAMR4 of RAMn-3 to RAMn,---and RAMRn-3 to RAMRn in first group; Be RAM circuit block RAM1, RAM2 to RAM4,--and RAM circuit block RAML1, the RAML2 to RAML4 of RAMn-3 to RAMn,---and RAMLn-3 to RAMLn in second group.Arrange in order in first group RAM circuit block RAMR1, RAMR2 to RAMR4,---and RAMRn-3 to RAMRn: start from from the nearest RAM circuit block RAMR1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMRn farthest.Similarly, arrange in order in second group RAM circuit block RAML1, RAML2 to RAML4,---and RAMLn-3 to RAMLn: start from from the nearest RAM circuit block RAML1 of interior power supply circuit 10 and end at from interior power supply circuit 10 RAM circuit block RAMLn farthest.In internal electric source wiring, correspond respectively to RAM circuit block RAMR1, RAMR2 to RAMR4 in first group,--and the arrangement of RAMRn-3 to RAMRn ground dot generation dead resistance RR1, RR2 to RR4,---and RRn-3 to RRn.Similarly, in the wiring of other internal electric source, correspond respectively to RAM circuit block RAML1, RAML2 to RAML4 in second group,--and the arrangement of RAMLn-3 to RAMLn ground dot generation dead resistance RL1, RL2 to RL4,---and RLn-3 to RLn.Select the RAM circuit block comprise RAM circuit block RAMR1, RAMR2 to RAMR4 in first group,---and RAMRn-3 to RAMRn in the middle of at least one RAM circuit block; With second group in RAM circuit block RAML1, RAML2 to RAML4,---and RAMLn-3 to RAMLn in the middle of at least one RAM circuit block.

Equally, in conductor integrated circuit device, used the RAM circuit block of identical type according to first to the 3rd embodiment of the present invention.But they are not limited thereto kind of a situation.Even under the situation of using different types of circuit block, can use the present invention.Equally, can mix different types of circuit block.Under these circumstances, although operating current differs from one another, can control the principle of the internal power source voltage VINT1 of power circuit 10 outputs internally according to decline quantity and use the present invention based on internal power source voltage.

Equally, in conductor integrated circuit device, described by changing the voltage division ratio and come the method for control output voltage VINT1 ' to be used as the control mode of the output voltage V INT1 ' of interior power supply circuit 10 according to first to the 3rd embodiment of the present invention.But, can use other circuit structure and control method.

Equally, in the conductor integrated circuit device according to first to the 3rd embodiment of the present invention, the output voltage V INT1 ' that has described in RAM circuit block activation signal is in period of high level " H " wherein interior power supply circuit 10 is controlled to be the higher period.But, there is following circuit, wherein depend on circuit, even activation signal is cut off, operation still continues a period of time.Therefore, when the present invention was applied to aforesaid circuit, in the period that circuit is activated, interior power supply circuit 10 should be provided with and wherein internal power source voltage VINT1 is controlled to be the higher control period.

Equally, keep the viewpoint of internal power source voltage to describe conductor integrated circuit device from the output voltage that is similar to interior power supply circuit according to first to the 3rd embodiment of the present invention.But, can be in the following manner the output voltage of interior power supply circuit be controlled to be height, wherein depend on mode of operation, even consider drop-out voltage for the necessary circuit piece, the voltage that is applied to power port becomes higher.

Equally, in conductor integrated circuit device according to first to the 3rd embodiment of the present invention, the RAM circuit block that example provides in lcd driver and described the present invention.But if the purpose of the decline in the supply voltage that the dead resistance that satisfied improvement is connected up by internal electric source causes, the present invention can be applied to any conductor integrated circuit device so.

Although described the present invention in the above together with some embodiment of the present invention, but described clearly embodiment only provides for the present invention is shown for those skilled in the art, and can not explain the application's claim based on described embodiment in limiting sense.

Claims (17)

1. conductor integrated circuit device comprises:

The RAM circuit, described RAM circuit is constructed to comprise a plurality of RAM circuit blocks, wherein RAM is a random access storage device; With

Interior power supply circuit, described interior power supply circuit are constructed to voltage is offered the selection RAM piece of selecting from described a plurality of RAM circuit blocks,

Wherein said voltage is corresponding to the arrangement position of described selection RAM circuit block.

2. conductor integrated circuit device according to claim 1 further comprises:

The internal electric source wiring, described internal electric source wiring is constructed to connect described interior power supply circuit and described a plurality of RAM circuit block,

Wherein correspond respectively to a plurality of arrangements position of described a plurality of RAM circuit blocks, in described internal electric source wiring, a plurality of dead resistances occur,

Wherein in described interior power supply circuit, be respectively described a plurality of RAM circuit block and be provided with and the corresponding a plurality of voltages of described a plurality of dead resistances,

Wherein said interior power supply circuit offers described selection RAM circuit block with described voltage, and

Described voltage is included in described a plurality of voltage, and corresponding to the described described arrangement position of selecting the RAM circuit block in described a plurality of arrangements position.

3. conductor integrated circuit device according to claim 2, wherein said interior power supply circuit comprises:

Bleeder circuit, described bleeder circuit are constructed to have a plurality of voltage division ratios so that described a plurality of voltage to be set,

Wherein said a plurality of voltage division ratio corresponds respectively to described a plurality of RAM circuit block,

Wherein said interior power supply circuit is selected from described a plurality of voltage division ratios and the corresponding selection voltage division of described selection RAM circuit block ratio, and described voltage is offered described selection RAM circuit block, and

Described voltage is corresponding to described selection voltage division ratio.

4. conductor integrated circuit device according to claim 3 further comprises:

Logical circuit, described logical circuit are constructed to will be used to select the division control signal of described selection voltage division ratio to export described bleeder circuit to based on the RAM circuit block activation signal that is used to select described selection RAM circuit block,

Wherein said bleeder circuit is selected described selection voltage division ratio based on described division control signal from described a plurality of voltage division ratios, and

Wherein said interior power supply circuit will offer described selection RAM circuit block with the corresponding described voltage of described selection voltage division ratio.

5. conductor integrated circuit device according to claim 2, wherein said interior power supply circuit generates internal power source voltage,

Wherein said a plurality of RAM circuit block is connected to described internal electric source wiring in parallel,

Wherein when selecting and operate in described a plurality of RAM circuit block each, with respect to described each RAM circuit block, operating current and the dead resistance between described each RAM circuit block and the described interior power supply circuit based on described each RAM circuit block generate drop-out voltage, and

In wherein said a plurality of voltage each is a described internal power source voltage and with respect to the summation of the described drop-out voltage of described each RAM circuit block.

6. conductor integrated circuit device according to claim 5, wherein when described a plurality of RAM circuit blocks were represented as n RAM circuit block from RAM circuit block to a nRAM circuit block, wherein n was an integer,

With described n the corresponding described a plurality of dead resistances of RAM circuit block be represented as R1, R1+R2,---and R1+---+Rn,

The operating current of each in described n RAM circuit block is represented as Iact,

Described internal power source voltage is represented as VINT1,

Described selection RAM circuit block is represented as the jRAM circuit block, and wherein j is an integer, is equal to, or greater than 1, and is equal to or less than n, and

Described output voltage is represented as VINT1 ', its be in described a plurality of voltage with the corresponding voltage of described jRAM circuit block,

Represent described VINT1 ' by following equation:

${\mathrm{VINT}1}^{\&prime;}=\mathrm{VINT}1+(\mathrm{Iact}\&times;\underset{i=1}{\overset{j}{\mathrm{\&Sigma;}}}\mathrm{Ri})$

Described i is an integer, is equal to, or greater than 1, and is equal to or less than n.

7. conductor integrated circuit device according to claim 1 further comprises:

The internal electric source wiring, described internal electric source wiring is constructed to connect described interior power supply circuit and described a plurality of RAM circuit block,

Wherein when described a plurality of RAM circuit blocks were n RAM circuit block from a RAM circuit block to the nRAM circuit block, wherein n was an integer,

Wherein said n RAM circuit block formed x RAM circuit block group, and wherein x is an integer, less than n,

The a plurality of arrangements position that wherein corresponds respectively to described x RAM circuit block group a plurality of dead resistances occur in described internal electric source wiring,

Wherein be respectively described x RAM circuit block group, in described interior power supply circuit, be provided with and the corresponding x of a described a plurality of dead resistances voltage, and

Wherein said interior power supply circuit offers described selection RAM circuit block with described voltage, and

Described voltage is included in the described x voltage, and corresponding to the described described arrangement position of selecting the RAM circuit block in described a plurality of arrangements position.

8. conductor integrated circuit device according to claim 7, the quantity of the RAM circuit block in each of wherein said x RAM circuit block group is N, N is the integer that satisfies the equation of n=x * N.

9. conductor integrated circuit device according to claim 7, wherein said interior power supply circuit comprises:

Bleeder circuit, described bleeder circuit are constructed to have x voltage division ratio so that a described x voltage to be set,

Wherein said x voltage division ratio corresponds respectively to described x RAM circuit block,

Wherein said interior power supply circuit is selected from described x voltage division ratio and the corresponding selection voltage division of described selection RAM circuit block ratio, and described voltage is offered described selection RAM circuit block, and

Described voltage is corresponding to described selection voltage division ratio.

10. conductor integrated circuit device according to claim 9 further comprises:

Logical circuit, described logical circuit are constructed to will be used to select the division control signal of described selection voltage division ratio to export described bleeder circuit to based on the RAM circuit block activation signal that is used to select described selection RAM circuit block,

Wherein said bleeder circuit is selected described selection voltage division ratio based on described division control signal from described x voltage division ratio, and

Wherein said interior power supply circuit will offer described selection RAM circuit block with the corresponding described voltage of described selection voltage division ratio.

11. according to claim 2 or 7 described conductor integrated circuit devices, wherein by the RAM circuit block that starts from having minimum dead resistance and end to have the described a plurality of RAM circuit blocks of sequence arrangement of the RAM circuit block of maximum dead resistance.

12. according to any one the described conductor integrated circuit device in the claim 1 to 10, wherein by starting from from the nearest RAM circuit block of described interior power supply circuit and ending at from the described a plurality of RAM circuit blocks of the sequence arrangement of described interior power supply circuit RAM circuit block farthest.

13. according to any one the described conductor integrated circuit device in the claim 1 to 10, wherein said selection RAM circuit block is in described a plurality of RAM circuit block two or more.

14. according to any one the described conductor integrated circuit device in the claim 1 to 10, wherein said RAM circuit comprises a plurality of groups, each in described a plurality of groups comprises described a plurality of RAM circuit block,

Wherein said selection RAM circuit block comprises:

At least one RAM circuit block of in described a plurality of groups each.

15. a LCD driver that is used to drive display panels comprises:

The RAM circuit, described RAM circuit is constructed to comprise a plurality of RAM circuit blocks, wherein RAM is a random access storage device; With

Interior power supply circuit, described interior power supply circuit are constructed to voltage is offered the selection RAM piece of selecting from described a plurality of RAM circuit blocks,

Wherein said voltage is corresponding to the arrangement position of described selection RAM circuit block.

16., further comprise according to the described LCD driver of claim 15:

The internal electric source wiring, described internal electric source wiring is constructed to connect described interior power supply circuit and described a plurality of RAM circuit block,

Wherein correspond respectively to a plurality of arrangements position of described a plurality of RAM circuit blocks, in described internal electric source wiring, a plurality of dead resistances occur,

Wherein be respectively described a plurality of RAM circuit block and in described interior power supply circuit, be provided with and the corresponding a plurality of voltages of described a plurality of dead resistances,

Wherein said interior power supply circuit offers described selection RAM circuit block with described voltage, and

Described voltage is included in described a plurality of voltage, and corresponding to the described described arrangement position of selecting the RAM circuit block in described a plurality of arrangements position.

17. LCD driver according to claim 15 further comprises:

The internal electric source wiring, described internal electric source wiring is constructed to connect described interior power supply circuit and described a plurality of RAM circuit block,

Wherein when described a plurality of RAM circuit blocks were n RAM circuit block from a RAM circuit block to n RAM circuit block, wherein n was an integer,

Wherein said n RAM circuit block formed x RAM circuit block group, and wherein x is an integer, less than n,

The a plurality of arrangements position that wherein corresponds respectively to described x RAM circuit block group a plurality of dead resistances occur in described internal electric source wiring,

Wherein be respectively described x RAM circuit block group and in described interior power supply circuit, be provided with and the corresponding x of a described a plurality of dead resistances voltage,

Wherein said interior power supply circuit offers described selection RAM circuit block with described voltage, and

Described voltage is included in the described x voltage, and corresponding to the described described arrangement position of selecting the RAM circuit block in described a plurality of arrangements position.

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