CN101587304B - Pattern transferring method - Google Patents
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- CN101587304B CN101587304B CN2008101125140A CN200810112514A CN101587304B CN 101587304 B CN101587304 B CN 101587304B CN 2008101125140 A CN2008101125140 A CN 2008101125140A CN 200810112514 A CN200810112514 A CN 200810112514A CN 101587304 B CN101587304 B CN 101587304B
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Abstract
The invention provides a pattern transferring method, which comprises the following steps: providing a semiconductor substrate with a plurality of mask layers, wherein the mask layers which are furthest from the semiconductor substrate and are not etched are provided with photoresist layers, and the photoresist layers contain a photographic acidifier and alkyl phenoxy benzoic acid resin; exposing an objective pattern to the photoresist layer to form a photoresist layer with a semiconductor device pattern, wherein the depth of the semiconductor device pattern on the photoresist layer is less than the depth of the photoresist layer; performing silanization treatment on the surface of the photoresist layer with the objective pattern; forming an anti-plasma etching layer with an objective pattern shape on the photoresist layer; taking the anti-plasma etching layer on the photoresist layer as a mask; performing plasma etching on the photoresist layer until a mask layer is exposed; and taking the anti-plasma etching layer or the photoresist layer as the mask to etch the mask layer. The pattern transferring method does not need to coat an anti-reflection layer on the etched surface and avoids the unsmooth coating of the anti-reflection layer, thereby avoiding an unstable structure of pattern lines formed by the photoresist layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to graph transfer method.
Background technology
In order to improve integrated level, reduce manufacturing cost, the critical size of semiconductor devices constantly diminishes, and the semiconductor devices quantity in the chip unit area constantly increases.When the semiconductor devices critical size reduced, semiconductor device graph is granular constantly also.Yet the formation of trickle figure and trickle pitch difficulty is all the more got up, in order to form trickle figure, introduced on the rete with photomask board on figure carry out double exposure technology.
" semiconductor manufacturing " 2007 8 monthly magazine articles " stack figure immersion lithography is applied to the prospect forecast of 32nm half-section distance " disclose existing with double exposure technology methods of making semiconductor devices.Referring to figs. 1 to Fig. 5, in Fig. 1, form first mask layer 102 comprising driving circuit at isostructural the semiconductor-based end 101, wherein, the material of first mask layer 102 can be polysilicon or silicon oxynitride etc., act as to protect the semiconductor-based end 101 to avoid the influence of etching gas in the subsequent etching process; The method that forms first mask layer 102 is chemical vapour deposition technique or physical vaporous deposition etc.Then; on first mask layer 102, form second mask layer 103 with methods such as chemical vapour deposition technique or physical vaporous depositions; the material of second mask layer 103 can be a silicon nitride etc., act as in order to protect the complete of first mask layer 102 in the subsequent etching process.Form first anti-reflecting layer 104 on second mask layer 103, the rete below protection in the post-exposure technology is avoided the influence of light, and the method that forms first anti-reflecting layer 104 can be a spin-coating method.And on first anti-reflecting layer 104 spin coating first photoresist layer 105.
As shown in Figure 2, the photomask 10 and the semiconductor-based end 100 that has each rete are put into lithographic equipment, mask figure 12 on the photomask 10 is transferred on first photoresist layer 105 by photoetching technique, forms figure and the semiconductor device graph 12 corresponding graphical first photoresist layer 105a.With the graphical first photoresist layer 105a is mask,, form and corresponding graphical second mask layer 103a of the graphical first photoresist layer 105a and the graphical first anti-reflecting layer 104a to exposing first mask layer 102 with wet etching first anti-reflecting layer 104 and second mask layer 103.
As shown in Figure 3, remove the graphical first photoresist layer 105a with ashing method; Form second anti-reflecting layer 107 on the graphical first anti-reflecting layer 104a and first mask layer 102, described formation method comprises spin-coating method; On second anti-reflecting layer 107, form second photoresist layer (figure does not show) with spin-coating method, and second photoresist layer is filled the opening 106 of expiring on the graphical second mask layer 103a, after drying, the second photoresist layer surfacing; Move with respect to photomask 10 at the semiconductor-based end 100 that will have each rete, and the distance that moves is that to make first semiconductor device graph on the graphical second mask layer 103a be the required size of target pitch with follow-up pitch between second semiconductor device graph of formation on first mask layer 102; Mask figure 12 on the photomask 10 is transferred on second photoresist layer by photoetching technique, forms the second photoresist layer 108a with second semiconductor device graph.
As shown in Figure 4, with the second photoresist layer 108a with second semiconductor device graph is mask, use the wet etching method, etching second anti-reflecting layer 107 forms the aimed semiconductor component graphics to the first anti-reflecting layer 104a that exposes first mask layer 102 and have first semiconductor device graph.
With second photoresist layer 108a with second semiconductor device graph and the first anti-reflecting layer 104a with first semiconductor device graph is mask, with 102 layers of wet etching first masks to exposing the semiconductor-based end 101, formation has the first mask layer 102a of aimed semiconductor component graphics, and remove and to have second photoresist layer 108a of second semiconductor device graph and the first anti-reflecting layer 104a with first semiconductor device graph, the semiconductor-based end 101 after the etching and have the aimed semiconductor component graphics the first mask layer 102a cross section structure as shown in Figure 5.
Above-mentioned prior art is when spin coating forms second anti-reflecting layer 107 on the first anti-reflecting layer 104a with first semiconductor device graph and first mask layer 102, be coated with the second mask layer 103a owing to have the first anti-reflecting layer 104a of first semiconductor device graph with first semiconductor device graph, cause when coating second anti-reflecting layer 107, second anti-reflecting layer 107 can not evenly entirely be coated with in the groove 106 of the second mask layer 103a with first semiconductor device graph, so, when second photoresist layer is exposed, because the inhomogeneous luminous energy that causes photoresist to be accepted of second anti-reflecting layer 107 is inconsistent, the graphic structure instability that photoresist is formed is caved in.
In addition, second anti-reflecting layer 107 produces standing wave effect easily when exposure, and the photoresist graphic structure sidewall steepness that makes the exposure back form is relatively poor, is unfavorable for the carrying out of etching.
In addition, prior art is used wet etching, because the anisotropy of first mask layer 102 and second mask layer 103, the lines cross section that wet etching causes forming on first mask layer and second mask layer T shape, inverted T-shaped, triangle, del, trapezoidal, trapezoidal, semicircle top occur or does not have the phenomenon on top, or the lines sidewall and the semiconductor-based basal surface out of plumb that form.Caving in appears in the lines that wet etching also causes forming on first mask layer and second mask layer easily.
Summary of the invention
The technical matters that the present invention solves provides a kind of graph transfer method, the mask layer surface-coated anti-reflecting layer that need be etched not, avoid anti-reflecting layer coating out-of-flatness, inhomogeneous in the prior art, and then the luminous energy that causes photoresist to be accepted is inconsistent, thereby the pattern line structural instability that photoresist layer is formed is caved in easily.
For addressing the above problem, the invention provides a kind of graph transfer method, comprise step: provide the semiconductor-based end with at least one mask layer, have photoresist layer farthest and on the not graphical mask layer from the semiconductor-based end, described photoresist layer contains photo acid generator and to alkyl phenoxy formic acid resin; Form graphical photoresist layer by exposure, and the figure degree of depth on the graphical photoresist layer is less than photoresist layer thickness; Use silanizing agent that silanization is carried out on graphical photoresist layer surface and handle, make to be exposed on the graphical photoresist layer and partly change graphical anti-plasma etching layer into; With graphical anti-plasma etching layer is mask, and graphical photoresist layer is carried out plasma etching to exposing mask layer; With graphical anti-plasma etching layer or graphical photoresist layer is mask, the etch mask layer.
Alternatively, the intensity of described exposure is 20mj/cm2 to 50mj/cm2.
Alternatively, the figure degree of depth on the described graphical photoresist layer is 5% to 10% of a photoresist layer thickness.
Alternatively, before the described step, can also comprise the step that photoresist layer is baked and banked up with earth in advance by the graphical photoresist layer of exposure formation.
Alternatively, described temperature of baking and banking up with earth in advance is 100 ℃ to 120 ℃.
Alternatively, the described time of baking and banking up with earth in advance is 50 seconds to 70 seconds.
Alternatively, described silanization can also comprise the step that photoresist layer is toasted after handling, and it is crosslinked that anti-plasma etching layer is produced.
Alternatively, described is right-sec-butyl-phenoxy group t-butyl formate, right-sec-butyl-the phenoxy group sec.-butyl formate, right-sec-butyl-the phenoxy group isopropyl formate, right-isopropyl-the phenoxy group t-butyl formate, right-isopropyl-phenoxy group sec.-butyl formate or right-isopropyl-phenoxy group isopropyl formate to alkyl phenoxy formic acid resin.
Alternatively, described photo acid generator comprises sulphion hexafluoro antimonate or sulphion hexafluorophosphate.
Alternatively, described sulphion hexafluoro antimonate comprises triphenyl sulphur hexafluoro antimonate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluoro antimonate or two-[(4-diphenyl sulfide) phenyl] thioether-two-hexafluoro antimonate.
Alternatively, described sulphion hexafluorophosphate comprises triphenyl sulphur hexafluorophosphate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluorophosphate or two-[(4-diphenyl sulfide) phenyl] sulfide-pairs-hexafluorophosphate.
Alternatively, described silanizing agent comprises hexamethyldisilazane, tetramethyl-disilazane, two (dimethylamino) methyl-monosilane, two (dimethylamino) dimethylsilane, dimethyl silyl dimethylamine, dimethyl silyl diethylamine, the silica-based dimethylamine of front three, the silica-based diethylamine of front three or (dimethylamino) pentamethyl disilane.
Alternatively, carry out plasma etching gas and comprise O2, Ar, CF4, CH2F2 or C4F8.
Compared with prior art, technique scheme forms graphical anti-plasma etching layer on graphical photoresist layer, promptly original position forms the mask layer that one deck is used for the etching photoresist on graphical photoresist layer, and come the graphical photoresist layer of etching with this, thereby the mask layer surface-coated anti-reflecting layer that need not be etched, avoid anti-reflecting layer coating out-of-flatness inhomogeneous, and then the luminous energy that prevents photoresist acceptance is inconsistent, thereby the pattern line structural instability of avoiding photoresist layer to form, and reduced the processing step of making semiconductor devices.
In addition, adopt plasma etching can make the lines sidewall that forms on the photoresist layer vertical with next mask layer or semiconductor-based basal surface or approaching vertical, can avoid described lines cross section T shape, inverted T-shaped, triangle, del, trapezoidal, trapezoidal, semicircle top to occur or do not have the phenomenon on top, can also prevent that caving in from appearring in described lines.
Description of drawings
Fig. 1 to Fig. 5 is the semiconductor-based basal cross section synoptic diagram of prior art;
Fig. 6 is the process flow diagram of graph transfer method embodiment 1 etching second mask layer of the present invention;
Fig. 7 is the process flow diagram of graph transfer method embodiment 1 etching first mask layer of the present invention;
Fig. 8 to Figure 13 is a semiconductor-based basal cross section synoptic diagram among the embodiment 1;
Figure 14 is graph transfer method embodiment 2 process flow diagrams of the present invention;
Figure 15 is graph transfer method embodiment 3 process flow diagrams of the present invention.
Embodiment
In the embodiment, provide a kind of graph transfer method, form graphical anti-plasma etching layer on graphical photoresist layer, promptly original position forms one deck mask layer on graphical photoresist layer, and comes the graphical photoresist layer of etching with this mask layer.
For this reason, a kind of graph transfer method is provided, comprise step: the semiconductor-based end with at least one mask layer is provided, has photoresist layer farthest and on the not graphical mask layer from the semiconductor-based end, described photoresist layer contains photo acid generator and to alkyl phenoxy formic acid resin; Form graphical photoresist layer by exposure, and the figure degree of depth on the graphical photoresist layer is less than photoresist layer thickness; Use silanizing agent that silanization is carried out on graphical photoresist layer surface and handle, make to be exposed on the graphical photoresist layer and partly change graphical anti-plasma etching layer into; With graphical anti-plasma etching layer is mask, and graphical photoresist layer is carried out plasma etching to exposing mask layer; With graphical anti-plasma etching layer or graphical photoresist layer is mask, the etch mask layer.Alternatively, the intensity of described exposure is 20mj/cm2 to 50mj/cm2.Alternatively, the figure degree of depth on the described graphical photoresist layer is 5% to 10% of a photoresist layer thickness.Alternatively, before the described step, can also comprise the step that photoresist layer is baked and banked up with earth in advance by the graphical photoresist layer of exposure formation.Alternatively, described temperature of baking and banking up with earth in advance is 100 ℃ to 120 ℃.Alternatively, the described time of baking and banking up with earth in advance is 50 seconds to 70 seconds.Alternatively, described silanization can also comprise the step that photoresist layer is toasted after handling, and it is crosslinked that anti-plasma etching layer is produced.Alternatively, described is right-sec-butyl-phenoxy group t-butyl formate, right-sec-butyl-the phenoxy group sec.-butyl formate, right-sec-butyl-the phenoxy group isopropyl formate, right-isopropyl-the phenoxy group t-butyl formate, right-isopropyl-phenoxy group sec.-butyl formate or right-isopropyl-phenoxy group isopropyl formate to alkyl phenoxy formic acid resin.Alternatively, described photo acid generator comprises sulphion hexafluoro antimonate or sulphion hexafluorophosphate.Alternatively, described sulphion hexafluoro antimonate comprises triphenyl sulphur hexafluoro antimonate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluoro antimonate or two-[(4-diphenyl sulfide) phenyl] thioether-two-hexafluoro antimonate.Alternatively, described sulphion hexafluorophosphate comprises triphenyl sulphur hexafluorophosphate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluorophosphate or two-[(4-diphenyl sulfide) phenyl] sulfide-pairs-hexafluorophosphate.Alternatively, described silanizing agent comprises hexamethyldisilazane, tetramethyl-disilazane, two (dimethylamino) methyl-monosilane, two (dimethylamino) dimethylsilane, dimethyl silyl dimethylamine, dimethyl silyl diethylamine, the silica-based dimethylamine of front three, the silica-based diethylamine of front three or (dimethylamino) pentamethyl disilane.Alternatively, carry out plasma etching gas and comprise O2, Ar, CF4, CH2F2 or C4F8.
Be specifically described by embodiment below in conjunction with accompanying drawing.
Embodiment 1
The mask layer surface-coated anti-reflecting layer that present embodiment need not be etched, avoid in the prior art anti-reflecting layer coating out-of-flatness inhomogeneous, and then the luminous energy that causes photoresist to be accepted is inconsistent, thereby the pattern line structural instability that photoresist layer is formed is caved in easily.Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
As shown in Figure 6, the present embodiment photoetching method comprises:
Step S111 provides the semiconductor-based end that the two superimposed mask layer can be arranged, and being etched away from first mask layer at the semiconductor-based end forms graphical first mask layer, and exposes second mask layer under graphical first mask layer;
Step S112 forms on second mask layer and graphical first mask layer and contains photo acid generator and to second photoresist layer of alkyl phenoxy formic acid resin;
Step S113, utilize shallow-layer exposure (Shallow Exposure) with on photomask figure transfer to the second photoresist layer, form graphical second photoresist layer, the position that its figure is exposed by graphical first mask layer corresponding to second mask layer, and on second photoresist layer degree of depth of figure less than the thickness of second photoresist layer;
Step S114 carries out silanization processing (Silylation) to the part of being exposed by shallow-layer in the graphical second photoresist layer surface, forms graphical anti-plasma etching layer on graphical second photoresist layer;
Step S115 is a mask with graphical anti-plasma etching layer, and second photoresist layer is carried out plasma etching to exposing graphical first mask layer and second mask layer;
Step S116 is a mask with graphical anti-plasma etching layer, and etching second mask layer forms graphical second mask layer to exposing the semiconductor-based end, removes graphical first mask layer, graphical anti-plasma etching layer and graphical second photoresist layer again.
In step S116, can remove graphical anti-plasma etching layer in advance, be mask with graphical first mask layer and graphical second photoresist layer again, etching second mask layer is removed graphical first mask layer and graphical second photoresist layer again to exposing the semiconductor-based end.
In the said method, the method that forms the described semiconductor-based end of step S111 can be the usual photoetching methods that use of those skilled in the art, and as shown in Figure 7, concrete steps can comprise:
Step S101 provides the semiconductor-based end, has second mask layer, first mask layer, anti-reflecting layer and first photoresist layer successively at described the semiconductor-based end;
Step S102 is transferred to first semiconductor device graph on first photomask on first photoresist layer, forms graphical first photoresist layer;
Step S103 is a mask with graphical first photoresist layer, and the etching anti-reflecting layer and first mask layer form graphical first mask layer to exposing second mask layer;
Step S104 removes graphical first photoresist layer and anti-reflecting layer.
Step S111 is combined in step S101 to step S104 to step S116, has formed the method that complete etching has the semiconductor-based end of two-layer mask layer.Fig. 8 to Figure 13 is the synoptic diagram of this method.
As shown in Figure 8, provide the semiconductor-based end 201, have second mask layer 202, first mask layer 203, anti-reflecting layer 204 and first photoresist layer 205 at described the semiconductor-based end 201 successively.
The material of second mask layer 202 and first mask layer 203 can be determined according to the material at the semiconductor-based end, makes second mask layer 202 and first mask layer 203 reach certain etching ratio and requires.When the semiconductor-based end, be common monocrystalline silicon, the material of second mask layer 202 can be monox, silicon nitride or polysilicon, the thickness of second mask layer 202 can be 10nm to 200nm, specifically can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm or 200nm, when using polysilicon, the thickness of second mask layer 202 is 50nm.The material of first mask layer 203 can be monox, silicon nitride or polysilicon, the thickness of second mask layer 202 can be 10nm to 200nm, specifically can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm or 200nm, when using polysilicon, the thickness of first mask layer 203 is 50nm.
The thickness of anti-emission coating 204 can be 30nm to 150nm, specifically can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm or 150nm.
The thickness of first photoresist layer 205 can be 150nm to 400nm, specifically can be 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, 310nm, 320nm, 330nm, 340nm, 350nm, 360nm, 370nm, 380nm, 390nm or 400nm.
As shown in Figure 9.By execution in step S102, first semiconductor device graph 22 on first photomask 20 is transferred on first photoresist layer, form the graphical first photoresist layer 205a.
Execution in step S103 is a mask with the graphical first photoresist layer 205a again, and the etching anti-reflecting layer 204 and first mask layer 203 form as shown in figure 10 graphical first mask layer 203a and graphical anti-reflecting layer 204a to exposing second mask layer 202.
Execution in step S104 removes graphical first photoresist layer 205a and graphical anti-reflecting layer 204a.After execution of step S104, formed a kind of like this semiconductor-based end with two-layer mask layer, promptly away from first mask layer at the semiconductor-based end groove that is etched out, channel bottom exposes second mask layer, has also promptly formed the semiconductor-based end that step S111 will provide.
As shown in figure 11, execution in step S112 again, coating contains photo acid generator (being called photosensitive acid generator again, Photoacid Generator) and to second photoresist layer 206 of alkyl phenoxy formic acid resin on second mask layer 202 and the graphical first mask layer 203a.Photoresist can be that the trade mark that JSR company produces is the photoresist of JSRl532.The coating thickness of second photoresist layer 206 is 150nm to 250nm, concrete example such as 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm or 250nm.Described photo acid generator can be sulphion hexafluoro antimonate or sulphion hexafluorophosphate, concrete example such as triphenyl sulphur hexafluoro antimonate, triphenyl sulphur hexafluorophosphate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluoro antimonate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluorophosphate, two-[(4-diphenyl sulfide) phenyl] thioether-two-hexafluoro antimonate or two-[(4-diphenyl sulfide) phenyl] sulfide-pairs-hexafluorophosphate.Also contain in second photoresist layer 206 to alkyl phenoxy formic acid resin, concrete example such as right-sec-butyl-phenoxy group t-butyl formate, right-sec-butyl-the phenoxy group sec.-butyl formate, right-sec-butyl-the phenoxy group isopropyl formate, right-isopropyl-the phenoxy group t-butyl formate, right-isopropyl-phenoxy group sec.-butyl formate or right-isopropyl-phenoxy group isopropyl formate.
Execution in step S113 again, first semiconductor device graph of second semiconductor device graph 23 on second photomask 21 with respect to the last formation of the graphical first mask layer 203a moved, make the projection of second semiconductor device graph 23 on second mask layer 202 be positioned at the groove of the graphical first mask layer 203a.Be that mask carries out the shallow-layer exposure to second photoresist layer 206 with second photomask 21 again, second semiconductor device graph 23 on second photomask 21 is transferred on second photoresist layer 206, makes the degree of depth of the figure 207 on second photoresist layer 206 account for 5% to 10% of second photoresist layer, 206 thickness.The light source of shallow-layer exposure can be KrF, ArF, F
2Or extreme ultraviolet (Extreme ultraviolet, EUV) light source.And exposure intensity is 20mj/cm
2To 50mj/cm
2, concrete example such as 20mj/cm
2, 25mj/cm
2, 30mj/cm
2, 35mj/cm
2, 40mj/cm
2, 45mj/cm
2Or 50mj/cm
2The second photomask 2l can be scale-of-two shading value mask (Binary Intensity Mask), phase shift type mask version (Phase Shift Mask) or cell projection formula mask (Cell Projection Mask).Semiconductor device graph on second photomask 21 and first photomask 20 can be the same or different, and promptly can substitute second photomask 21 with first photomask 20.
Can also comprise the step that second photoresist layer is baked and banked up with earth in advance before the shallow-layer exposure, the temperature of baking and banking up with earth in advance is 100 ℃ to 120 ℃, concrete example is as 100 ℃, 105 ℃, 110 ℃, 115 ℃ or 120 ℃, the time of baking and banking up with earth in advance is 50 seconds to 70 seconds, and concrete example was as 50 seconds, 55 seconds, 60 seconds, 65 seconds or 70 seconds.
Execution in step S114 again, the figure 207 that is exposed by shallow-layer in the surface of second photoresist layer 206 carries out silanization to be handled, and forms graphical anti-plasma etching layer 207a on second photoresist layer 206.Being used to carry out the silanizing agent that silanization handles can be nitrogenous silane, concrete example such as hexamethyldisilazane (hexamethyldisilazane, C6H19NSi2), tetramethyl-disilazane (tetramethyldisilazane, C4H15NSi2), two (dimethylamino) methyl-monosilane (bis (dimethylamino) methylsilane, C5H16N2Si), two (dimethylamino) dimethylsilane (bis (dimethylamino) dimethylsilane, C6H18N2Si), dimethyl silyl dimethylamine (dimethylsilyldimethylamine, C4H13NSi), dimethyl silyl diethylamine (dimethylsilyldiethylamine, C6H17NSi), silica-based dimethylamine (the trimethylsilyldimethylamine of front three, C5H 15NSi), silica-based diethylamine (the trimethylsilyldiethylamine of front three, C7H19NSi) or (dimethylamino) pentamethyl disilane (dimethylaminopentamethyldisilane, C7H21NSi2).The process that silanization is handled is under the gas shield that low-pressure nitrogen, helium, argon gas, neon, oxygen or air etc. do not participate in reacting; provide silanizing agent to flow through the surface of second photoresist layer 206; make silanizing agent and react, generate noncrosslinking anti-plasma etching layer through the figure 207 of overexposure.The temperature of reaction is between 90 ℃ and 150 ℃, and concrete example is as 90 ℃, 95 ℃, 100 ℃, 105 ℃, 110 ℃, 115 ℃, 120 ℃, 125 ℃, 130 ℃, 135 ℃, 140 ℃, 145 ℃, 150 ℃.The pressure of reaction is between 10
-1.5MmHg and 10
-1Between the mmHg, concrete example is as 10
-1.5MmHg, 10
-1.4MmHg, 10
-1.3MmHg, 10
-1.2MmHg, 10
-1.1MmHg, 10
-1MmHg.Silanizing agent flows through the time on second photoresist layer, 206 surfaces between 80 seconds and 200 seconds, and concrete example was as 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, 130 seconds, 140 seconds, 150 seconds, 160 seconds, 170 seconds, 180 seconds, 190 seconds, 200 seconds.
Silanizing agent is after 206 surface reactions of second photoresist layer finish, can also toast the semiconductor-based end 200 that is coated with second photoresist layer 206, it is crosslinked that noncrosslinking anti-plasma etching layer is produced, and generates the stronger crosslinked graphical anti-plasma etching layer 207a of anti-plasma etching ability.
Main chemical reaction process comprises four reactions among step S113 and the S114: photo acid generator is in the sour environment second photoresist layer that is exposed by shallow-layer through discharging hydrogen particle (reaction 1) after the illumination; Alkyl phenoxy formic acid resin can be generated under acid condition alkylphenol (reaction 2) in second photoresist layer; Alkylphenol and nitrogenous silane reaction are generated alkyl phenoxy silane (reaction 3); Alkyl phenoxy silane is generated crosslinked under the condition that is heated between 60 ℃ and 80 ℃ to alkyl phenoxy silane (reaction 4).
As shown in figure 12, execution in step S115, with graphical anti-plasma etching layer 207a is mask, and second photoresist layer (figure does not show) is carried out dry plasma etch to exposing the graphical first mask layer 203a and second mask layer 202, forms the graphical second photoresist layer 206a.The plasma etching gas that is adopted is O
2, Ar, CF
4, CH
2F
2Or C
4F
8, preferred plasma etching gas is O
2It is vertical with semiconductor-based basal surface or approaching vertical to adopt dry plasma etch can make the second photoresist layer 206a go up the lines sidewall that forms, and can avoid described lines cross section T shape, inverted T-shaped, triangle, del, trapezoidal, trapezoidal, phenomenon that semicircle pushed up or do not have the top to occur.Dry plasma etch can also prevent that caving in from appearring in described lines.
With graphical first mask layer 203a and graphical anti-plasma etching layer 207a is mask, etching second mask layer 202 is to exposing the semiconductor-based end, remove the graphical first mask layer 203a, graphical anti-plasma etching layer 207a and the graphical second photoresist layer 206a again, form structure as shown in figure 13.Certainly, also can remove graphical anti-plasma etching layer 207a earlier, be mask with graphical first mask layer 203a and the graphical second photoresist layer 206a again, etching second mask layer 202 is removed graphical first mask layer 203a and the graphical second photoresist layer 206a again to exposing the semiconductor-based end.
Embodiment 2
Embodiment 1 is after having used the conventional method etching away from first mask layer at the semiconductor-based end, on second mask layer, form when having second photoresist layer of second semiconductor device graph, adopt the method for shallow-layer exposure-silanization-plasma etching associating, but the invention is not restricted to this, also can adopt the method for shallow-layer exposure-silanization-plasma etching associating when on first mask layer, forming first photoresist layer with first semiconductor device graph, as shown in figure 14, this method comprises:
Step S201 provides the semiconductor-based end with two-layer mask layer, and wherein second mask layer at first mask layer with at semiconductor-based the end;
Step S202 forms on first mask layer and contains photo acid generator and to first photoresist layer of alkyl phenoxy formic acid resin;
Step S203 form graphical first photoresist layer with the shallow-layer exposure, and the figure degree of depth on graphical first photoresist layer is less than the thickness of graphical first photoresist layer;
Step S204 carries out the silanization processing to the part of being exposed by shallow-layer in the graphical first photoresist layer surface, forms graphical anti-plasma etching layer on graphical first photoresist layer;
Step S205 is a mask with graphical anti-plasma etching layer, and first photoresist layer is carried out dry plasma etch to exposing first mask layer, forms graphical first photoresist layer;
Step S206 is a mask with graphical anti-plasma etching layer, and etching first mask layer is to exposing second mask layer, and removes graphical first photoresist layer and graphical anti-plasma etching layer;
Step S207, etching second mask layer.
In step S206, also can remove anti-plasma etching layer earlier, be mask with graphical first photoresist layer, etching first mask layer is to exposing second mask layer, and removes first photoresist layer.
The step S207 of etching second mask layer can be the lithographic method known to those skilled in the art, also can be among the embodiment 1 step S111 to the described method of step S116.
Step S202 is identical with step S112 to S116 among the embodiment 1 to step S206 in the present embodiment, and concrete technology can be with reference to the process conditions described in the embodiment 1.
Because the described method of present embodiment is used for first mask layer of etching away from the semiconductor-based end, and embodiment 1 described method is to be used for etching second mask layer after etching first mask layer, the two difference is the difference of step S111 among step S201 and the embodiment 1 in the present embodiment, what be that step S111 is provided among the embodiment 1 has two-layer mask layer at semiconductor-based the end, be etched out on first mask layer away from the semiconductor-based end and have the groove of semiconductor device graph, and second mask layer is not etched, had two-layer mask layer and step S201 provides in the present embodiment, first mask layer also is not etched at semiconductor-based the end.
Embodiment 3
When only having one deck mask layer, also can adopt the method for shallow-layer exposure-silanization-plasma etching associating when on mask layer, forming semiconductor device graph at semiconductor-based the end.As shown in figure 15, this method comprises:
Step S301 provides the semiconductor-based end with one deck mask layer;
Step S302 forms on mask layer and contains photo acid generator and to the photoresist layer of alkyl phenoxy formic acid resin;
Step S303 forms graphical photoresist layer with shallow-layer exposure, and on the photoresist layer degree of depth of figure less than the thickness of first photoresist layer;
Step S304 carries out the silanization processing to the part of being exposed by shallow-layer in the photoresist layer surface, forms graphical anti-plasma etching layer on photoresist layer;
Step S305 is a mask with the graphical anti-plasma etching layer on the photoresist layer, and photoresist layer is carried out plasma etching to exposing mask layer, forms graphical photoresist layer;
Step S306 is a mask with graphical anti-plasma etching layer, and the etch mask layer is to exposing the semiconductor-based end, and removes graphical first photoresist layer and graphical anti-plasma etching layer.
In step S306, also can remove graphical anti-plasma etching layer earlier, be mask with graphical photoresist layer, the etch mask layer is to exposing the semiconductor-based end, and removes graphical photoresist layer.
Step S302 is similar to step S112 to S116 among the embodiment 1 to step S306 in the present embodiment, and concrete technology can be with reference to the process conditions described in the embodiment 1.
By that analogy, the method of the shallow-layer exposure-silanization that embodiment 1, embodiment 2 and embodiment 3 are adopted-plasma etching associating can be used for having at the semiconductor-based end of some mask layers, from the semiconductor-based end farthest and the etching of the arbitrary layer of mask layer that is not etched.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. a graph transfer method is characterized in that, may further comprise the steps:
The semiconductor-based end, be provided, have second mask layer and first mask layer at described the semiconductor-based end successively, have the anti-reflecting layer and first photoresist layer on described first mask layer successively;
Behind graphical first photoresist layer of exposure formation, be mask with graphical first photoresist layer, etching anti-reflecting layer, first mask layer form graphical first mask layer and graphical anti-reflecting layer to exposing second mask layer;
After removing first photoresist layer and graphical anti-reflecting layer, on second mask layer and graphical first mask layer, form second photoresist layer, described second photoresist layer contains photo acid generator and to alkyl phenoxy formic acid resin, described is right-sec-butyl-phenoxy group t-butyl formate, right-sec-butyl-the phenoxy group sec.-butyl formate, right-sec-butyl-the phenoxy group isopropyl formate, right-isopropyl-the phenoxy group t-butyl formate, right-isopropyl-phenoxy group sec.-butyl formate or right-isopropyl-phenoxy group isopropyl formate to alkyl phenoxy formic acid resin;
Form graphical second photoresist layer by exposure, and the figure degree of depth on graphical second photoresist layer is less than the second photoresist layer thickness;
Use silanizing agent that silanization is carried out on the graphical second photoresist layer surface and handle, make to be exposed on graphical second photoresist layer and partly change graphical anti-plasma etching layer into;
With graphical anti-plasma etching layer is mask, and graphical second photoresist layer is carried out plasma etching to exposing graphical first mask layer and second mask layer;
With graphical anti-plasma etching layer and graphical first mask layer is mask, etching second mask layer.
2. photoetching method as claimed in claim 1 is characterized in that: the exposure intensity that described exposure forms graphical second photoresist layer is 20mj/cm
2To 50mj/cm
2
3. photoetching method as claimed in claim 1 is characterized in that: the figure degree of depth on described graphical second photoresist layer is 5% to 10% of the second photoresist layer thickness.
4. photoetching method as claimed in claim 1 is characterized in that: before the described step by graphical second photoresist layer of exposure formation, can also comprise the step that second photoresist layer is baked and banked up with earth in advance.
5. photoetching method as claimed in claim 4 is characterized in that: described temperature of baking and banking up with earth in advance is 100 ℃ to 120 ℃.
6. photoetching method as claimed in claim 4 is characterized in that: the described time of baking and banking up with earth in advance is 50 seconds to 70 seconds.
7. photoetching method as claimed in claim 1 is characterized in that: described silanization can also comprise the step that second photoresist layer is toasted after handling, and it is crosslinked that anti-plasma etching layer is produced.
8. photoetching method as claimed in claim 1 is characterized in that, described photo acid generator comprises sulphion hexafluoro antimonate or sulphion hexafluorophosphate.
9. photoetching method as claimed in claim 8 is characterized in that, described sulphion hexafluoro antimonate comprises triphenyl sulphur hexafluoro antimonate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluoro antimonate or two-[(4-diphenyl sulfide) phenyl] thioether-two-hexafluoro antimonate.
10. photoetching method as claimed in claim 8, it is characterized in that described sulphion hexafluorophosphate comprises triphenyl sulphur hexafluorophosphate, (4-thiophenyl-phenyl) diphenyl sulphur hexafluorophosphate or two-[(4-diphenyl sulfide) phenyl] sulfide-pairs-hexafluorophosphate.
11. photoetching method as claimed in claim 1, it is characterized in that described silanizing agent comprises hexamethyldisilazane, tetramethyl-disilazane, two (dimethylamino) methyl-monosilane, two (dimethylamino) dimethylsilane, dimethyl silyl dimethylamine, dimethyl silyl diethylamine, the silica-based dimethylamine of front three, the silica-based diethylamine of front three or (dimethylamino) pentamethyl disilane.
Photoetching method as claimed in claim 1 is characterized in that, carries out plasma etching gas and comprises O
2, Ar, CF
4, CH
2F
2Or C
4F
8
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| CN2008101125140A CN101587304B (en) | 2008-05-23 | 2008-05-23 | Pattern transferring method |
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|---|---|---|---|
| CN2008101125140A CN101587304B (en) | 2008-05-23 | 2008-05-23 | Pattern transferring method |
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| CN101587304B true CN101587304B (en) | 2011-11-30 |
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| EP3203499B1 (en) * | 2016-01-28 | 2018-10-17 | IMEC vzw | A method of patterning a target material layer |
| CN113327842A (en) * | 2020-02-28 | 2021-08-31 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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