CN101577535B - Device and method for sample rate conversion - Google Patents
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Abstract
Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a resampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.
Description
The application be that March 19, application number in 2004 are 200480010769.6 the applying date, denomination of invention divides an application for the original application of " sample rate conversion equipment and method ".
Technical field
The present invention relates generally to audio amplifier system, more particularly, the present invention relates to be used to change the input traffic with first sampling rate is the system and method with output stream of second data rate.
Background technology
Pulse width modulation (PWM) or D class signal amplification technique have existed for many years.Along with developing rapidly of switched-mode power supply (SMPS), pulse width modulating technology becomes more and more popular.Because the appearance of this technology, the interest of amplifying apply pulse width modulated technology in the application at signal is increasing, consequently obtain great effective improvement, this improvement replaces traditional (linear AB class) power output topological structure to realize by using D class power output topological structure.
The early stage trial that the exploitation signal amplify to be used used with early stage switched-mode power supply in used identical for the processing method of amplifying.More particularly, analog modulation scheme has been used in these trials, and this modulation scheme causes the application of low performance.These scheme implementations get up very complicated and very expensive.Therefore, these solutions are not adopted widely.Amplify in the application in main flow, the existing simulation embodiment of D class technology can't replace traditional class ab ammplifier.
Recently, digital pwm modulation schemes has been come out.These schemes have used ∑-Δ modulation technique to be created in the pulse width modulating signal that uses in the more new-type digital D class embodiment.Yet the contribution aspect the major obstacle of these digital pwm modulation schemes in alleviating the solution that pulse-width modulator is integrated in the whole amplifier is very few.Therefore, D class technology still can not replace traditional class ab ammplifier in mainstream applications.
Also there are a series of problems in the modulation scheme of current digital pulsewidth modulation.A problem is, the performance of the remainder of signal processing system and mass property are for different application and different.The strictness enforcement of whole system solution and terminal use's application are not conclusive.As a result, the details of prediction enforcement in advance.Because current Technology Need is at the solution of concrete application, these solutions are not really flexible in the ordinary course of things, and application not extendible or that not can be transferred to other is got on.Therefore, these technology not may be used in the main flow system in the ordinary course of things.
The concrete place that the modulation scheme of current digital pulsewidth modulation does not satisfy the main flow system requirements is the processing of flowing for the digital input data with various sampling rate.According to the type of the equipment that data are provided and the particular design of equipment, these digital input data streams can have different sampling rates.Input traffic can also use different clock sources, and different clock sources may have different slightly speed or some drift relative to one another.The single input sample speed of current specification requirement, perhaps a plurality of fixing known input rates, and can not be fit to the different speed that equipment can provide the input data.
Another problem of prior art systems is, because they do not have to produce local clock signals sampling speed conversion device, so they will rebuild the pulse width modulation clock signal from the input data in the ordinary course of things.The clock signal of this reconstruction can not be supported higher performance, and the clock signal that produces for this locality this may accomplish.
Summary of the invention
Can solve above-mentioned one or more problems by each embodiment of the present invention.In a broad sense, the present invention includes the combination that is used to use the hardware and software parts becomes digital input data stream second sampling rate from first sample rate conversion system and method.In one embodiment, the conversion of realization in the sample rate converter of digital audio system from first sampling rate to second sampling rate.Sample rate converter has a plurality of parts, and some parts are wherein implemented with hardware, some parts software implementation wherein.Each parts is implemented with hardware or is used software implementation, depends on the performance requirement of these parts.The parts that can obtain better performance with software are just used software implementation, and the parts that can obtain better performance with hardware are just implemented with hardware.Should be noted that not only aspect the tolerance of audio performance, and in complexity of calculation, parts " match " and the others to software engine, performance all is can be improved.
An embodiment comprises a sample rate converter system, and sample rate converter system comprises: rate estimator counters is configured to estimate the sampling rate of input traffic with it; The phase place selected cell is configured to select to be used for according to the sampling rate of estimation the phase place of one group of multiphase filter coefficient of interpolation with it; Coefficient interpolator, it is configured to can be according to selected phase interpolation filter coefficient so that increase phase resolution; Convolution unit, with its be configured to can the convolution interpolation filter coefficient and the sample of input traffic so that produce the sample of the output stream of resampling.As previously discussed, these system units comprise the hardware and software parts the two.In one embodiment, said system comprises two or more passages, and each passage wherein can both receive the input traffic with different, variable sampling rate, rather than the data flow that is received by other passage.In one embodiment, different passage and one or more public parts of other channels share.In one embodiment, sample rate converter system is coupled to an audio amplifier system, and it is configured to change input traffic is public output sampling rate, thereby can be handled by amplifier unit such as audio frequency effect unit or pulse-width modulator.
Another embodiment comprises a kind of method, the output stream that said method comprises the steps: to receive input traffic with input sample speed and uses the said input traffic of combined treatment of hardware and software parts to have the output sampling rate that is different from input sample speed with generation.In one embodiment, said processing comprises: estimation input sample speed, selection are used to insert said this group multiphase filter coefficient of phase place, interpolation, this final sample of organizing the sample of multiphase filter coefficient and input traffic and output stream being provided of convolution of one group of multiphase filter coefficient.In one embodiment, said method comprises: receive and handle two or more input traffics of the sampling rate with independent variable on passage independently, so that produce the output stream of the correspondence with a public output sampling rate.At least a portion processing for different data streams in different passages is carried out together with software part.
Many different embodiment also are possible.
Compare with prior art system, the two has series of advantages to use hardware component and software part.A possible advantage is, can implement processing speed and be those very important parts in the hardware of special use to give full play to their performance, implements more importantly other parts of flexibility simultaneously in software.Another possible advantage is, hardware and/or software can be by a plurality of channels share, with cost and the complexity that reduces system, and the flexibility that can also keep the speed of system simultaneously.Another possible advantage is, each passage all may be able to handle variable and with other passage on the irrelevant input sample speed of sampling rate of data flow.Another possible advantage is that local high performance Generation of Clock Signal can satisfy pulse width modulation output must be from importing the higher performance standard of situation that data rebuild out than clock signal.
According to the invention provides a kind of sample rate converter, described sample rate converter comprises a plurality of sample rate converter parts, and described sample rate converter comprises: rate estimator counters; Low pass filter, the output of wherein said rate estimator counters is by described low pass filter; Phase place selected cell, the output of wherein said low pass filter are provided for described phase place selected cell; Heterogeneous coefficient interpolator, wherein said heterogeneous coefficient interpolator produce the multiphase filter coefficient of one group of interpolation according to the output of described phase place selected cell; Convolution unit, it is configured to the multiphase filter coefficient of the described interpolation of convolution and the corresponding sample of input traffic; The input fifo queue, the described sample that it is configured to receive the sample of described input traffic and described input traffic is provided to described convolution unit; The output fifo queue, it is configured to receive the sample from the output stream of described convolution unit; And the first in first out administrative unit, it is coupled to described input fifo queue and described output fifo queue and is configured to provide feedback to described low pass filter; The first of wherein said parts comprises hardware component; And the second portion of wherein said parts comprises software part.
According to sample rate converter provided by the invention, wherein implement described rate estimator counters, described low pass filter and described heterogeneous coefficient interpolator with hardware.
According to sample rate converter provided by the invention, wherein use the described phase place selected cell of software implementation, described convolution unit and described first in first out administrative unit.
According to sample rate converter provided by the invention, wherein said rate estimator counters comprises a counter, described counter is configured to count the sampling period of described input traffic, and wherein calculates input sample speed by a software part according to the value of described counter.
According to sample rate converter provided by the invention, wherein said sample rate converter comprises two or more passages that are used to handle input traffic, the one or more parts in the described a plurality of sample rate converter parts of wherein said two or more channels share.
According to sample rate converter provided by the invention, wherein said sample rate converter comprises two or more passages that are used to handle input traffic, and each passage in wherein said two or more passages all is configured to handle the irrelevant input traffic of sampling rate of the input traffic that sampling rate and other passage handle.
According to sample rate converter provided by the invention, wherein each passage comprises independently rate estimator counters.
According to sample rate converter provided by the invention, wherein each rate estimator counters comprises independent sampling period counter.
According to sample rate converter provided by the invention, wherein each counter produces the independent counting of the sampling rate that is used to estimate corresponding input traffic in sampling period.
According to sample rate converter provided by the invention, wherein: a passage is the main channel in the described passage, and remaining channel is a secondary channel in the described passage; For described main channel estimating sampling speed, for each secondary channel, determine the corresponding sampling period counter and the ratio of the sampling period counter of described main channel, and the sampling rate of each secondary channel is confirmed as the described sampling rate of described main channel estimation be multiply by described ratio.
According to sample rate converter provided by the invention, wherein: each passage is implemented a multiphase filter; And the coefficient that is used for each multiphase filter embodiment is from one of filter coefficient shared group interpolation.
According to sample rate converter provided by the invention, wherein said sample rate converter is coupled to the pulse width modulation audio frequency amplifier.
According to the invention provides a kind of sample rate converter, described sample rate converter changes the digital input data circulation into predetermined output sampling rate (Fout), described sample rate converter comprises: the control path, and it is configured to receive the frame synchronizing signal that is associated with described input traffic and controls sample rate conversion; The voice data path, described voice data path comprises: the input fifo queue, it is configured to receive the sample of described input traffic; Convolution unit, it is configured to receive the output of described input fifo queue and the described sample and the filter coefficient of the described input traffic of convolution; And the output fifo queue, it is configured to receive the output of described convolution unit, and wherein sample can read from described output fifo queue with described output sampling rate (Fout); And the first in first out administrative unit, it is coupled to described input fifo queue and described output fifo queue and is configured to provide feedback to the low pass filter in described control path; Wherein said control path comprises the rate estimator counters counter, the number of the clock cycle between the sample that described rate estimator counters rolling counters forward is received; Wherein said control path comprises that also multiplexer is one of to select in the described rate estimator counters counter; The described low pass filter filtering in wherein said control path is corresponding to the sample rate count of selected rate estimator counters counter; And wherein be transferred to the phase place selected cell and be used for the multiphase filter interpolation filter coefficient through the sample rate count of filtering.
According to sample rate converter provided by the invention, wherein said feedback is used to stop overflowing or underflow of described input fifo queue and described output fifo queue.
According to sample rate converter provided by the invention, wherein said filter coefficient comprises the multiphase filter coefficient of interpolation.
According to sample rate converter provided by the invention, the described rate estimator counters counter in wherein said control path, described low pass filter and heterogeneous coefficient interpolator are implemented with hardware; And the described phase place selected cell software implementation in described control path.
According to sample rate converter provided by the invention, wherein: the described convolution unit software implementation in described voice data path; And described first in first out administrative unit software implementation.
According to the invention provides a kind of method, described method is used for the digital input data circulation is changed to predetermined output sampling rate (Fout), said method comprising the steps of: receive the frame synchronizing signal that is associated with described input traffic on the control path of control sample rate conversion; Come to produce counting by the number of counting the clock cycle between the sample that is received according to the described frame synchronizing signal that is associated with described input traffic; The described counting of low-pass filtering; And will be transferred to the phase place selected cell through the sample rate count of filtering and utilize described sample rate count to come to be the multiphase filter interpolation filter coefficient through filtering; Receive the sample of described input traffic at the input fifo queue; The described sample and the filter coefficient of the described input traffic of convolution, the described sample of described input traffic is exported from described input fifo queue; And exporting convolution has been carried out in the fifo queue reception with described filter coefficient sample, wherein sample can read from described output fifo queue with described output sampling rate (Fout); Management is by the stream of the sample of described input fifo queue and described output fifo queue; And provide feedback according to the described low pass filter that flows to described control path of the sample by described input fifo queue and described output fifo queue.
According to the method that is used for the digital input data circulation is changed to predetermined output sampling rate (Fout) provided by the invention, the described feedback that wherein is provided to the described low pass filter in described control path is used to regulate described low pass filter.
According to the invention provides a kind of digital audio amplification system, comprising: sample rate converter, it converts digital input data stream to predetermined output sampling rate (Fout) from input sample speed (Fin); Audio effects subsystem, it receives the digital data stream with described predetermined output sampling rate (Fout) from described sample rate converter, and described digital data stream is carried out handle, to produce treated digital data stream; Pulse-width modulator, it converts described treated digital data stream to pulse width modulating signal; And output stage, it amplifies described pulse width modulating signal to produce the signal that is exaggerated that can be used to drive speaker system; Wherein said sample rate converter comprises: the control path, and it is configured to receive the frame synchronizing signal that is associated with described input traffic and controls sample rate conversion; The voice data path, it comprises: the input fifo queue, it is configured to receive the sample of described input traffic; Convolution unit, it is configured to receive the output of described input fifo queue and the described sample and the filter coefficient of the described input traffic of convolution; And the output fifo queue, it is configured to receive the output of described convolution unit, and wherein sample can read from described output fifo queue with described output sampling rate (Fout); And the first in first out administrative unit, it is coupled to described input fifo queue and described output fifo queue and is configured to provide feedback to the low pass filter in described control path; Wherein said control path comprises the rate estimator counters counter, the number of the clock cycle between the sample that described rate estimator counters rolling counters forward is received; Wherein said control path comprises that also multiplexer is one of to select in the described rate estimator counters counter; The described low pass filter filtering in wherein said control path is corresponding to the sample rate count of selected rate estimator counters counter; And wherein be transferred to the phase place selected cell and be used for the multiphase filter interpolation filter coefficient through the sample rate count of filtering.
Description of drawings
Read following detailed and with reference to accompanying drawing after, other purpose of the present invention and advantage all will become apparent.
Fig. 1 is the functional block diagram that the digital audio amplification system of pulse width modulating technology is used in explanation;
Fig. 2 is the schematic diagram that explanation realizes the mode of sample rate conversion usually;
Fig. 3 is the interpolation and the schematic diagram that extracts with the corresponding signal that produces different sampling rates of the input signal of explanation sampling;
Fig. 4 is the schematic diagram of explanation according to the parts of the sample rate converter of one embodiment of the present of invention.
Though the present invention carries out various improvement and replacement form easily, also to represent its specific embodiment by example in the accompanying drawing and the detailed description that accompanies thereof.Yet, should be appreciated that, do not expect that accompanying drawing and detailed description limit the invention to described specific embodiment.On the contrary, the disclosure is intended to cover all modifications, equivalent and the alternative that drops in the scope of the present invention that is limited by the accompanying claims.
Embodiment
One or more embodiment of the present invention is described below.Be noted that these embodiment of describing below and any other embodiment are exemplary, be intended to illustrate the present invention rather than restriction the present invention.
As described herein, each embodiment of the present invention comprises that the combination of using the hardware and software parts becomes digital input data stream the system and method for second sampling rate from first sample rate conversion.As used herein, " hardware " refers to logical circuit special-purpose, that fixed function is arranged, on the other hand, " software " is used to quote the logical circuit that can programme, the said logical circuit that can programme is controlled by the algorithm of being determined by the programmer, perhaps utilize the general module that can programme under software control, said module is in the ALU (ALU) or memory of digital signal processor (DSP).
In one embodiment, in the sample rate converter of digital audio system, carry out conversion from first sampling rate to second sampling rate.Sample rate converter has a plurality of parts, and wherein some are implemented with hardware, wherein some software implementations.Each parts is with hardware enforcement or uses software implementation, depends on the performance requirement of parts.The parts that can obtain better performance with software are just used software implementation, and the parts that can obtain better performance with hardware are just implemented with hardware.As previously discussed, performance can wait with audio performance, computational complexity and measure, and wherein uses some metrics like this: the number in the processor cycle that computing is required, the capacity of equipment, implementation cost, flexibility, power consumption etc.
With according to conventional or complete with hardware or compare with the prior art system of software implementation entirely, the two may bring series of advantages the use hardware and software.For example, can in the hardware of special use, implement for processing speed very important components to give full play to their performance.For the other parts, the importance of processing speed is less than flexibility.These parts are embodied as software so that the flexibility of expectation is provided.Using the two another advantage of hardware and software parts is that some parts can be used for a plurality of passages.By between each passage, sharing some parts, can reduce the expense and the complexity of system, the speed and the flexibility that can also keep system simultaneously.
The preferred embodiments of the present invention are implemented in an audio amplifier system.As previously discussed, pulse width modulation (PWM) technology has obtained application recently in audio amplifier system, but but suffers from the shortcoming of conventional method.These methods have been used analog modulation scheme, but this scheme is complicated and expensive, and the performance of relative mistake is provided.On the contrary, system and method for the present invention is implemented in digital modulation scheme, and the method for using has solved some problem that exists in the prior art.
Referring now to accompanying drawing 1, wherein the functional block diagram of the digital audio amplification system of pulse width modulating technology is used in the expression explanation.In this embodiment, system 100 as CD Player, MP3 player, digital audiotape or analog, receives digital input data stream from a data source.Input traffic is received by sample rate converter 110.Input traffic has the specific sampling rate that depends on data source.This sampling rate is a kind of in one group of predetermined sampling rate being used by corresponding types equipment in the ordinary course of things.For example, the sampling rate of the numerical data that CD Player may be exported is 44.1 KHz, and the sampling rate of the numerical data that the digital audiotape player may be exported is 32 KHz.
According to system and method for the present invention, sample rate converter 110 conversion input traffics, the predetermined internal rate that the sample rate conversion when making it from reception becomes will use system 100.In one embodiment, this internal sample rate is 100 KHz.Like this, if receive data with the sampling rate of 50 KHz, then sample rate converter 110 will the said data of resampling, are the internal data flow of a correspondence of 100 KHz to produce sampling rate.This internal data flow offers audio effects subsystem 120 then.Any desired processing that audio effects subsystem 120 realizes for internal data flow, and the data flow that will finally handle offers PWM modulator 130.
The data flow that PWM modulator 130 receives is represented a pulse code modulation signal.PWM modulator 130 converts this data flow to pulse width modulating signal.Then pulse width modulating signal is offered output stage 140.In output stage 140, amplify pulse width modulating signal and can carry out certain filtering or further processing amplifying signal.Final signal outputs to speaker system 150 subsequently, and speaker system 150 becomes this electrical signal conversion the earcon that can be heard by the audience.
Emphasis of the present disclosure is the sample rate converter in above-mentioned audio system.As previously discussed, the purpose of sample rate converter is to receive the output stream of sampling with second sampling rate with the input traffic and the generation of first rate sampling.Though the audio signal by the data flow representative remains unchanged (at least in certain embodiments) basically, the change of sampling rate will meet the requirement of audio system and could be handled by this system.
Referring now to accompanying drawing 2, wherein the expression explanation realizes the schematic diagram of the mode of sample rate conversion usually.As shown in the drawings by this, at first pass through first filter 210 to up-sampling or interpolation input traffic, pass through second filter 220 then to down-sampling or extraction input traffic.Use a medial filter 230 to come low-pass filtering then to extract said data again to up-sampling to the data of up-sampling.Input traffic has the first sampling rate Fin.The upwards decimation factor of this data flow is M.So after up-sampling, the sampling rate of data flow is M * Fin.Thereby between up-sampling is normally by the sample at input traffic, carry out interpolation and produce that intermediate sample realizes.Select for M, so that intermediate samples speed (M * Fin) greater than the output sampling rate Fout that expects.In the ordinary course of things, intermediate rate is more much bigger than the output speed of expectation.
For carrying out filtering to the data flow of up-sampling and extracting then, so that sampling rate is reduced to the output speed of expectation from middle speed.After down-sampling, sampling rate is Fou=(M/N) * Fin.Data flow to down-sampling or to extract be to realize by abandoning from the sample of intermediary data stream in the ordinary course of things.For example, if be 100 KHz, then abandon a sample every a sample with the sample output sampling rate of intermediary data stream and hope of 200 KHz.
In the ideal case, M and N are integers.If M is an integer, then the upwards sampling of input traffic comprises M-1 new sample of insertion, and they are separated equably between each original samples.Then, if N is an integer, then the downward sampling of intermediary data stream comprises and only extracts each N sample, and remainder abandons.This situation is shown among Fig. 3.
Fig. 3 illustrates interpolation and extracts the input signal of sampling so that produce a schematic diagram of corresponding signal with different sampling rates.In this figure, the input sample is by point 301,306,311,316 expressions.The straight-line interpolation value of this signal is illustrated by the broken lines.The upwards decimation factor of this signal is 5, thus between every pair of adjacent sample 4 additional sampled points of interpolation.So, insertion point 302-305 in the interval between sample 301 and sample 306.Similarly, insertion point 306-311 in the interval between sample 307 and sample 311, insertion point 312-315 in the interval between sample 311 and sample 316.After the process low-pass filtering, the downward decimation factor of final point (301-316) is 3, so use each the 3rd point, remaining point is dropped.Final data stream comprises sample 301,304,307,310,313 and 316 (as shown by arrows).
Input traffic to up-sampling with to one of problem of the direct embodiment of down-sampling be, be integer in order to make M and N, and resolution in order to keep expecting, M and N normally count greatly.Consider the example of Fig. 3.If Fin is 60 KHz, Fout is 100 KHz, then M be 5 and N be 3.Yet,, must select M=200 and N=121 if Fin is 60.5 KHz rather than 60 KHz.Develop easily need be bigger even M and the situation of the value of N.According to the resolution of sample rate converter in a preferred embodiment, the value up to 218 may be necessary.
Another problem of interpolation and abstracting method is that the variation of handling the sampling rate of the data flow that is received may be very difficult.In typical audio system, each equipment or parts all may produce the clock signal that it is controlled oneself, and corresponding sampling rate just is based on this clock signal.Yet, be the same even expect the clock signal of two parts, these two clock signals can not be synchronous, may slightly change.Because have this difference in time signal, data just may be lost, perhaps buffer may overflow, and causes error.Design so that can handle these differences for sample rate converter of the present invention.
Should be noted that audio system can also comprise the audio-source of various type.For example, can pass through CD Player, MP3 player, digital audiotape or analog and produce audio signal.Can dispose these equipment has the audio signal of different sampling rates with generation.For example, the sampling rate of the output signal that CD Player provides is 44.1 KHz, and the sampling rate of the output signal that the digital audiotape player produces is 32 KHz.System and method of the present invention can make a plurality of different sampling rate in the sample rate converter adaptation input traffic.And sample rate converter can be regulated each passage independently to adapt to different input sample speed.By more as can be known, prior art system can only adapt to the different sampling rates on different passages under the known condition of two sampling rates.
By using multiphase filter can adapt to different sampling rates and the variation between these just often identical speed.Multiphase filter can be realized the two function of interpolater 210 and withdrawal device 220.By the interpolation input traffic, multiphase filter can be realized these functions by the interpolation input traffic, and the mode that realizes these functions does not need by make progress sampled data stream or by the downward sampled data stream of integer factor of integer factor.
In the ordinary course of things, above-mentioned interpolater and withdrawal device are embodied as (FIR type) filter.Multiphase filter obviously also is a kind of filter, but do not produce a large amount of sample (as being done) by interpolation filter, throw away unwanted sample then, and (as being done by decimation filter), multiphase filter only produces those final samples that still keeps.So, compare with the example of Fig. 3, not to produce sample 301-316, abandon 2/3 in these samples then, but only produce sample 301,304,307,310,313 and 316, do not abandon any one.
Determine multiphase filter by one group of filter coefficient.If these coefficients are extrapolated in the different coefficient sets, then can realize different sampling rates.This can realize non-integral sample rate conversion by selecting the suitable filters coefficient.
Use the typical sample rate converter of multiphase filter to comprise: be used to store memory from the sample of input traffic, be used for the memory filter coefficient memory, be used to filter coefficient to carry out the hardware that interpolation calculates and be used for calculated data and the multiply accumulating unit of the inner product of coefficient.In the ordinary course of things, these parts are to use specialized hardware to implement entirely.This is extremely expensive, and especially aspect the accessory logic circuit that calculates at needs and the private memory aspect that needs of input sampling data is more expensive.These memories are relatively little and therefore utilize the efficient of silicon area low relatively.Though also may use the software implementation sample rate converter fully, such embodiment necessary speed of voice applications that can not provide support in the ordinary course of things.
Therefore, system and method for the present invention utilize the combination of hardware and software parts be implemented in speed in the sample rate converter and efficient the two.These system and methods use the processor with enough big computing capability and memory capacity to realize desired parts.
Referring now to accompanying drawing 4, the schematic diagram of the parts of the sample rate converter of expression explanation one embodiment of the present of invention wherein.Corresponding to the data path of the voice data that will change, the upper half of Fig. 4 is corresponding to the control path that is used to control actual sample rate conversion substantially for the Lower Half of Fig. 4.
As shown in Figure 4, receive the sample of audio data stream, and it is stored in the input fifo queue (input FIFO) 405.The sampling rate of input traffic is Fin.Read sample and make said sample and one group of interpolation coefficient convolution from fifo queue 405 by convolution engine 410.Convolution engine 410 is effectively to up-sampling or to the said data of down-sampling, to produce the sample that speed equals the output speed (Fout) of sample rate converter.With these sample storage in output fifo queue (output FIFO) 406.From output fifo queue 406, read sample with speed Fout then.
The counter 421 of through-rate estimation device receives the frame synchronizing signal relevant with voice data with 422.The counter 421 and 422 of rate estimator counters is counted the number of the clock cycle between the sample that receives on each passage simply.Though (be noted that present embodiment has two passages and rate corresponding estimation device, other embodiment can also handle N passage and have N corresponding components group.) select one of rate estimator counters counter by multiplexer 430, and pass through the counting of low pass filter 440 filtering correspondences.Sample rate count through filtering is transferred to phase place selected cell 450, and is used to the multiphase filter interpolation filter coefficient.Then, in convolution unit 410, make the multiphase filter coefficient of interpolation and data sample convolution to produce the data of resampling.
Data sample is mobile by 407 management of first in first out administrative unit by fifo queue 405 and fifo queue 406.According to flowing of data, first in first out administrative unit 407 provides feedback to feedback unit 470.This feedback is used to regulate low pass filter 440.This regulates the sampling rate of estimation effectively, has therefore regulated the coefficient interpolation of carrying out in sample rate converter.Also regulated sample rate conversion thus, thereby can more closely follow the tracks of actual input sample speed and can prevent overflowing or underflow of fifo queue 405 and 406.
As can be seen, the parts of Fig. 4 or be hardware (HW) or for software (SW).In this embodiment, hardware component comprises input and output fifo queue 405,406, rate estimator counters 421,422, multiplexer 430, low pass filter 440 and coefficient interpolator 460.Implement these parts with hardware various reasons are arranged.For example, with the reason of hardware practice factor interpolater 460 be interpolation process must carry out fast enough in case provide will with the filter coefficient of data sample convolution in the convolution unit 410.Can be at an easy rate and implement the counter 421,422 of rate estimator counters expeditiously with hardware, this is because they are to need the simple counter upgraded fast, rather than complete rate estimation unit.The value of counter is read by software, and in fact said software carry out rate estimation (and in one embodiment, said software is shared for all passages).Feedback unit 470 available software are implemented efficiently, and the fifo queue 405 and 406 of input and output is to implement effectively in as the memory space of fifo queue control with software.In other words, fifo queue 405,406 is not implemented as small-sized independently memory, and has been to use the bigger memory space of digital signal processor.
In one embodiment, the counter 421,422 of rate estimator counters is the counter of 24 bits.Each counter can be selected from 4 incoming frame synchronizing signals: SAI LRCK; SPDIF RX frame synchronization; Grouped data frame synchronization; With ESSI frame synchronization.By the number of inside counting digital signal processor clock cycle during the count cycle of frame synchronizing signal, can measure performance period.Count cycle can programme, and the usually said cycle equals 1.In this embodiment, counting multiplies each other with gain.This gain is the integer of one 12 bit, usually this integer is arranged to 2 power, promptly equals to move a decimal point.This may be convenient to increase the resolution in the low pass filter 440.
In one embodiment, low pass filter 440 is iir filters of a second order.This filter for example can comprise the first order IIR filtering device of a pair of cascade.Low pass filter 440 decay are from the shake of the counting of the counter reception of rate estimator counters.So just can protect the variation of levying counting is slowly, and can improve the quality of sample rate conversion thus.The balancing procedure of being implemented by low pass filter has produced the possibility of alleviating underflow and overflowing.This problem solves by using the software implementation closed loop feedback, the deviation of one 24 bit of said software adjustment, and this deviation appends on the count value, and then makes this value by low pass filter 440.In one embodiment, the filter coefficient of low pass filter 440 can be regulated, thereby can carry out frequency and phase locking fast.
Coefficient interpolator 460 provides the ROM address generator of address to operate with the ROM of these coefficients of storage and the coefficient that uses for the retrieval interpolater.In fact filter coefficient is stored in two ROM, a storage even number coefficient, and another stores odd coefficients.Interpolater is carried out cubic spline interpolation.This interpolation has used the streamline of one 5 stage, two circulations to carry out interpolation, can make resource-sharing thus, can keep the throughput that per two clocks circulation has an interpolation simultaneously.
Parts with software implementation comprise: convolution unit 410, phase place selected cell 450, first in first out administrative unit 407 and feedback unit 470.The flexibility that can not provide in the strict hardware embodiment of prior art is provided these parts.The value of software part read-out speed estimation device 421,422, and from the definite input sample speed of these values.By can the regulations speed estimated value from the feedback of software part such as first in first out administrative unit 407 and feedback unit 470.Then, phase place selected cell 450 uses the speed interpolation multiphase filter coefficient of estimation, and carries out the convolution of these coefficients and input sample of data by convolution unit 410.Convolution unit 410 is to use software implementation, because typical digital signal processor can be realized this function effectively, can read sample and read coefficient from main storage from coefficient interpolator 460 simultaneously.
In one embodiment, the software of sample rate converter is responsible for carrying out the multi-task.For example, as previously discussed, the counter 421,422 of rate estimator counters multiplies each other their Counter Value separately and a gain, but this gain is determined by this software.Similarly, be used for determining by this software at the deviation and the filter coefficient of the low pass filter of rate estimator counters counter back.This software further also is responsible for calculating input sample speed (Fin) and the ratio of exporting sampling rate (Fout), and this ratio is fixed in a preferred embodiment.According to the ratio of sampling rate with the value of the counter of process filtering, said software is determined filter length, phase place and is used for the phase place increase of interpolation multiphase filter coefficient.And then this software also is responsible for convolution multiphase filter coefficient and input sample, management input and output fifo queue, and provide feedback to regulate the input sample speed of estimation.
In data processor, implement software part.Typical modern processors has carries out tight loop (tight loop) ability of sense data stream simultaneously extremely effectively.For example, digital signal processor (DSP) has the ability of " zero consumption circulation (zero overhead looping) ".Modern microcontroller also has the ability that each cycle carries out a plurality of instructions.These digital signal processors and microcontroller also have in the ordinary course of things makes it be suitable for the program of separating and the data storage of sample rate converter applications.
These processors have at a processor for example carries out the ability of described task down in the cycle: read a data sample (as by the indication of sampling pointer register) from memory, upgrade the sampling pointer register to point to next sample, to extract a coefficient value, go multiplier according to sample, addition data register (adding up) multiplication result with this coefficient value from peripheral coefficient interpolation unit.If multiphase filter comprises X coefficient, then use X clock cycle to calculate an output sample.
A processor can side by side be handled a series of parallel passage Y, and here, Y is subjected to the utilizable limited in number of accumulator and sampling pointer register.When using identical coefficient to handle Y passage simultaneously, the hardware that can design relative compact is in Y circulation or less than the following task of execution in Y the circulation: from memory, read a series of coefficients (as indicating), update coefficients pointer register, execution interpolation by the coefficient pointer with calculating filter coefficient to expected accuracy.
In " pseudo-C ", processor carries out following operation:
Be each output sample
Start the hardware coefficient calculator
for?j＝1?to?Y
O[Y]=0; // startup accumulator
P[Y]=start (N); // startup pointer
For i=1 to X // for each coefficient
C=mem[coeff] // coefficient read
For j=1toY // in each passage
o[Y]+＝C*mem[p[Y]++]
In the ordinary course of things, use the inner loop of j to be unfolded, reading of next coefficient can be carried out concurrently with last iteration (j=Y).A simple and effective processor may go out a new coefficient for the cycle calculations of each Y.One more flexibly solution may in Y circulation or less circulation, calculate a coefficient.When new sample becomes utilizable the time, stop this calculating, until till when reading this sample and therefore being adjusted to the speed that digital signal processor reads filter coefficient automatically.Except the actual value that makes Y more flexibly, this also will allow processor periodically to stop to calculate and function that other can be provided as interruption.
Embodiments of the invention can provide series of advantages, and these advantages are unavailable in the prior art.For example, the combination of hardware and software parts can allow system and method for the present invention to provide higher speed and flexibility at the aspect of performance of sample rate converter function with high level, and this is all by hardware or be out of the question in the prior art systems with software implementation all.Their enforcement efficient is than prior art height.
Implement in the side at some, the parts of sample rate converter can independently be shared between the sample rate conversion paths two or more.For example, same multiphase filter coefficient interpolation hardware can be used in two different paths, wherein may comprise ROM, address generator and the interpolater of packing coefficient itself.At the other example of resources shared on the sample rate conversion paths is the data processor of carrying out the software part on the path separately.Although resources shared is arranged, each sample rate conversion paths all realizes separately sample rate conversion function with other path independence ground.
At least the additional advantage of some embodiment of the present invention is to handle the input traffic of the sampling rate with the variation of allowing.Because each sample rate conversion paths all comprises a sampling rate estimation device, be used for determining input sample speed, and comprise various parts, be used for the function at this input sample modifying rates sample rate converter, the variation of sampling rate produces error so this sample rate converter is not easy.A relevant advantage is to revise two different sample rate conversion paths independently at the input traffic with different sampling rates.
Another advantage is to simplify the embodiment of some parts of sample rate converter.For example, in one embodiment, all comprise a simple counter for the rate estimator counters hardware of each sample rate conversion paths.This counter can be read by a software part at an easy rate, can determine the sampling rate of input traffic then according to the value of counter.
Will be understood by those skilled in the art that, use any one technology in the various different technologies can representative information and signal.For example, can represent data, instruction, order, information, signal, bit, symbol and the chip of in above whole described content, quoting by voltage, electric current, electromagnetic wave, magnetic field or particle, light field or particle or their combination in any.Use any suitable transmission medium, comprising lead, metallic traces, through hole, optical fiber or analog, can be between each parts of disclosed system exchange message and signal.
Those of ordinary skill in the art should be realized that various illustrative logical block, module, circuit and the algorithm steps described in conjunction with embodiment disclosed herein may be embodied as electronic hardware, computer software or the combination of the two.In order to clearly demonstrate this interchangeability of hardware and software, more than according to the function describe, in general terms various illustrative parts, logical block, module, circuit and step.These functions still are as software implementation as hardware, depend on specific application and the design constraints restrict forced on whole system.Those of ordinary skill in the art can implement described function according to the different modes of each application-specific, but the determining should not be construed as and departed from scope of the present invention of such embodiment.
Being combined in various illustrative logical block, module and circuit that embodiment disclosed herein describes can utilize any combination that is used to realize function described herein of general processor, digital signal processor (DSP) or other logical device, application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA), discrete gate circuit or transistor-transistor logic circuit, discrete hardware component or they to implement or realize.General processor can be processor, controller, microcontroller, state machine or the analog of any routine.Processor can also be embodied as the combination of calculation element, for example combination of digital signal processor and microprocessor, a plurality of microprocessor, the one or more microprocessors that combine with digital signal processor core or any other such configuration.
Software that the method for describing in conjunction with embodiment disclosed herein or the step of algorithm can be carried out with hardware, by processor or firmware module or their combination are directly implemented.Software product can reside in RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or the storage medium of any other form of being known in the art in.A typical storage medium is coupled on the processor so that processor can be from said storage medium sense information and can writing information in the storage medium.In replaceable scheme, storage medium can be integrated into processor.Processor and storage medium can reside in the application-specific integrated circuit (ASIC).Application-specific integrated circuit (ASIC) can reside in user terminal.In replaceable scheme, processor and storage medium can reside in the user terminal as discrete parts.
The purpose described above that disclosed embodiment is provided is to make those of ordinary skill in the art can make and use the present invention.Various improvement for these embodiment is easy to become obviously for the person of ordinary skill of the art, General Principle described herein can be applied to other embodiment and can not depart from design of the present invention and scope.Like this, do not expect to limit the present invention to the embodiments described herein, the present invention meets and principle disclosed herein and new Ying's feature the wideest consistent scope.
Abovely benefit and advantage that the present invention can provide have been described with reference to specific embodiment.These benefits and advantage, and the element or the restriction that these advantages are taken place or become outstanding more are not considered to the feature of key, the necessary or essence of any one claim or all claim.As used herein, expectation " comprises term " or its any other version, is construed to and not exclusively is included in element or the restriction that occurs after these terms.Therefore, system, a method or comprise that other embodiment of a set of pieces is not limited to have only these elements, can also comprise other element that obviously do not list or claimed embodiment itself is intrinsic.
Though described the present invention with reference to certain embodiments, should be appreciated that these embodiment are illustrative, scope of the present invention is not limited to these embodiment.For above-described embodiment, many variations, modification, increase or improvement all are possible.Can expect that these variations, modification, increase or improvement all will fall within the scope of the invention.
Claims (20)
1. sample rate converter, described sample rate converter comprises a plurality of sample rate converter parts, described sample rate converter comprises:
Rate estimator counters;
Low pass filter, the output of wherein said rate estimator counters is by described low pass filter;
Phase place selected cell, the output of wherein said low pass filter are provided for described phase place selected cell;
Heterogeneous coefficient interpolator, wherein said heterogeneous coefficient interpolator produce the multiphase filter coefficient of one group of interpolation according to the output of described phase place selected cell;
Convolution unit, it is configured to the multiphase filter coefficient of the described interpolation of convolution and the corresponding sample of input traffic;
The input fifo queue, the described sample that it is configured to receive the sample of described input traffic and described input traffic is provided to described convolution unit;
The output fifo queue, it is configured to receive the sample from the output stream of described convolution unit; And
The first in first out administrative unit, it is coupled to described input fifo queue and described output fifo queue and is configured to provide feedback to described low pass filter;
The first of wherein said parts comprises hardware component; And
The second portion of wherein said parts comprises software part.
2. the sample rate converter of claim 1, wherein said rate estimator counters, described low pass filter and described heterogeneous coefficient interpolator are implemented with hardware.
3. the sample rate converter of claim 1, wherein said phase place selected cell, described convolution unit and described first in first out administrative unit software implementation.
4. the sample rate converter of claim 1, wherein said rate estimator counters comprises a counter, described counter is configured to count the sampling period of described input traffic, and wherein calculates input sample speed by a software part according to the value of described counter.
5. the sample rate converter of claim 1, wherein said sample rate converter comprises two or more passages that are used to handle input traffic, the one or more parts in the described a plurality of sample rate converter parts of wherein said two or more channels share.
6. the sample rate converter of claim 1, wherein said sample rate converter comprises two or more passages that are used to handle input traffic, and each passage in wherein said two or more passages all is configured to handle the irrelevant input traffic of sampling rate of the input traffic that sampling rate and other passage handle.
7. the sample rate converter of claim 6, wherein each passage comprises independently rate estimator counters.
8. the sample rate converter of claim 7, wherein each rate estimator counters comprises independent sampling period counter.
9. the sample rate converter of claim 8, wherein each sampling period counter produces the independent counting of the sampling rate that is used to estimate corresponding input traffic.
10. the sample rate converter of claim 8, wherein:
A passage is the main channel in the described passage, and remaining channel is a secondary channel in the described passage;
For described main channel estimating sampling speed,
For each secondary channel, determine the corresponding sampling period counter and the ratio of the sampling period counter of described main channel, and
The sampling rate of each secondary channel is confirmed as the described sampling rate of described main channel estimation be multiply by described ratio.
11. the sample rate converter of claim 6, wherein:
Each passage is implemented a multiphase filter; And
The coefficient that is used for each multiphase filter embodiment is from one of filter coefficient shared group interpolation.
12. the sample rate converter of claim 1, wherein said sample rate converter is coupled to the pulse width modulation audio frequency amplifier.
13. a sample rate converter, described sample rate converter changes the digital input data circulation into predetermined output sampling rate (Fout), and described sample rate converter comprises:
The control path, it is configured to receive the frame synchronizing signal that is associated with described input traffic and controls sample rate conversion;
The voice data path, described voice data path comprises:
The input fifo queue, it is configured to receive the sample of described input traffic;
Convolution unit, it is configured to receive the output of described input fifo queue and the described sample and the filter coefficient of the described input traffic of convolution; And
The output fifo queue, it is configured to receive the output of described convolution unit, and wherein sample can read from described output fifo queue with described output sampling rate (Fout); And
The first in first out administrative unit, it is coupled to described input fifo queue and described output fifo queue and is configured to provide feedback to the low pass filter in described control path;
Wherein said control path comprises the rate estimator counters counter, the number of the clock cycle between the sample that described rate estimator counters rolling counters forward is received;
Wherein said control path comprises that also multiplexer is one of to select in the described rate estimator counters counter;
The described low pass filter filtering in wherein said control path is corresponding to the sample rate count of selected rate estimator counters counter; And
Wherein the sample rate count through filtering is transferred to the phase place selected cell and is used for the multiphase filter interpolation filter coefficient.
14. the sample rate converter of claim 13, wherein said feedback are used to stop overflowing or underflow of described input fifo queue and described output fifo queue.
15. the sample rate converter of claim 13, wherein said filter coefficient comprise the multiphase filter coefficient of interpolation.
16. the sample rate converter of claim 13, the described rate estimator counters counter in wherein said control path, described low pass filter and heterogeneous coefficient interpolator are implemented with hardware; And
The described phase place selected cell software implementation in described control path.
17. the sample rate converter of claim 16, wherein:
The described convolution unit software implementation in described voice data path; And
Described first in first out administrative unit software implementation.
18. a method that is used for the digital input data circulation is changed to predetermined output sampling rate (Fout) said method comprising the steps of:
On the control path of control sample rate conversion, receive the frame synchronizing signal that is associated with described input traffic;
Come to produce counting by the number of counting the clock cycle between the sample that is received according to the described frame synchronizing signal that is associated with described input traffic;
The described counting of low-pass filtering; And
To be transferred to the phase place selected cell through the sample rate count of filtering and utilize described sample rate count to come to be the multiphase filter interpolation filter coefficient through filtering;
Receive the sample of described input traffic at the input fifo queue;
The described sample and the filter coefficient of the described input traffic of convolution, the described sample of described input traffic is exported from described input fifo queue;
Receive the sample that has carried out convolution with described filter coefficient at the output fifo queue, wherein sample can read from described output fifo queue with described output sampling rate (Fout);
Management is by the stream of the sample of described input fifo queue and described output fifo queue; And
The described low pass filter that flows to described control path according to the sample by described input fifo queue and described output fifo queue provides feedback.
19. the method for claim 18, the described feedback that wherein is provided to the described low pass filter in described control path is used to regulate described low pass filter.
20. a digital audio amplification system comprises:
Sample rate converter, it converts digital input data stream to predetermined output sampling rate (Fout) from input sample speed (Fin);
Audio effects subsystem, it receives the digital data stream with described predetermined output sampling rate (Fout) from described sample rate converter, and described digital data stream is carried out handle, to produce treated digital data stream;
Pulse-width modulator, it converts described treated digital data stream to pulse width modulating signal; And
Output stage, it amplifies described pulse width modulating signal to produce the signal that is exaggerated that can be used to drive speaker system;
Wherein said sample rate converter comprises:
The control path, it is configured to receive the frame synchronizing signal that is associated with described input traffic and controls sample rate conversion;
The voice data path, it comprises:
The input fifo queue, it is configured to receive the sample of described input traffic;
Convolution unit, it is configured to receive the output of described input fifo queue and the described sample and the filter coefficient of the described input traffic of convolution; And
The output fifo queue, it is configured to receive the output of described convolution unit, and wherein sample can read from described output fifo queue with described output sampling rate (Fout); And
The first in first out administrative unit, it is coupled to described input fifo queue and described output fifo queue and is configured to provide feedback to the low pass filter in described control path;
Wherein said control path comprises the rate estimator counters counter, the number of the clock cycle between the sample that described rate estimator counters rolling counters forward is received;
Wherein said control path comprises that also multiplexer is one of to select in the described rate estimator counters counter;
The described low pass filter filtering in wherein said control path is corresponding to the sample rate count of selected rate estimator counters counter; And
Wherein the sample rate count through filtering is transferred to the phase place selected cell and is used for the multiphase filter interpolation filter coefficient.
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| US45642903P | 2003-03-21 | 2003-03-21 | |
| US60/456,429 | 2003-03-21 | ||
| US46976103P | 2003-05-12 | 2003-05-12 | |
| US60/469,761 | 2003-05-12 |
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| CNB2004800107696A Division CN100511980C (en) | 2003-03-21 | 2004-03-19 | Sampling speed converter and method thereof |
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| CN101577535B true CN101577535B (en) | 2011-06-15 |
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| CN101521497A (en) * | 2009-04-14 | 2009-09-02 | 北京中星微电子有限公司 | Self-adapting up-sampling filter |
| CN101540749B (en) * | 2009-04-22 | 2012-09-26 | 吕正德 | Implementation method and device of pretreatment unit capable of being configured with length-variable DFT |
| CN104718761A (en) * | 2012-07-09 | 2015-06-17 | 日本电信电话株式会社 | Video image encoding/decoding method, device, program, recording medium |
| FR3015754A1 (en) * | 2013-12-20 | 2015-06-26 | Orange | RE-SAMPLING A CADENCE AUDIO SIGNAL AT A VARIABLE SAMPLING FREQUENCY ACCORDING TO THE FRAME |
| CN104008080B (en) * | 2014-06-17 | 2017-06-27 | 杭州士兰微电子股份有限公司 | serial data analysis method and device |
| US9560465B2 (en) * | 2014-10-03 | 2017-01-31 | Dts, Inc. | Digital audio filters for variable sample rates |
| CN104301085B (en) * | 2014-10-23 | 2017-08-29 | 西安空间无线电技术研究所 | A kind of Perfect Reconstruction Substrip analysis device of resource multiplex |
| CN106205651A (en) * | 2016-06-30 | 2016-12-07 | 乐视控股（北京）有限公司 | Sample rate method for transformation, device and terminal |
| CN113126530B (en) * | 2019-12-30 | 2022-03-18 | 珠海极海半导体有限公司 | Method for calculating sampling rate of timer filter and control device |
| CN112925293B (en) * | 2021-01-25 | 2022-09-06 | 东风电子科技股份有限公司 | Method, system, device, processor and storage medium for realizing detection aiming at different load feedback waveforms of BCM (binary coded modulation) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986589A (en) * | 1997-10-31 | 1999-11-16 | Ati Technologies, Inc. | Multi-stream audio sampling rate conversion circuit and method |
| US6061410A (en) * | 1997-02-27 | 2000-05-09 | Advanced Micro Devices | Frequency ratio estimation arrangement and method thereof |
| CN1371179A (en) * | 2001-02-20 | 2002-09-25 | 三星电子株式会社 | Sample rate converting device and method |
-
2004
- 2004-03-19 CN CNB2004800107696A patent/CN100511980C/en not_active Expired - Fee Related
- 2004-03-19 CN CN2009101384826A patent/CN101577535B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6061410A (en) * | 1997-02-27 | 2000-05-09 | Advanced Micro Devices | Frequency ratio estimation arrangement and method thereof |
| US5986589A (en) * | 1997-10-31 | 1999-11-16 | Ati Technologies, Inc. | Multi-stream audio sampling rate conversion circuit and method |
| CN1371179A (en) * | 2001-02-20 | 2002-09-25 | 三星电子株式会社 | Sample rate converting device and method |
Non-Patent Citations (2)
| Title |
|---|
| Park 等.A Novel Structure for Real-Time Digital Sample-Rate Converters with Finite Precision Error Analysis.1991 International Conference on Acoustics, Speech, and Signal Processing.1991,53613-3616. |
| Park等.A Novel Structure for Real-Time Digital Sample-Rate Converters with Finite Precision Error Analysis.1991 International Conference on Acoustics, Speech, and Signal Processing.1991,53613-3616. * |
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| CN101027837A (en) | 2007-08-29 |
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