CN101572264A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- CN101572264A CN101572264A CNA2008101101305A CN200810110130A CN101572264A CN 101572264 A CN101572264 A CN 101572264A CN A2008101101305 A CNA2008101101305 A CN A2008101101305A CN 200810110130 A CN200810110130 A CN 200810110130A CN 101572264 A CN101572264 A CN 101572264A
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Abstract
In a semiconductor integrated circuit device having a volatile memory therein, high-speed operation is enabled and the density of the memory can be enhanced. The volatile memory includes a word line, a complementary bit line having bit lines, a plurality of common source lines, and a memory cell that is coupled with the word line and the complementary bit lines. The memory cell includes transistors. The gate electrodes of the transistors are coupled with the word line, and the drain electrode of one of the transistors is coupled with one of the bit lines. The drain electrode of the other transistor is coupled with the other bit line. The respective source electrodes of the transistors are coupled with any one of the common source lines, or brought in a floating state, thereby storing storage information in the memory cell.
Description
The cross reference of related application
This by with reference to introduce on April 30th, 2008 and June 11 in 2007 bu you can well imagine the Japanese patent application No.2008-118506 of friendship and whole disclosures of No.2007-153541, comprise specification, accompanying drawing and summary.
Technical field
The present invention relates to semiconductor device, more specifically, include effect and be used to comprise for example technology of the system LSI (large scale integrated circuit) of the nonvolatile memory of mask model ROM (read-only memory).
Background technology
The inventor has studied the following technology among the ROM in being assemblied in system LSI for example.
For example, have the ROM that is assemblied in the system LSI, wherein the configuration of the word of ROM mainly is medium-scale and large-scale, and in order to obtain stable and operation at a high speed, memory cell array is the paratope line structure, to carry out read operation at a high speed by differential reading-out amplifying.The ROM of paratope line structure comprises memory cell, word line, paratope line and the differential reading-out amplifying that is connected with paratope line.Each memory cell comprises a pair of first and second MOS transistor, and it has the gate electrode that is connected with same word line respectively.A source/drain electrode of first and second MOS transistor is connected with the respective bit line of paratope line BL and BLB respectively.Another source/drain electrode of first MOS transistor is connected with the voltage signal line that is applied with given voltage (common source line), and another source/drain electrode of second MOS transistor is in floating.
As the method for write data in above-mentioned ROM, there is a kind of like this method, wherein according to the existence of the through hole between the first metal layer and second metal level/do not exist, in the source electrode of nmos pass transistor or drain electrode, produce the existence that is electrically connected/do not exist.In addition, there is a kind of method, wherein produces the existence that is electrically connected/do not exist according to the existence of the through hole between diffusion layer and the first metal layer/do not exist.
Figure 18 illustrates the example of the configuration of the ROM memory cell of having studied as prerequisite of the present invention.Figure 18 illustrates to be used for two the memory cell and the equivalent electric circuit of connection thereof.Dispose actual memory array by this way, make memory cell on array, arrange and be connected according to configuration of required word and row configuration.In Figure 18, each among MC (1) and the MC (2) be corresponding to the memory cell that is used for, and form separately that the grid of the MOS transistor of memory cell is connected with WL1 with word line WL0 respectively.In addition, the drain electrode of the MOS transistor in the memory cell is connected with BL with bit line BLB.Any one right source electrode of transistor in the memory cell is connected with common source line CS by the setting of the contact layer on the layout patterns.That is, the ROM perforated layer is contact (CONTACT) layer, and according to the writing information that is provided with of the contact layer of the source electrode of two MOS transistor on it.By connecting common source line CS and arbitrary transistorized source electrode, any of bit line BLB and BL is connected with common source line CS when selecting any of word line WL0 and WL1, thereby feasiblely can cause in bit line BLB or BL that the electromotive force change is with reading cells information.More specifically, be high level and when making common source line CS be low level when making word line WL0, the electromotive force that has been pre-charged to BLB among the bit line BL of high level and the BLB descends.Electromotive force change among the BLB is read out amplifier amplifies, thereby makes location information to be read.Equally, be high level and when making common source line CS be low level, the electromotive force of BL descends to read information among bit line BL and the BLB when making word line WL1.
Figure 19 (a) and Figure 19 (b) illustrate the schematic layout pattern that is used for two ROM memory cell corresponding to equivalent electric circuit shown in Figure 18.Figure 19 (a) be the diffusion layer (Diffusion) that forms MOS transistor, grid layer (GATE) are shown, as the first metal layer (Metal1) of the extraction electrode of source electrode and drain electrode and be connected diffusion layer and the diagram of the layout patterns of the contact layer of the first metal layer (CONTACT).Two contact layers that are positioned at middle body are to be used to be connected the drain electrode of MOS transistor and the layer of bit line BL and BLB with the first metal layer.The grid layer (GATE) that is positioned at the both sides of middle body forms word line WL0 and WL1 respectively.In addition, be arranged in its outside contact layer and the first metal layer be to be used to connect into arbitrary source electrode of right upper and lower MOS transistor and the layer of common source line CS.That is, the ROM perforated layer is contact (CONTACT) layer, and according to the writing information that is provided with of the contact layer of the source electrode of two MOS transistor on it.The grid layer that forms in its outside is the separation grid that is used for the MOS transistor of separating adjacent memory cell.
Figure 19 (b) is the schematic diagram of layout patterns that the upper strata of Figure 19 (a) is shown.Bit line BL and BLB are formed by second metal level (Metal2), and are connected with the first metal layer as lower floor's MOS transistor source electrode by via hole 1 (Via1).Common source line CS is also formed by second metal level (Metal2), and is connected with the first metal layer as lower floor's MOS transistor drain electrode by via hole 1 (Via1).Word line WL0 and WL1 are formed by the 3rd metal level (Metal3).The word line WL0 that forms by the grid layer of Figure 19 (a) and WL1 with unshowned word in the layout of Figure 19 (a) and Figure 19 (b) along separate routes pattern (word shuntpattern) be connected with WL1 with the word line WL0 that the 3rd metal level by Figure 19 (b) forms.Word is the needs that reduce according to the word line resistance device of pattern and regular arrangement along separate routes, for example, and per four or eight.
Figure 20 illustrates the example that is connected of ROM memory cell and differential reading-out amplifying.Paratope line BL is connected with gb1b with global bit line gb1 by the row switch with BLB.Global bit line gb1 is connected with the lead-out terminal of differential reading-out amplifying, equalizer and output latch with gb1b.
Figure 21 illustrates the connection diagram of ROM memory cell.As shown in Figure 21, any of MOS transistor is connected with the CS line with the storage data by the ROM perforation.The MOS transistor of not carrying out the ROM perforation as yet is as switch, and it changes the electromotive force of bit line b1 or b1b, even select word line w1.Yet the diffusion capacitance of the MOS transistor that is connected with b1b with bit line b1 is equal to each other.As a result, the input capacitance of differential reading-out amplifying becomes balanced.This has realized stable high speed reads extract operation.
Figure 22 illustrates the sequential chart that the ROM memory cell of having studied as prerequisite of the present invention is passed through the read operation of common source control system.Read operation is begun by the operation that synchronously obtains the address in the control circuit with the forward position of clock.Is high level based on address signal and reading command order from control circuit output from one of decoder driving word-line signal w1.In this operation example, select word line w1 n+3.In addition, drive one of Y switch controlling signal yse[n:0] be high level, and bit line b1 and b1b and global bit line gb1 and gb1b are connected to each other by the Y switch.On the other hand, driving common source line CS is low level.Driving word line w1n+3 is high level, and to drive common source line CS be low level, and the result is, the electrical potential difference between bit line b1 and the b1b increases according to the information of write storage unit.When the electrical potential difference between bit line b1 and the b1b is increased to a certain degree, export sense amplifier enable signal sae to carry out amplifieroperation by sense amplifier from control circuit.Then, the electrical potential difference between global bit line gb1 and the gb1b increases to high level and low level.When the electrical potential difference between global bit line gb1 and the gb1b increases, according to sense data counter-rotating output latch.When sense data is in initial condition or when identical with last sense data, output latch is nonreversible, and keeps this data.
In the ROM of this configuration because the common source line CS that is connected with the source node of memory cell and the bit line b1 that is connected with its drain node and b1b the two during the cycle except that time for reading, be set to Vdd, so significantly reduce at the leakage current of storage area.In addition, when when selecting word that CS selection timing is set later on, can reduce influence (leakage current) to not selecting memory cell.
As technology, there is for example disclosed technology in the open No.2005-327339 of Japanese unexamined patent about above-mentioned ROM.
Summary of the invention
Incidentally, as the inventor result of the technology of above-mentioned semiconductor device after deliberation, proved following theme.
For example, under the situation of the memory cell of above-mentioned paratope line structure, can realize high speed operation.Yet, because a memory cell needs two transistors, and can not store more than a blocks of data, therefore see that from the viewpoint of density this is disadvantageous.
Under above-mentioned environment, the purpose of this invention is to provide a kind of technology, it can carry out high speed operation and improve storage density in the semiconductor device wherein have nonvolatile memory.
In addition, in the above-mentioned technology of semiconductor device, according to the existence that is connected of the MOS transistor that forms memory cell and bit line/the do not exist programming of carrying out memory cell.Usually, the contact of the first metal layer wiring by the bit line on drain diffusion layer and its upper strata or the first metal layer that is connected with drain diffusion connect up be positioned at its upper strata on the existence that contacts/do not exist and programme of second metal line.In this system, determine this program before should in the initial relatively stage of semiconductor fabrication process, finishing lower metal, and in the manufacturing process latter half, can not rewrite the program of memory cell.For example, this problem occurs, promptly, can not rewrite when having finished the main body Wiring technique when in program, comprising under the situation of mistake (bug).
Under above-mentioned environment, another object of the present invention provides a kind of technology, wherein can be in the latter half of semiconductor fabrication process in the wiring of upper strata write memory.
Above-mentioned and other purposes of the present invention and novel feature will become clear from description of the invention and accompanying drawing.
The characteristic feature of the present invention of Miao Shuing is with as described below in this application.
That is what, semiconductor device according to the present invention related to is the semiconductor device with nonvolatile memory.Memory cell that nonvolatile memory comprises word line, comprises the paratope line of first and second bit lines, first, second is connected with paratope line with the 3rd common source line, with word line and the differential reading-out amplifying that is connected with paratope line.Memory cell comprises first and second transistors, and the first and second transistorized gate electrodes are connected with word line, and the drain electrode of the first transistor is connected with first bit line, and the drain electrode of transistor seconds is connected with second bit line.First and second transistorized each source electrode are connected with first, second any with the 3rd common source line, perhaps are in floating, thus in memory cell store storage information.
In addition, nonvolatile memory comprises word line, comprises the paratope line, first to the 5th common source line of first and second bit lines, the memory cell that is connected with paratope line with word line and the differential reading-out amplifying that is connected with paratope line.Memory cell comprises first and second transistors, the first and second transistorized gate electrodes are connected with word line, the drain electrode of the first transistor is connected with first bit line, the drain electrode of transistor seconds is connected with second bit line, any of first and second transistorized each source electrode and first to the 5th common source line or a plurality ofly be connected or be in floating, thus in memory cell store storage information.
The advantage that the characteristic feature of describing in this application of the present invention obtains is with as described below.
Because can store up a plurality of data values a memory cell, so improved storage density.
Description of drawings
Fig. 1 is the block diagram that illustrates according to the configuration of the semiconductor device of first embodiment of the invention;
Fig. 2 is the schematic diagram that illustrates according to the configuration of the ROM in the semiconductor device of first embodiment of the invention;
Fig. 3 is the circuit diagram that illustrates according to the configuration of the storage mat major part in the semiconductor device of first embodiment of the invention;
Fig. 4 is the circuit diagram that the control circuit (L/H output) according to the common source line in the semiconductor device of first embodiment of the invention is shown;
Fig. 5 (a) and Fig. 5 (b) are the layouts that illustrates according to the configuration of the storage mat major part in the semiconductor device of first embodiment of the invention, wherein Fig. 5 (a) illustrates the metal of source/drain and MOS, and Fig. 5 (b) illustrates the metal of MOS source electrode;
Fig. 6 is the layout that illustrates according to the configuration of the storage mat major part in the semiconductor device of first embodiment of the invention, and wherein Fig. 6 illustrates being connected of CS line and MOS source electrode;
Fig. 7 (a) and Fig. 7 (b) are the layouts that illustrates according to the configuration of the storage mat major part in the semiconductor device of first embodiment of the invention, wherein Fig. 7 (a) illustrates the ROM rewriting of the 3rd metal level, and Fig. 7 (b) illustrates being connected of CS line and the 3rd metal level;
Fig. 8 (a) is the cross-sectional view of being got along the A-A ' line of Fig. 5 (a), Fig. 5 (b) and Fig. 6, and Fig. 8 (b) is the cross-sectional view of being got along the B-B ' line of Fig. 5 (a), Fig. 5 (b) and Fig. 6;
Fig. 9 (a) is the cross-sectional view of being got along the C-C ' line of Fig. 7 (a) and Fig. 7 (b), and Fig. 9 (b) is the cross-sectional view of being got along the D-D ' line of Fig. 7 (a) and Fig. 7 (b).
Figure 10 is the state diagram that illustrates according to the selected address in the semiconductor device of first embodiment of the invention, internal state and data output;
Figure 11 is the sequential chart that illustrates according to the read operation in the semiconductor device of first embodiment of the invention;
Figure 12 is the circuit diagram that illustrates according to the configuration of the storage mat major part in the semiconductor device of second embodiment of the invention;
Figure 13 is the circuit diagram that the control circuit (L/H/Hi-Z output) according to the common source line in the semiconductor device of second embodiment of the invention is shown;
Figure 14 is the state diagram that illustrates according to the selected address in the semiconductor device of second embodiment of the invention, internal state and data output;
Figure 15 is the block diagram that illustrates according to the summary configuration of the ROM in the semiconductor device of third embodiment of the invention;
Figure 16 is the circuit diagram that illustrates according to the configuration of the storage mat major part in the semiconductor device of third embodiment of the invention;
Figure 17 is the state diagram that illustrates according to the selected address in the semiconductor device of third embodiment of the invention, internal state and data output;
Figure 18 is the schematic diagram of example of the configuration of the ROM memory cell studied as prerequisite of the present invention;
Figure 19 (a) and Figure 19 (b) are the schematic diagrames of example of the configuration of the ROM memory cell studied as prerequisite of the present invention, and wherein Figure 19 (a) illustrates the metal of MOS and source/drain, and Figure 19 (b) illustrates the metal of bit line and MOS source electrode;
Figure 20 is the circuit diagram of example of the configuration of the ROM memory cell studied as prerequisite of the present invention and differential reading-out amplifying;
Figure 21 is the schematic diagram of example of the connection of the ROM memory cell studied as prerequisite of the present invention; And
Figure 22 is the sequential chart of the read operation of the ROM memory cell of passing through the common source control system studied as prerequisite of the present invention.
Embodiment
Below, provide the description of embodiments of the present invention with reference to the accompanying drawings in more detail.At the institute's drawings attached that is used for describing execution mode, represent same parts by same-sign in principle, and will omit it and be repeated in this description.
First execution mode
Fig. 1 is the block diagram that illustrates according to the configuration of the semiconductor device of first embodiment of the invention, Fig. 2 is the schematic diagram that illustrates according to the configuration of the ROM in the semiconductor device of first execution mode, Fig. 3 is the circuit diagram that the configuration of storage mat major part is shown, Fig. 4 is the circuit diagram of control circuit (L/H output) that the common source line is shown, Fig. 5 (a), Fig. 5 (b), Fig. 6, Fig. 7 (a) and Fig. 7 (b) are the layouts of storage mat, Fig. 8 (a) and Fig. 8 (b) are Fig. 5 (a), Fig. 5 (b), the cross-sectional view of Fig. 6, Fig. 9 (a) and Fig. 9 (b) are the cross-sectional views of Fig. 7 (a) and Fig. 7 (b), Figure 10 illustrates selected address, the state diagram of internal state and data output, and Figure 11 is the sequential chart that read operation is shown.
At first, will provide description with reference to Fig. 1 according to the example of the configuration of the semiconductor device of first execution mode.Semiconductor device according to first execution mode relates to for example system LSI 100, and forms on a semiconductor chip by known semiconductor fabrication.System LSI 100 comprises for example ROM 101, RAM 102, CPU (CPU) 103, bus control unit 104 and the various IP 105 of user logic.
Be equipped with the various IP of user logic 105 and read the system program that is stored among the ROM 101 and the system LSI 100 of the CPU 103 of operation in because the reading performance of ROM 101 influences the performance of whole system, so require the ROM 101 of high speed operation.As recent trend, storage has been stored in the data among the RAM and has been necessary with the ROM 101 of the speed operation identical with RAM.
The configuration of ROM 101 will be described with reference to Fig. 2 subsequently.
Fig. 3 illustrates the part of storage mat 201.In storage mat 201, a plurality of word line WL, many to paratope line BLT and BLB and common source line CS, CS1 and CS2 with matrix arrangements, and a plurality of memory cell MC is arranged in their intersection point place.Memory cell MC has the first MOS transistor M1 and the second MOS transistor M2, and its gate electrode connects with corresponding word line WL jointly.The drain electrode of two MOS transistor M1 and M2 is connected with BLB with paratope line BLT, and its source electrode is connected with any of common source line CS, CS1 and CS2, perhaps suspension joint.According to which is connected with the source electrode of MOS transistor M1 and M2 among common source line CS, CS1 or the CS2, determine the logical value of stored information.
For example, under the situation of memory cell MC (n), the gate electrode of MOS transistor M1 is connected with word line WL (n), and drain electrode is connected with paratope line BLT, and the source electrode is in floating.The gate electrode of MOS transistor M2 is connected with word line WL (n), and drain electrode is connected with paratope line BLB, and the source electrode is connected with common source line CS.When selecting common source line CS1, because common source line CS becomes " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".When selecting common source line CS2, because common source line CS becomes " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".
In addition, under the situation of memory cell MC (n+1), the gate electrode of MOS transistor M1 is connected with word line WL (n+1), and drain electrode is connected with paratope line BLT, and the source electrode is connected with common source line CS2.The gate electrode of MOS transistor M2 is connected with word line WL (n+1), and drain electrode is connected with paratope line BLB, and the source electrode is connected with common source line CS1.When selecting common source line CS1, because common source line CS1 becomes " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".When selecting common source line CS2, because common source line CS2 becomes " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".
In addition, under the situation of memory cell MC (n+2), the gate electrode of MOS transistor M1 is connected with word line WL (n+2), and drain electrode is connected with paratope line BLT, and the source electrode is connected with common source line CS1.The gate electrode of MOS transistor M2 is connected with word line WL (n+2), and drain electrode is connected with paratope line BLB, and the source electrode is connected with common source line CS2.When selecting common source line CS1, because common source line CS1 becomes " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".When selecting common source line CS2, because common source line CS2 becomes " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".
In addition, under the situation of memory cell MC (n+3), the gate electrode of MOS transistor M1 is connected with word line WL (n+3), and drain electrode is connected with paratope line BLT, and the source electrode is connected with common source line CS.The gate electrode of MOS transistor M2 is connected with word line WL (n+3), and drain electrode is connected with paratope line BLB, and the source electrode is in floating.When selecting common source line CS1, because common source line CS becomes " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".When selecting common source line CS2, because common source line CS2 becomes " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".
As mentioned above, the signal of common source line CS1 and CS2 switches, thereby makes can store two data in a memory cell.
Fig. 4 illustrates the examples of circuits of the CS control circuit 204 of the signal that generates common source line CS, CS1 and CS2.All be under the situation of " H " level at two common source CS1 and CS2 only, precharging signal csp becomes " L " level.That is, be under the situation of " L " level in any of common source CS1 and CS2, common source CS becomes " L " level, and precharging signal csp becomes " H " level.
Fig. 5 (a), Fig. 5 (b) illustrate the part of the layout of storage mat to Fig. 7 (a), Fig. 7 (b).Fig. 5 (a), Fig. 5 (b) are illustrated in the layout corresponding to the storage mat at the part place of the equivalent electric circuit of Fig. 3 to Fig. 7 (a), Fig. 7 (b).Fig. 5 (a) illustrates the layout patterns of the metal level (metal1) of the diffusion layer (Diffusion) of MOS transistor and source/drain electrode.It is two rectangular that diffusion layer has that each row vertically arranges, and repeat layout patterns according to the size of storage mat.Grid layer (GATE) has the laterally memory cell grille utmost point from word line WL (n) to WL (n+3) arranged alternate, and repeats layout patterns according to the size of storage mat.Word line WL is the grid layer of horizontal expansion, and word line resistance increases and increase along with columns, and this causes service speed to reduce.In this case, along separate routes pattern is parallel to column direction and arranges, and grid layer is connected with the transverse metal wiring on upper strata, thereby feasiblely can prevent the resistance increase.Inserting the interval of shunt pattern can suitably select according to the occasion needs, for example, and per four or per eight.Source/the drain electrode of the MOS transistor that is formed by diffusion layer and grid layer is connected with the first metal layer (Metal1) by contact layer (CONTACT).In addition, via hole 1 (Via1) is arranged in the outside on the first metal layer of drain electrode of MOS transistor, and on the first metal layer of disposed inboard at source electrode.Via hole 1 is the through hole that connects the first metal layer and second metal level.Fig. 5 (b) illustrates the layout patterns as second metal level (Metal2) of bit line BLT and BLB and the 3rd metal level (Metal3) that is connected with the source electrode of MOS transistor.Fig. 5 (b) is the layout patterns as the upper strata formation of Fig. 5 (a).Two-layer (Metal2) that form bit line BLT and BLB forms in a longitudinal direction.Bit line BLT is connected by the first metal layer of via hole 1 with drain electrode shown in Fig. 5 (a) with BLB, and this drain electrode that lists MOS transistor is connected with BLB with bit line BLT.Second metal layer pattern with source electrode pattern equal number in Fig. 5 (b) vertically is arranged on the first metal layer of source electrode among Fig. 5 (a), and this first metal layer is by guiding to corresponding second metal level on the via hole 1.The 3rd metal level (Metal3) transverse arrangement of turbo and is connected with second metal level by via hole 2 (Via2) on second metal level.That is, the layout patterns of drain electrode by Fig. 5 (a) and Fig. 5 (b) of MOS transistor is connected to each other independently on the right side and left among the storage mat, and on guide to the bit line BLT and the BLB of second metal level.The source electrode of MOS transistor is all guided to the 3rd metal level on independently.Fig. 6 is the layout patterns that is connected of expression the 3rd metal level (Metal3) that is connected with the source electrode of MOS transistor and the 4th metal level (Metal4) that forms common source line CS, CS1 and CS2.The 3rd metal level that connects with the source electrode of MOS transistor is identical with the 3rd metal level of Fig. 5 (b).Via hole 3 suitably is arranged in the 3rd metal level (Metal3) and forms the cross part office of the 4th metal level (Metal4) of common source line CS, CS1 and CS2, and the source electrode of MOS transistor is connected with CS2 with common source line CS, CS1.The connection of using via hole 3 is corresponding to this program stored.That is, the information that is stored in the memory cell can be according to which is connected with CS2 with common source line CS, CS1 and writes in BLB side source electrode and the BLT side source electrode.The information that has write in Fig. 6 is the information identical with the information of equivalent electric circuit shown in Fig. 3, and layout patterns has identical annexation.
In ROM according to first execution mode, because the formation position according to via hole 3 after forming the 3rd metal level writes ROM information, so compare with using contact layer, the first metal layer or the second metal level rewrite information, can carry out the rewriting in the latter half of manufacturing process.That is because even carry out wrong correction in the back in the technology, so the degree of freedom of design alternative increases, this reduces for cost is effective.
Fig. 7 (a) and Fig. 7 (b) illustrate the layout patterns by the improvement example of the 3rd metal level (Metal3) programming ROM.In this case, the layout patterns up to second metal level is identical with the layout patterns of Fig. 5 (a) and Fig. 5 (b).In Fig. 7 (a), the source electrode of MOS transistor is guided to second metal level on independently, in Fig. 5 (b), and guides to the 3rd metal level of transverse arrangement of turbo on independently by second via layer.The pattern of three the 3rd metal levels is arranged between the 3rd right metal level of BLT side MOS source electrode and BLB side MOS source electrode independently.The patterned arrangement of those three the 3rd metal levels is used to be connected to form common source line CS, CS1 and the 4th metal level (Metal4) of CS2 and the source electrode of MOS transistor that is arranged on the upper strata.Pattern by suitably connecting three the 3rd metal levels and the 3rd metal level of BLT side MOS source electrode and BLB side MOS source electrode are realized the program of ROM.In this embodiment, go up most pattern and BLT side MOS source electrode that memory cell connects middle the 3rd metal level, and memory cell connects the pattern and the BLT side MOS source electrode of the left side the 3rd metal level on second, and connects the pattern and the BLB side MOS source electrode of the right the 3rd metal level.Memory cell connects the left side the 3rd metal level and BLB side MOS source electrode on the 3rd, and connects the right the 3rd metal level and BLT side MOS source electrode.Descend most memory cell to connect the pattern and the BLB side MOS source electrode of middle the 3rd metal level.Three metal levels suitably are provided with aforesaid connecting wiring, thereby realize the program of ROM.Wiring pattern in this embodiment is identical with the routine plan of ROM shown in Fig. 3 and Fig. 6.
Fig. 7 (b) illustrates the 4th metal level (Metal4) on upper strata and the layout that is connected of the 3rd metal level shown in Fig. 7 (a).The 3rd metal level shown in Fig. 7 (b) is identical with the 3rd metal level shown in Fig. 7 (a).The 4th metal level is arranged on the column direction as three common source line CS, CS1 and CS2.Each common source line CS, CS1 and CS2 are connected by the pattern of three the 3rd metal levels on via hole 3 (Via3) and the 3rd metal level that is arranged in lower floor.Via hole 3 allows BLT side MOS source electrode to be connected with BLB side MOS source electrode any with common source line CS, CS1 and CS2, thereby finishes the pattern as ROM.In this embodiment, because the formation position according to the 3rd metal level writes ROM information, so with use contact layer, the first metal layer or the second metal level rewrite information to compare in Fig. 5 (a), Fig. 5 (b) and the execution mode shown in Fig. 6, can carry out the rewriting in the latter half of manufacturing process.That is because even can in the technology of back, carry out wrong correction, so the degree of freedom of design alternative increases, this reduces for cost is effective.
Fig. 8 (a) is the cross-sectional view of being got along the A-A ' line of Fig. 5 (a), Fig. 5 (b) and Fig. 6, and Fig. 8 (b) is the cross-sectional view of being got along the B-B ' line of Fig. 5 (a), Fig. 5 (b) and Fig. 6.
Fig. 9 (a) is the cross-sectional view of being got along the C-C ' line of Fig. 7 (a) and Fig. 7 (b), and Fig. 9 (b) is the cross-sectional view of being got along the D-D ' line of Fig. 7 (a) and Fig. 7 (b).Figure 10 illustrates common source line CS, CS1 and the state of CS2 and the example that data are exported the relation of Q of selected address A, ROM.For example, when reading to select word line WL (n) when the address is " 0 " and " 1 ", when reading to select common source line CS1 when the address is " 0 ", when reading to select common source line CS2 when the address is " 1 ".That is, for example, when the address was " 0 " and " 1 ", selected word line was WL (n), and the memory cell that reads is same, but was different according to the selection mode sense data of common source line CS, CS1 and CS2.
Figure 11 illustrates the read operation timing of ROM 101.The storage cycle of clock signal definition ROM101.Clock signal is a high-frequency clock, its frequency be equal to CPU 103 the operation reference clock signal frequency or for its part.The WL signal is commonly referred to as " word line ".Symbol " yes＜n:0〉" is commonly referred to as array selecting signal.By the one-period definition memory cycle of clock signal.Begin to make address signal effectively (V) in the memory cycle.Then, column selection operation beginning, and the word line selection operation begins.Paratope line BLT, BLB and common source line CS, CS1, CS2 are pre-charged to supply voltage Vdd select regularly up to arriving word line, or after and then arriving word line and selecting regularly.Then, the operation of precharge paratope line BLT and BLB stops, and is being later than the timing that precharge operation stops, and common source line CS, CS1 and CS2 begin discharge.In this case, common source line CS1 or CS2 become " L " level.When yse (0)=" H ", satisfy CS1=" L ", and when yse (1)=" H ", satisfy CS2=" L ".
The bit line precharge operation stop and common source line CS, CS1 and CS2 discharge after, information stores state according to the memory cell MC that has selected by word line WL, promptly, which is connected with the source electrode of MOS transistor M1 and M2 among common source line CS, CS1 and the CS2, makes any discharge of paratope line BLT and BLB.Differential reading-out amplifying 205 detects its change, and complementally drives complementary global bit line gb1 and gb1b.The complementary signal that occurs in complementary global bit line gb1 and gb1b is output latch 208 and latchs, with decision sense data Q.
After the amplifieroperation of decision differential reading-out amplifying 205, finish the column selection operation.Be synchronized with this decision, paratope line BLT and BLB and common source line CS, CS1 and CS2 are pre-charged to supply voltage Vdd once more.
Therefore, according to the semiconductor device of present embodiment, so the layout that has not changed MOS transistor quantity because realized increasing common source line quantity is need be corresponding to the memory cell area of wiring quantity.Yet, in same memory cell, can store a plurality of data values.
Second execution mode
Figure 12 is the circuit diagram that illustrates according to the configuration of the storage mat major part in the semiconductor device of second embodiment of the invention.Figure 13 is the circuit diagram of control circuit (L/H/Hi-Z output) that the common source line is shown.Figure 14 is the state diagram that selected address, internal state and data output are shown.
Semiconductor device according to second execution mode is another topology example of the ROM 101 in the system LSI 100 in first execution mode.Figure 12 illustrates the part of the storage mat that forms ROM101.The storage mat of ROM has a plurality of word line WL, many pairs of bit line BLT, BLB and common source line CS, CS1, CS2, CS3 and the CS4 with matrix arrangements in second execution mode.A plurality of memory cell MC are arranged in the place, crosspoint of these lines.Memory cell MC has the first MOS transistor M1 and the second MOS transistor M2, and its gate electrode connects with corresponding word line WL jointly.The two has MOS transistor M1 and M2 the drain electrode that is connected with BLB with paratope line BLT, is connected with any of common source line CS, CS1, CS2, CS3 and CS4 or the source electrode of suspension joint.According to which is connected to determine the logical value of stored information with the source electrode of MOS transistor M1 and M2 among common source line CS, CS1, CS2, CS3 and the CS4.
For example, under the situation of memory cell MC (n), the gate electrode of MOS transistor M1 is connected with word line WL (n), and drain electrode is connected with paratope line BLT, and the source electrode is in floating.The gate electrode of MOS transistor M2 is connected with word line WL (n), and drain electrode is connected with paratope line BLB, and the source electrode is connected with common source line CS.When selecting any of common source line CS1, CS2, CS3 and CS4, because common source line CS becomes " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".
In addition, under the situation of memory cell MC (n+1), the gate electrode of MOS transistor M1 is connected with word line WL (n+1), and drain electrode is connected with paratope line BLT, and the source electrode is connected with common source line CS3.The gate electrode of MOS transistor M2 is connected with word line WL (n+1), and drain electrode is connected with paratope line BLB, and the source electrode is connected with CS with common source line CS1, CS2.When selecting any of common source line CS1, CS2 and CS4, because common source line CS1, CS2 and CS4 become " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".When selecting common source line CS3, because common source line CS3 becomes " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".
In addition, under the situation of memory cell MC (n+2), the gate electrode of MOS transistor M1 is connected with word line WL (n+2), and drain electrode is connected with paratope line BLT, and the source electrode is connected with CS2 with common source line CS1.The gate electrode of MOS transistor M2 is connected with word line WL (n+2), and drain electrode is connected with paratope line BLB, and the source electrode is connected with CS4 with common source line CS3.When selecting common source line CS1 and CS2, because common source line CS1 and CS2 become " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".When selecting any of common source line CS3 and CS4, because common source line CS3 and CS4 become " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".
In addition, under the situation of memory cell MC (n+3), the gate electrode of MOS transistor M1 is connected with word line WL (n+3), and drain electrode is connected with paratope line BLT, and the source electrode is connected with CS4 with common source line CS3.The gate electrode of MOS transistor M2 is connected with word line WL (n+3), and drain electrode is connected with paratope line BLB, and the source electrode is connected with CS2 with common source line CS1.When selecting any of common source line CS1 and CS2, because common source line CS1 and CS2 become " L ", paratope line BLT becomes " H ", and paratope line BLB becomes " L ", and complementary global bit line gb1 becomes " H ".When selecting any of common source line CS3 and CS4, because common source line CS3 and CS4 become " L ", paratope line BLT becomes " L ", and paratope line BLB becomes " H ", and complementary global bit line gb1 becomes " L ".
As mentioned above, the signal of common source line CS1 and CS2 switches, thereby makes can store four data (16) in a memory cell.Yet, during read operation, need only selected common source line to be set to " L ", and other common source lines are set to " Hi-Z " (high impedance).During standby, all common source lines are set to " H ", and all word lines are set to " L ".
Similarly, in storage mat according to second execution mode, by using and the identical mode of layout patterns shown in Fig. 5 (a), Fig. 5 (b), Fig. 6 or Fig. 7 (a) and Fig. 7 (b), common source line CS, CS1, CS2, CS3 and the CS4 of the 4th metal level are provided, thereby carry out the ROM program, make the connection of existence by via hole 3/do not exist or the 3rd metal level, carry out the connection of the source electrode of MOS transistor.
Figure 13 illustrates the examples of circuits of the CS control circuit 204 of the signal that generates common source line CS, CS1, CS2, CS3 and CS4.Figure 13 is the circuit of L/H/Hi-Z (high impedance) output.
Figure 14 illustrates the example of the relation of selected address A, ROM internal state and data output Q.For example, when reading to select word line WL (n) when the address is " 0 ", " 1 ", " 2 " and " 3 ", when reading to select common source line CS1 when the address is " 0 ", when reading to select common source line CS2 when the address is " 1 ", when reading to select common source line CS3 when the address is " 2 ", when reading to select common source line CS4 when the address is " 3 ".
The 3rd execution mode
Figure 15 is the block diagram that illustrates according to the summary configuration of the ROM in the semiconductor device of third embodiment of the invention.Figure 16 is the circuit diagram that the configuration of storage mat major part is shown.Figure 17 is the state diagram that selected address, internal state and data output are shown.
Semiconductor device according to the 3rd execution mode is another topology example of the ROM 101 in the system LSI 100 in first execution mode.Figure 15 illustrates the dual-port ROM of the data that can read different addresses simultaneously.Address terminal A is arranged in Qa side and Qb side independently, thereby realizes two reading.
Figure 16 illustrates the part of the storage mat that forms ROM 101.The storage mat of ROM in the 3rd execution mode has a plurality of word line WL, many pairs of bit line BLTa, BLBa, BLTb, BLBb and common source line CSa, CS1a, CS2a, CSb, CS1b and the CS2b with matrix arrangements.A plurality of memory cell MC are arranged in the place, crosspoint of those lines.Memory cell MC has the first MOS transistor M1a, the second MOS transistor M2a, the 3rd MOS transistor M1b and the 4th MOS transistor M2b, and its gate electrode connects with corresponding word line WL jointly.The drain electrode of MOS transistor M1a and M2a is connected with BLBa with paratope line BLTa, and the drain electrode of MOS transistor M1b and M2b is connected with BLBb with paratope line BLTb.The source electrode of MOS transistor M1a and M2a is connected or suspension joint with any of common source line CSa, CS1a and CS2a.The source electrode of MOS transistor M1b and M2b is connected or suspension joint with any of common source line CSb, CS1b and CS2b.According to which is connected to determine the logical value of stored information with the source electrode of MOS transistor M1a, M2a, M1b and M2b in the common source line.
As mentioned above, can be controlled at paratope line BLTa, BLBa, MOS transistor M1a, M2a and common source line CSa, CS1a, the CS2a of a side and independently at paratope line BLTb, BLBb, MOS transistor M1b, M2b and common source line CSb, CS1b, the CS2b of b side.This makes the data of different addresses to be read simultaneously.Yet, during read operation, need only selected common source line to be set to " L ", and other common source lines are set to " Hi-Z " (high impedance).During standby, all common source lines are set to " H ", and all word lines are set to " L ".
Self-evident, in storage mat according to the 3rd execution mode, by using and the identical mode of layout patterns shown in Fig. 5 (a), Fig. 5 (b), Fig. 6 or Fig. 7 (a) and Fig. 7 (b), common source line CSa, CS1a, CS2a, CSb, CS1b and the CS2b of the 4th metal level are provided, and can carry out the ROM programming, make the connection of existence by via hole 3/do not exist or the 3rd metal level, carry out the connection of the source electrode of MOS transistor.
Figure 17 illustrates the example of the relation of selected address A, ROM internal state and data output Q.For example, select word line WL (n) when being " 0 ", " 1 ", " 2 " and " 3 " when reading the address, when reading to select common source line CS1a and CS1b when the address is " 0 ", and when reading address selection common source line CS2a and CS2b when being " 1 ".In Figure 17, A1 and A0 are column selections, and A3 and A2 are that row is selected.
Below describe the present invention in detail based on execution mode.Yet, the invention is not restricted to above-mentioned execution mode, but can make various modifications under the premise of without departing from the spirit of the present invention.In addition, above-mentioned first to the 3rd execution mode can suitably be combined.
The present invention can be widely used in having the semiconductor device of nonvolatile memory, for example microcomputer or system LSI.
Claims (12)
1. semiconductor device comprises:
Word line;
The paratope line that comprises first and second bit lines;
Two or more N common source lines; And
Memory cell, it is connected with described paratope line with described word line;
Wherein said memory cell comprises first and second transistors,
The wherein said first and second transistorized grids are connected with described word line,
The source electrode of wherein said the first transistor or drain electrode are connected with described first bit line;
The source electrode of wherein said transistor seconds or drain electrode are connected with described second bit line;
The source electrode or drain different source electrodes or the drain electrode that connect with bit line in wherein said first and second transistors are connected with any of N common source line with first, perhaps are in floating, with store storage information in described memory cell.
2. according to the semiconductor device of claim 1,
Wherein during the read operation of described memory cell, the described first common source line changes first current potential into, and any of N common source line changes first current potential into.
3. according to the semiconductor device of claim 1,
The data of wherein said storage unit stores therein N position.
4. according to the semiconductor device of claim 1,
Wherein by the M metal level wiring that is connected to form the first common source line and N common source line and (M-1) metal wiring layer that is connected with described first and second transistor drain or source electrode, carry out the writing of data in the described memory cell.
5. a semiconductor device has nonvolatile memory, and described nonvolatile memory comprises:
Word line;
The paratope line that comprises first and second bit lines;
First, second and the 3rd common source line;
Memory cell, it is connected with described paratope line with described word line; And
Differential reading-out amplifying, it is connected with described paratope line,
Wherein said memory cell comprises first and second transistors,
The wherein said first and second transistorized gate electrodes are connected with described word line,
The drain electrode of wherein said the first transistor is connected with described first bit line,
The drain electrode of wherein said transistor seconds is connected with described second bit line, and
Wherein said first and second transistorized each source electrode are connected with any of described first, second and the 3rd common source line, perhaps are in floating, with store storage information in described memory cell.
6. according to the semiconductor device of claim 5,
Wherein during the read operation of described memory cell, the described first common source line changes first current potential into, and any of the described second and the 3rd common source line changes first current potential into.
7. according to the semiconductor device of claim 5,
Wherein said nonvolatile memory is in two data of a memory cell storage.
8. according to the semiconductor device of claim 5,
Wherein carry out the writing of data in the described memory cell with the wiring of the M metal level of the 3rd common source line and (M-1) metal wiring layer that is connected with described first and second transistor drain by being connected to form the described first common source line and second.
9. a semiconductor device has nonvolatile memory, and described nonvolatile memory comprises:
Word line;
The paratope line that comprises first and second bit lines;
First to the 5th common source line;
Memory cell, it is connected with described paratope line with described word line; And
Differential reading-out amplifying, it is connected with described paratope line,
Wherein said memory cell comprises first and second transistors,
The wherein said first and second transistorized gate electrodes are connected with described word line,
The drain electrode of wherein said the first transistor is connected with described first bit line,
The drain electrode of wherein said transistor seconds is connected with described second bit line, and
Any one of wherein said first and second transistorized each source electrode and described first to the 5th common source line or a plurality of the connection, perhaps be in floating, with store storage information in described memory cell.
10. according to the semiconductor device of claim 9,
Wherein during the read operation of described nonvolatile memory, the described first common source line changes first current potential into, and any of described second to the 5th common source line changes first current potential into.
11. according to the semiconductor device of claim 9,
Wherein said nonvolatile memory is in four data of a memory cell storage.
12. according to the semiconductor device of claim 9,
Wherein carry out the writing of data in the described memory cell by the M metal level wiring that is connected to form described first to the 5th common source line and (M-1) metal wiring layer that is connected with described first and second transistor drain.
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| JP2007153541 | 2007-06-11 | ||
| JP2008118506 | 2008-04-30 | ||
| JP2008118506A JP2009020990A (en) | 2007-06-11 | 2008-04-30 | Semiconductor integrated circuit device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578545A (en) * | 2012-07-31 | 2014-02-12 | 意法半导体股份有限公司 | Non-volatile memory device with clustered memory cells |
| CN106356095A (en) * | 2016-09-13 | 2017-01-25 | 中国科学院微电子研究所 | Read operation method and device for nonvolatile storage |
| CN107945823A (en) * | 2016-10-12 | 2018-04-20 | 中天鸿骏半导体（北京）有限公司 | Non-volatile memory device, its method for programming and its method for reading data |
-
2008
- 2008-06-10 CN CNA2008101101305A patent/CN101572264A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578545A (en) * | 2012-07-31 | 2014-02-12 | 意法半导体股份有限公司 | Non-volatile memory device with clustered memory cells |
| CN103578545B (en) * | 2012-07-31 | 2018-06-12 | 意法半导体股份有限公司 | The nonvolatile memory device of memory cell with cluster |
| CN106356095A (en) * | 2016-09-13 | 2017-01-25 | 中国科学院微电子研究所 | Read operation method and device for nonvolatile storage |
| CN106356095B (en) * | 2016-09-13 | 2019-11-15 | 中国科学院微电子研究所 | A kind of read operation method and device for nonvolatile memory |
| CN107945823A (en) * | 2016-10-12 | 2018-04-20 | 中天鸿骏半导体（北京）有限公司 | Non-volatile memory device, its method for programming and its method for reading data |
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