CN101572119A - Memory operating method - Google Patents

Abstract

The invention provides a memory operating method which comprises the following steps: forcing a main data line (MDQ) and a local data line (LDQ) of the memory to be in logic high levels when the memory is in a resetting mode; selecting a column selection line (CSL) and a word line of the memory to open a memory unit of the memory; and writing the logic high levels of the main data line and the local data line in the opened memory unit to reset the opened memory unit.

Description

Memory operating method

Technical field

The invention relates to a kind of method of operating of storer, and particularly be applicable to the method for the storage unit of resetting in the dynamic storage (memory cell).

Background technology

In the past, the employed storer of PC be Synchronous Dynamic Random Access Memory (synchronous dynamic random access memory, SDRAM).This SDRAM carries out the access of data at the rising edge of system clock pulse signal.

In addition, framework-binary channels Synchronous Dynamic Random Access Memory that existing development again makes new advances (Double DataRate SDRAM, abbreviation DDR SDRAM).This DDR SDRAM carries out the access of data at the rising edge and the falling edge of system clock pulse signal.Therefore, DDR SDRAM performance more is better than traditional SDRAM, so DDR SDRAM is more and more general.

In response to the demand of user for data transmission, DDR SDRAM is developed to present third generation DDR3 by the DDR1 of the first generation, the DDR2 of the second generation.One of characteristics of DDR3 are that it can be returned to original state with read-write, address signal etc. under (reset) pattern of replacement.

The invention provides a kind of method of operating of storer, it more can be reset to the stored contents of storage unit except control signal, address signal etc. being returned to the original state, to be convenient to follow-up sequencing (programming).

Summary of the invention

The present invention proposes a kind of memory operating method.When storer when carry out resetting action, the storage unit that selected needs are reset resets to required logic current potential with these storage unit, in order to program design.

One of example of the present invention proposes a kind of memory operating method.The method comprises the following steps: to make storer to be in reset mode; Allow the general data line and the area data line of storer be the logic current potential; The field selection wire and the word line of selection memory are with the storage unit of selection memory; According to the logic current potential of general data line and area data line, the selecteed storage unit of resetting.

Another example of the present invention proposes a kind of memory operating method, is applicable to storer.This memory operating method comprises: send a reset signal, with resetting memory, read-write and address signal in the storer are reset; Forcing the general data line and the area data line of storer is logic high potential; Open the field selection wire and the word line of storer, with a storage unit of selection memory; And the logic high potential of general data line and area data line write to selecteed storage unit, with the selecteed storage unit of resetting.

Comprehensive the above, when a storer during in Reset Status, except replacement read-write and address signal, also can be according to the needs of program design, the replacement particular storage is to specific current potential.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:

Fig. 1 is the storer synoptic diagram.

Fig. 2 is for being illustrated in the sequential chart of replacement storage unit in the dynamic storage according to one embodiment of the invention.

The main element symbol description:

101, MDQ, MDQ: general data line

102, CSL: field selection wire

110: memory cell

111: capacitor

112, BL, BL: bit line

113: sensing amplifier

114: the field selector switch

N1: storage unit current potential

120: memory array

121: the general data wiretap

122: general data wiretap control line

123, LDQ, LDQ: area data line

124, WL: word line

RESET: reset signal

Embodiment

When storer when carry out resetting action, except replacement read-write, address signal, the storage unit of also can resetting allows the program designer can comply with its storage unit of need resetting.

Fig. 1 is the synoptic diagram of storer.As shown in Figure 1, storer comprises at least: the general data line (masterdata line, MDQ) 101, the field selection wire (column selection line, CSL) 102 with memory array 120.Memory array 120 comprises at least: and general data wiretap 121, general data wiretap control line 122, area data line (Local data line, LDQ) 123, word line (word line, WL) 124 and memory cell 110.Memory cell 110 comprises storage unit 111, bit line 112, sensing amplifier (senseamplifier) 113, field selector switch 114 and word line switch 115.Wherein, storage unit 111 for example is a capacitor.

General data line 101 comprises the pair of data lines MDQ and the MDQ of current potential complementation.Area data line 123 comprises the pair of data lines LDQ and the LDQ of current potential complementation.Bit line 112 comprises a pair of bit line BL and the BL of current potential complementation.Node N1 represents the current potential of capacitor 111.That is, when node N1 is logic high potential, capacitor 111 stored logic " 1 " data; Otherwise, when node N1 is logic low potential, capacitor 111 stored logic " 0 " data.

General data line 101 is electrically connected to memory array 120.Particularly, general data line 101 sees through general data wiretap 121 and is electrically connected to area data line 123.The control end of this general data wiretap 121 is electrically connected at general data wiretap control line 122.When general data thread switching control 122 is logic current potential when high, general data wiretap 121 is a conducting state, makes the current potential of general data line 101 can write to area data line 123, and vice versa.

Area data line 123 sees through field selector switch 114 and is connected to bit line 112.The control end of field selector switch 114 is connected in field selection wire 102.When field selection wire 102 is logic current potential when high, field selector switch 114 is a conducting state, makes the current potential of area data line 123 can see through field selector switch 114 and reach bit line 112.

Sensing amplifier 113 is arranged between the bit line 112, and voltage differences small between bit line BL and the BL can be amplified by sensed amplifier 113, feasible wherein current potential that the bit line is a logic high, and another bit line is the current potential of logic low.

In embodiments of the invention, general data wiretap 121, field selector switch 114 and capacitor 111 can be transistors, and its grid is a control end.Above-mentioned storer for example is a third generation binary channels Synchronous Dynamic Random Access Memory.

Please be simultaneously with reference to Fig. 1 and Fig. 2.Fig. 2 is for being in the sequential chart under the reset mode according to the storer of the embodiment of the invention.When storer was in reset mode, reset signal RESET was a logic low, and general data wiretap control line 122 is that logic high is to open general data wiretap 121.Thus, general data line 101 can electrically conduct to area data line 123, that is the current potential of general data line 101 can write to area data line 123.In addition, under reset mode, the current potential of general data line 101 and area data line 123 may not one be decided to be logic high, can determine according to circumstances.

Then, make field selection wire 102 for logic high (just selecting this field selection wire 102) and open field selector switch 114.Thus, the current potential of area data line 123 can write to bit line 112.In addition, make word line 124 also for logic high (just selecting this word line 124) to open word line switch 115, make the current potential of bit line BL can write to capacitor 111.Thus, can military order storage unit current potential N1 and the current potential identical (just the current potential with general data line MDQ writes to capacitor 111) of general data line MDQ, finish replacement to capacitor 111.

Hold above-mentionedly,, when the replacement storage unit, if storage unit is reset to logic low potential, make then that general data line MDQ is that logic low gets final product when as can be known.

If desire replacement particular storage, allow relevant field selection wire CSL and the word line WL be that logic high is to open the also right replacement of corresponding storage unit.So visual need and determine which storage unit to be reset.What is more, also can select whole field selection wire CSL and word line WL, all be reset to make whole storage unit.

Hence one can see that, and storage unit current potential N1 can be reset to required logic current potential at standby mode, and be maintained to storer and leave till the standby mode.

As mentioned above, in the prior art, when storer is in reset mode, can only reset read-write, address signal etc.When storer was in reset mode, forcing general data line 101, area data line 123, bit line 114 was specific logic current potential with word line 124, specific or whole storage unit of can resetting but in embodiments of the present invention.Make the program designer more convenient in design.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims (13)

1. a memory operating method is applicable to a storer, and this memory operating method comprises:

Make this storer be in a reset mode;

Making a general data line and an area data line of this storer is a logic current potential;

Select a field selection wire and a word line of this storer, to select a storage unit of this storer; And

According to this logic current potential of this general data line and this area data line, selecteed this storage unit of resetting.

2. memory operating method as claimed in claim 1 is characterized in that, this step that makes this storer be in this reset mode comprises:

Make that a reset signal is a logic high potential.

3. memory operating method as claimed in claim 1 is characterized in that, this general data line comprises one first general data line and one second general data line, the current potential complementation of this first general data line and this second general data line.

4. memory operating method as claimed in claim 3 is characterized in that, makes this general data line of this storer and this area data line comprise for this step of this logic current potential:

Making this first general data line is logic high, and to make this second general data line be logic low.

5. memory operating method as claimed in claim 1 is characterized in that, this area data line comprises a first area data line and a second area data line, the current potential complementation of this first area data line and this second area data line.

6. memory operating method as claimed in claim 5 is characterized in that, makes this general data line of this storer and this area data line comprise for this step of this logic current potential:

Making this first area data line is logic high, and makes that this second area data line is a logic low.

7. memory operating method as claimed in claim 1 is characterized in that, according to this logic current potential of this general data line and this area data line, this step of selecteed this storage unit of resetting comprises:

This logic current potential of this general data line and this area data line is write to selecteed this storage unit, with this storage unit of resetting.

8. a memory operating method is applicable to a storer, and this memory operating method comprises:

Send a reset signal, with this storer of resetting, wherein a read-write and the address signal in this storer is reset;

Forcing a general data line and an area data line of this storer is logic high potential;

Open a field selection wire and a word line of this storer, to select a storage unit of this storer; And

This logic high potential of this general data line and this area data line is write to selecteed this storage unit, with selecteed this storage unit of resetting.

9. memory operating method as claimed in claim 8 is characterized in that, sends this reset signal and comprises with this step of this storer of resetting;

Make that this reset signal is a logic high potential.

10. memory operating method as claimed in claim 8 is characterized in that, this general data line comprises one first general data line and one second general data line, the current potential complementation of this first general data line and this second general data line.

11. memory operating method as claimed in claim 10 is characterized in that, forces this general data line of this storer and this step that this area data line is a logic high potential to comprise:

Making this first general data line is logic high, and to make this second general data line be logic low.

12. memory operating method as claimed in claim 8 is characterized in that, this area data line comprises a first area data line and a second area data line, the current potential complementation of this first area data line and this second area data line.

13. memory operating method as claimed in claim 12 is characterized in that, forces this general data line of this storer and this step that this area data line is a logic high potential to comprise:

Making this first area data line is logic high, and makes that this second area data line is a logic low.

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