CN101567394B - Vertical surrounding grid junction type field effect transistor, preparation method and applications thereof - Google Patents
Vertical surrounding grid junction type field effect transistor, preparation method and applications thereof Download PDFInfo
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- CN101567394B CN101567394B CN2009100522053A CN200910052205A CN101567394B CN 101567394 B CN101567394 B CN 101567394B CN 2009100522053 A CN2009100522053 A CN 2009100522053A CN 200910052205 A CN200910052205 A CN 200910052205A CN 101567394 B CN101567394 B CN 101567394B
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Abstract
The invention relates to a vertical surrounding grid junction type field effect transistor, a preparation method and applications thereof. The field effect transistor comprises a source area, a drain area, a surrounding grid, a sensitive grid, a channel and a source-drain area press welding block or metal lead; wherein the source area and the drain area are connected through the channel; the sensitive grid and the surrounding grid are connected; the surrounding grid surrounds the upper surface, the left surface and the right surface of the channel which is vertical; the channel and the surrounding grid form a Pn junction; the source area and the drain area are electrically connected with an external circuit through the press welding block or the metal lead. The field effect transistor and a sensitive structure are manufactured on the top layer silicon of an SOI silicon chip and are simultaneously manufactured by adopting a micro-mechanical processing method. The displacement detection on the sensitive structure is realized through capacitance coupling.
Description
Technical field
The present invention relates to a kind of vertical surrounding grid junction type field effect transistor, manufacture method and application that is used for the transducer displacement detecting, belong to sensor field.
Background technology
Capacitance detecting be micro electronmechanical integrated system (Micro-Electro-Mechanical-System, MEMS) in displacement detecting technology (M.Bao, Micro Mechanical Transducers, publishing house: ELSEVIER, 2000.) commonly used.Multiple micro-machine acceleration transducer, micromechanical gyro have all adopted capacitance determining method to realize the accurate measurement to the sensitive structure displacement.Reduce along with the integrated level of micro electronmechanical integrated system increases with volume, the capacitance of sensitization capacitance reduces thereupon.The sensitization capacitance value of the acceleration transducer that surface micro and SOI (Silicon onInsulator, silicon-on-insulator) micro mechanical technology is made is mostly less than 1pF, and capacitance change is mostly in the magnitude of fF/g.Because the general long-range sensitization capacitance value of parasitic capacitance value that encapsulation process is introduced causes the interface circuit manufacture difficulty of capacitance detecting to increase.In order to realize that high-precision capacitance detecting need realize monolithic integrated (N.Yazdi, F.Ayazi, the K.Najafi of sensitive structure and interface circuit, Micromachined inertial senosrs, Proceedings of the IEEE, Vol.86, No.8,1998, pp.1640-1659.).For example the acceleration transducer of Anglog Device company and micromechanical gyro have realized that all monolithic is integrated.Because micromachined and analog integrated circuit require differently to technology, the single slice integration technique difficulty of sensitive structure and interface circuit is big.In addition, the lithographic line width of integrated circuit technique reduces by the mole law, and device upgrade speed is fast.And it is not obvious to the effect that improves the micro mechanical device performance to reduce live width, but can significantly increase the risk and the cost of process debugging.Both cause single chip integrated cost significantly to increase to device upgrade speed difference, cause technical threshold height, the operation cost of single slice integration technique big.
Vibration dual-gate MOS structure is by integrated with a metal-oxide-semiconductor and sensitive structure, with sensitization capacitance and the coupling of mos gate electrode capacitance, realize capacitance-voltage conversion (1. J.A.Plaza, M.A.Benitez, J.Esteve, E.Lora-Tamayo, New FET accelerometer based on surface micromachining.Sensors and Actuators, A61,1997, pp.342-345; 2. A.Weinert, G.I.Andersson, High resolution resonant double gate transistor for oscillating structures.Sensorsand Actorators, A90,2001, pp.20-30.).This technology is equivalent to the first order of interface circuit and sensitive structure are realized that monolithic is integrated, can significantly reduce the influence of parasitic capacitance to measuring, and realizes the accurate measurement that small capacitance is changed.Realize that single metal-oxide-semiconductor is much lower with the integrated difficulty than the integrated whole interface circuit monolithic of monolithic of sensitive structure, this technology can realize device cheaply.Vibration dual-gate MOS structure can realize well integrated with the surface micromachined technology.The shortcoming of vibration dual-gate MOS pipe is that mainly the mos gate oxide layer generally can't tolerate the acid corrosion technology that is used to discharge sensitive structure, must adopt special process that the gate oxide of MOS structure is protected, thereby increase process complexity.
Vibration double grid technotron can be realized and vibrate function (K.M.Brunson like the dual-gate MOS tubing, D.J.Hamilton, R.J.T.Bunyan, M.E.McNie, Method of fabricatingmicro-electromechanical systems, US Patent, No.US7205173B2, Apr.17,2007).Because technotron does not have gate oxide, do not need grid is done special protection, it realizes that difficulty is lower than vibration dual-gate MOS pipe.
Micromachining technology based on the soi wafer top layer silicon develops rapidly in recent years, the top layer of soi wafer is a monocrystalline silicon, and top layer silicon thickness can be obviously greater than the structure sheaf of surface micro, and device mechanics of making and electrology characteristic all significantly are better than the surface micro device.Be planar structure owing to vibrate the dual-gate MOS pipe with vibration double grid technotron, generally the vertical stratification that needs making and grid to be connected could be realized the sensitivity to the sensitive structure transverse vibration, thereby significantly increases process complexity.
So the present invention intends proposing a kind of structure of vertical surrounding grid junction type field effect pipe.Though described field effect transistor adopts vibration double grid principle equally,, be expected to greatly simplify technology, thereby reduce production costs owing to adopted vertical grid and channel structure to make this vertical stratification be convenient to realize the integrated of sensitive structure on the top layer silicon with SOI.
Summary of the invention
In sum, the object of the present invention is to provide a kind of vertical surrounding grid junction type field effect transistor, manufacture method and application.This field effect transistor adopts vibration double grid principle, promptly utilizes sensitive structure as sensitive grid, by the displacement measurement of vertical surrounding grid junction type field effect pipe realization to sensitive structure.Owing to adopted vertical grid and channel structure, be convenient to realize with the SOI top layer silicon on sensitive structure integrated, can greatly simplify technology, thereby reduce production costs.
Figure 1 shows that the basic structure of vertical surrounding grid junction type field effect pipe.Described vertical surrounding grid junction type field effect transistor is produced on SOI (Silicon on Insulator, silicon-on-insulator) on the top layer silicon of silicon chip, structure comprises source region, drain region, forms around grid, sensitive grid, raceway groove and source-drain area press welding block/metal lead wire.The thickness in source region and drain region is equal to the thickness of soi wafer top layer silicon.The source region is connected by raceway groove with the drain region.Source region, drain region are identical with the doping type of raceway groove.If raceway groove mixes for the n type then is called n ditch technotron, if for the doping of p type then be called p ditch technotron.Sensitive grid with link to each other around grid, doping type is identical and opposite with the doping type of raceway groove.Surround the going up of raceway groove, left and right three around grid.For n ditch technotron, sensitive grid mixes be the p type around grid.For p ditch technotron, sensitive grid mixes be the n type around grid.Sensitive grid with generally be higher than one of channel doping concentration around the doping content of grid more than the order of magnitude.Raceway groove with form a pn knot around grid.Because around the doping content height of grid, the space charge region of pn knot mainly is positioned at raceway groove, as shown in Figure 2.During transistor work, the pn knot is partially anti-.The equivalent electric circuit of pn knot is that an ideal diode is in parallel with the pn junction capacitance.The pn junction capacitance is designated as C
GsAccording to Principles of Transistors, C
GsValue determine by the space charge sector width.
ε in the formula
sBe silicon relative dielectric constant, ε
0Be permittivity of vacuum, A is the pn junction area, and h is the space charge sector width.
Thereby general technotron is realized transistor characteristic by the thickness of grid modulation raceway groove, and promptly raceway groove is a level.Different with general technotron, the transistorized raceway groove of vertical surrounding grid junction type is vertical, and promptly channel width is much smaller than thickness, and transistor characteristic is mainly by the decision of modulation channel width.The thickness that the thickness of raceway groove equals the SOI top layer silicon deducts the thickness of top around grid and space charge region.Though the thickness of raceway groove also can be subjected to the modulation of grid voltage, because the thickness of raceway groove is much larger than width, mudulation effect is not obvious.Can be similar to and think that channel thickness is constant.Grid is to realize by the width of voltage control space charge region between grid and raceway groove to the modulation of channel width.
The source of vertical surrounding grid junction type field effect pipe, drain region realize that with other circuit electricity is connected by press welding block or metal lead wire.Because this field-effect transistor is used for the displacement detecting of sensitive structure, is used for capacitance detecting or rather, sensitive grid with around there not being metal lead wire between the grid, but by the displacement detecting of capacitive coupling realization to sensitive structure.(seeing embodiment for details)
The capacitive coupling of vertical surrounding grid junction type field effect transistor and sensitive structure as shown in Figure 3.Sensitive structure is two-end fixed beam-mass block structure among the figure.But the measurable sensitive structure of vertical surrounding gate field-effect transistor is not limited to two-end fixed beam-mass block structure, and can be the structure of any lateral movement.Vertical surrounding grid junction type field effect transistor places the side of sensitive structure.The sensitive grid of vertical surrounding grid junction type field effect transistor and sensitive structure constitute a plane-parallel capacitor, are designated as C
s, C
sWith the pn junction capacitance be series relationship, equivalent electric circuit is as shown in Figure 4.Fig. 4 (a) and (b) be respectively the equivalent electric circuit of n ditch and p ditch technotron, V among the figure
bAnd V
ChBe respectively the voltage of sensitive structure and raceway groove.Voltage on the pn junction capacitance is exactly the grid voltage of technotron, can get grid voltage by Fig. 4 to be
When sensitive structure has lateral displacement, C
sCan change C
GsWith V
GsAlso corresponding change.According to Principles of Transistors, the change of technotron grid voltage can cause the change of mutual conductance.Can record capacitor C by the variation of measuring mutual conductance
sVariation.
According to Principles of Transistors, the breadth length ratio that improves traditional technotron can improve device performance.The breadth length ratio of tradition technotron is equivalent to the ratio of the channel thickness and the length of vertical surrounding gate field-effect transistor.Because the channel thickness of vertical surrounding gate field-effect transistor is not an arbitrary value by the top layer silicon thickness decision of soi wafer.And channel length is subjected to the restriction of technology.Can improve the ratio of channel thickness and length by mode with a plurality of raceway groove parallel connections.When a plurality of raceway grooves were in parallel, the total length of raceway groove was constant, equal the length of single raceway groove, and the thickness of raceway groove equals the stack of a plurality of channel thickness.Figure 5 shows that the vertical surrounding gate field-effect transistor schematic diagram of 3 raceway groove parallel connections, this moment, the ratio of channel thickness and length was 3 times of single channel structure.
Vertical surrounding grid junction type field effect transistor provided by the invention and sensitive structure all are produced on the top layer silicon of soi wafer, adopt micromachining technology to make simultaneously.Concrete manufacture method sees execution mode for details.
The major advantage of vertical surrounding grid junction type field effect pipe provided by the invention is:
(1) the vertical surrounding grid junction type field effect pipe can be used as the interface circuit first order of micro electronmechanical sensitive structure capacitive displacement detection method.By vertical surrounding grid junction type field effect pipe and micro electronmechanical sensitive structure are realized that monolithic is integrated, can avoid encapsulating the influence of the parasitic capacitance of introducing.
(2) than existing vibration dual-gate MOS pipe, the vertical surrounding grid junction type field effect pipe is not for there being gate oxide, and the sacrifice layer release tech compatibility in its manufacture craft and the micromachined is good, and technology is simple.
(3) than existing vibration double grid technotron, the vertical surrounding grid junction type field effect pipe has adopted vertical gate structure, is convenient to detect the sensitive structure of motion in the silicon chip plane.
(4) vertical surrounding grid junction type field effect pipe and sensitive structure adopt and to make moulding simultaneously with sampling technology, and gate diffusions has the autoregistration characteristic, and technology is simple, and is good with the micromechanical process compatibility.
Description of drawings
Fig. 1 a is a vertical surrounding grid junction type field effect transistor vertical view provided by the invention, and Fig. 1 b is the profile of Fig. 1 a along B-B ' section, and Fig. 1 c is the profile along A-A ' section.The structure of vertical surrounding grid junction type field effect pipe comprises source region 1, drain region 2, around grid 3, sensitive grid 4, press welding block/lead-in wire 5, raceway groove 6.Vertical surrounding grid junction type field effect transistor is produced on the substrate 7, and realizes isolating by buried regions oxide layer 8.
Fig. 2 is a raceway groove and profile around grid.Raceway groove 6 an and space charge region 9 is arranged around 3 of grid.
Figure 3 shows that the schematic diagram of vertical surrounding grid junction type field effect pipe and sensitive structure coupling.Fig. 3 a is a vertical view, and Fig. 3 b is the profile along A-A ' section.Illustrated sensitive structure is two-end fixed beam-mass block structure, and it is made up of beam 10 and mass 11.
Fig. 4 is sensitive structure, sensitive grid, around the equivalent circuit diagram of grid and channel part.Fig. 4 a is a n ditch vertical surrounding grid junction type field effect pipe, and Fig. 4 b is a p ditch vertical surrounding grid junction type field effect pipe.
Fig. 5 is the vertical surrounding grid junction type field effect pipe schematic diagram of triple channel parallel connection.Fig. 5 a is a vertical view, and Fig. 5 b is the profile along A-A ' section.
Fig. 6 is for making around the structural representation before the grid.Fig. 6 a is a vertical view, and Fig. 6 b is the profile of A-A ' section.
Fig. 7 is the structural representation that diffuses to form around behind the grid.Fig. 7 a is a vertical view, and Fig. 7 b is the profile of A-A ' section.
Fig. 8 forms schematic diagram after source, leakage, the grid structure for dry etching.Fig. 8 a is a vertical view, and Fig. 8 b is the profile of A-A ' section.
Fig. 9 is the structural representation of making.Fig. 9 a is a vertical view, and Fig. 9 b is the profile of A-A ' section.
Figure 10 is the application of vertical surrounding grid junction type field effect pipe in cantilever beam mass block structure acceleration transducer displacement detecting.Figure 10 a is a vertical view, and Figure 10 b is the profile of A-A ' section.
Embodiment
Further specify substantive distinguishing features of the present invention and obvious improvement below in conjunction with accompanying drawing, but the present invention only is confined to embodiment by no means.
The making step of vertical surrounding grid junction type field effect transistor provided by the invention is:
(1) for n ditch field-effect transistor, adopting top layer silicon is the soi wafer of n type.Hot growing silicon oxide protective layer on top layer silicon.Form sensitive structure, sensitive grid by photoetching and dry etch process etching, and around the doping window of grid, and remove sensitive structure upper surface and sensitive grid, around the oxide layer of grid upper surface.As shown in Figure 6.
(2) utilize the diffusion technology of integrated circuit, at sensitive structure, sensitive grid and around the upper surface and the wall doping of grid.For n ditch field-effect transistor, doping type is the p type.For p ditch field-effect transistor, doping type is the n type.Doping content reaches 10
19/ cm
3More than, to satisfy the requirement of ohmic contact.As shown in Figure 7.
(3) photoetching once more, dry etching form neededly around the grid structure, and realize the insulation of vertical surrounding grid junction type field effect pipe and sensitive structure by deep trouth.As shown in Figure 8.
(4) make metal electrode.The erosion removal sensitive structure reaches the buried regions oxide layer under the raceway groove down, forms final structure.As shown in Figure 9.
Prepared vertical surrounding grid junction type field effect transistor comprises source region, drain region, forms around grid, sensitive grid, raceway groove and source-drain area press welding block or metal lead wire, wherein the source region is connected by raceway groove with the drain region, sensitive grid with link to each other around grid, surround the going up of raceway groove, left and right three around grid, raceway groove is vertical; Raceway groove with form a Pn knot around grid; Source, drain region realize that with external circuit electricity is connected by press welding block or metal lead wire.Owing to be higher than one of the doping content of raceway groove more than the order of magnitude, so the space charge region mainly is positioned at raceway groove around the doping content of grid.
The vertical surrounding grid junction type field effect transistor that provides is used for the displacement detecting of sensitive structure:
Figure 10 shows that the instantiation that the vertical surrounding grid junction type field effect pipe is applied to cantilever beam-mass block structure acceleration transducer.Utilize the vertical surrounding grid junction type field effect pipe to realize of the detection of cantilever beam-mass block structure among Figure 10 at silicon chip plane intrinsic displacement.The vertical surrounding grid junction type field effect pipe can significantly reduce the influence of parasitic capacitance to displacement detecting.The Differential Detection of a vertical surrounding grid junction type field effect pipe realization to cantilever beam-mass block structure displacement made in employing respectively on cantilever beam-mass block structure both sides.Cantilever beam-mass block structure is as the public grid of two vertical surrounding grid junction type field effect pipes.Adopt the mode of 5 raceway groove parallel connections to obtain bigger channel thickness and length ratio, reduce the raceway groove dead resistance.
Claims (11)
1. vertical surrounding grid junction type field effect transistor, it is characterized in that described field-effect transistor comprise source region, drain region, around grid, sensitive grid, raceway groove and source-drain area press welding block or metal lead wire, wherein, the source region is connected by raceway groove with the drain region, sensitive grid with link to each other around grid, and described sensitive grid and be to form by photoetching and dry etch process and diffusing, doping technology around grid surrounds the going up of raceway groove, left and right three around grid, and raceway groove is vertical; Raceway groove with form a pn knot around grid; Source, drain region realize that with external circuit electricity is connected by press welding block or metal lead wire; Sensitive grid and sensitive structure constitute a plane-parallel capacitor, and described sensitive structure is the structure of two-end fixed beam-mass block structure or any lateral movement.
2. by the described vertical surrounding grid junction type field effect transistor of claim 1, it is characterized in that described field-effect transistor is produced on the top layer silicon of SOI, realize isolating by the buried regions oxide layer.
3. by the described vertical surrounding grid junction type field effect transistor of claim 2, the thickness that the thickness that it is characterized in that raceway groove equals the top layer silicon of SOI deducts the thickness around gate part and space charge region that is positioned at above the described raceway groove; When a plurality of raceway grooves were in parallel, the total length of raceway groove was constant, and the thickness of raceway groove equals the stack of a plurality of channel thickness.
4. by the described vertical surrounding grid junction type field effect transistor of claim 2, it is characterized in that the thickness in source region and drain region equals the thickness of the top layer silicon of SOI.
5. by claim 1 or 4 described vertical surrounding grid junction type field effect transistors, it is characterized in that source region, drain region are identical with the doping type of raceway groove; Sensitive grid is identical and opposite with the doping type of raceway groove with doping type around grid.
6. by the described vertical surrounding grid junction type field effect transistor of claim 1, it is characterized in that sensitive grid and be higher than one of channel doping concentration more than the order of magnitude around the doping content of grid.
7. by the described vertical surrounding grid junction type field effect transistor of claim 5, it is characterized in that sensitive grid and be higher than one of channel doping concentration more than the order of magnitude around the doping content of grid.
8. make the method for vertical surrounding grid junction type field effect transistor as claimed in claim 1, it is characterized in that described field-effect transistor and sensitive structure are produced on the top layer silicon of SOI, adopt micro-machining to make simultaneously, concrete steps are:
(1) for n ditch field-effect transistor, adopting top layer silicon is the SOI of n type; Hot growing silicon oxide protective layer on top layer silicon forms sensitive structure, sensitive grid by photoetching and dry etch process etching, and around the doping window of grid, and remove sensitive structure upper surface and sensitive grid, around the silica protective layer of grid upper surface;
(2) utilize the diffusion technology of integrated circuit, at sensitive structure, sensitive grid and around the upper surface and the wall doping of grid; For n ditch field-effect transistor, doping type is the p type;
(3) photoetching once more, dry etching form neededly around the grid structure, and realize the insulation of vertical surrounding grid junction type field effect transistor and sensitive structure by deep trouth;
(4) make metal electrode, below the erosion removal sensitive structure and the buried regions oxide layer below the raceway groove, form final structure.
9. by the described manufacture method of claim 8, it is characterized in that step (2) doping content reaches 10
19/ cm
3More than, to satisfy the requirement of ohmic contact.
10. by the application of claim 1,2 or 4 described vertical surrounding grid junction type field effect transistors, it is characterized in that being used for sensitive grid with around there not being metal lead wire between the grid, by the displacement detecting of capacitive coupling realization to sensitive structure.
11. by the application of the described vertical surrounding grid junction type field effect transistor of claim 3, it is characterized in that being used for sensitive grid with around there not being metal lead wire between the grid, by the displacement detecting of capacitive coupling realization to sensitive structure.
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| CN102881687A (en) * | 2011-07-13 | 2013-01-16 | 广东中显科技有限公司 | Topological structure of PMOS polysilicon TFT register circuit |
| WO2013007024A1 (en) * | 2011-07-13 | 2013-01-17 | 广东中显科技有限公司 | Pmos poly-si tft register circuit based on metal-induced lateral crystallization technique |
| US9663346B1 (en) * | 2016-02-17 | 2017-05-30 | Globalfoundries Inc. | MEMs-based resonant FinFET |
| CN108267262B (en) * | 2016-12-30 | 2024-04-09 | 中国空气动力研究与发展中心超高速空气动力研究所 | Temperature self-compensating semiconductor piezoresistance strain gauge |
| CN115901862A (en) * | 2022-11-04 | 2023-04-04 | 湖南元芯传感科技有限责任公司 | Extension gate type field effect gas sensor and preparation method thereof |
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