CN101557205B - Mixed-mode AGC loop - Google Patents

Mixed-mode AGC loop Download PDF

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CN101557205B
CN101557205B CN 200910302631 CN200910302631A CN101557205B CN 101557205 B CN101557205 B CN 101557205B CN 200910302631 CN200910302631 CN 200910302631 CN 200910302631 A CN200910302631 A CN 200910302631A CN 101557205 B CN101557205 B CN 101557205B
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signal
input
output
gain
comparator
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CN 200910302631
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CN101557205A (en )
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杜占坤
郭桂良
阎跃鹏
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中国科学院微电子研究所
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Abstract

The invention discloses a mixed-mode AGC loop and belongs to the field of electronic technology. The AGC loop comprises a VGA module, a peak detector, a variable speed integrator, a comparator, a counter, a threshold controller and a gain controller; the VGA module is connected with the peak detector, the variable speed integrator and the gain controller; the peak detector is connected with the VGA module and the variable speed integrator; a threshold controller is connected with the variable speed integrator; the variable speed integrator is connected with the peak detector, the threshold controller, the VGA module and the comparator; the comparator is connected with the counter and the variable speed integrator; the counter is connected with the comparator and the gain controller; and the gain controller is connected with the counter and the VGA module. By implementing analog and digital dual-mode control to the differential intermediate frequency signal gain, the invention leads the output signal amplitude of the VGA module not to be changed along with the change of the input signal thereof; and the circuit structure of the AGC loop is simple and flexible.

Description

一种混合模式AGC环路 A hybrid AGC loop mode

技术领域 FIELD

[0001] 本发明涉及电子技术领域,特别涉及一种混合模式AGC环路。 [0001] The present invention relates to electronic technologies, and in particular relates to a hybrid mode of AGC loop. 背景技术 Background technique

[0002] 自动增益控制技术(AGC,Automatic Gain Control)广泛地应用于各类电子系统中,用于增大电子系统的动态范围。 [0002] The AGC techniques (AGC, Automatic Gain Control) is widely used in various electronic systems for increasing the dynamic range of the electronic system. 一个AGC主要由可变增益放大器(VGA,VariableGain Amplifier)和检测控制电路两部分组成;检测控制电路用于检测VGA输出信号的幅度,并通过一定的算法产生控制信号来调整VGA的输出增益,使VGA输出信号的幅度不随其输入而变化。 A variable gain AGC amplifier is mainly composed of (VGA, VariableGain Amplifier) ​​and a detection control circuit of two parts; detection control circuit for detecting the amplitude of the VGA output signal and a control signal is generated through a certain algorithm to adjust the output gain of the VGA, so VGA output amplitude varies with the input signal does not. 现有技术中,检测控制电路有两种实现方法:其一,是采用模拟方法检测VGA输出信号的峰值,并对峰值信号进行低通滤波及放大后,反馈回VGA,进而控制VGA输出信号的增益;其二,是采用数字方法检测VGA输出信号的峰值,并对峰值信号进行一定处理后,产生数字控制量,来调整VGA的输出信号增益。 In the prior art, the detection control circuit has two methods: One is a method using an analog VGA output signal to detect a peak, and the low-pass filtered and amplified peak signal, fed back to the VGA, and thus the control of the VGA output signal gain; Second, peak detection method is a digital VGA output signal, and after a certain peak signal processing, generates a digital control quantity to adjust the gain of the VGA output signal.

[0003] 但是,上述两种检测控制电路的实现方法都存在缺陷;首先,模拟检测控制方法难以实现较宽增益范围的控制,并且AGC速度较慢;其次,数字检测方法虽然可以获得较宽增益范围的控制,但是如果电子系统没有A/D转换器,那么AGC是无法实现的。 [0003] However, to achieve the above-described two detection methods are flawed control circuit; First, the simulation method for detection control is difficult to achieve a wide gain control range and AGC slow speed; Secondly, although the digital detection method can obtain a wide gain control range, but if the electronic system is not a / D converter, then the AGC can not be achieved.

发明内容 SUMMARY

[0004] 为了解决模拟检测控制方法无法实现较宽增益范围的控制,AGC速度慢,以及数字检测方法有时无法实现AGC等问题,本发明提供了一种混合模式AGC环路,所述AGC环路包括VGA模块、峰值检测器、速度可变积分器、比较器、计数器、阈值控制器和增益控制器; [0004] In order to solve the analog detection control methods can not achieve a wide gain control range, slow AGC, and a digital AGC detection method may not be achieved and other problems, the present invention provides a hybrid mode of AGC loop, the AGC loop VGA module includes a peak detector, variable speed integrator, a comparator, a counter, and the threshold controller gain controller;

[0005] 所述VGA模块,与所述峰值检测器、速度可变积分器和增益控制器相连,用于接收外部输入信号,并根据所述速度可变积分器输出控制信号的大小对输入信号进行放大,将放大后的输入信号发送给所述峰值检测器,以及接收所述增益控制器输出的控制信号; [0005] The VGA module, and said peak detector, a variable speed and a gain controller coupled to the integrator, for receiving an external input signal, and a variable integrator output control signal according to the magnitude of the input speed signal amplifies the input signal amplified is sent to the peak detector, and the gain controller receives the control signal output;

[0006] 所述峰值检测器,与所述VGA模块和速度可变积分器相连,用于检测所述VGA模块发送的输出信号的峰值大小,并将峰值发送给所述速度可变积分器; [0006] The peak detector connected to said variable integrator module VGA and speed for peak magnitude of the detection output signal transmitted from the VGA module, and transmitted to the peak value of the variable speed integrator;

[0007] 所述阈值控制器,与所述速度可变积分器相连,用于在外部控制信号的控制下,选择输出不同的阈值; [0007] The threshold value controller, the integrator is connected to the variable speed, the control for the next external control signal, selects and outputs different threshold values;

[0008] 所述速度可变积分器,与所述峰值检测器、阈值控制器、VGA模块和比较器相连,用于比较所述峰值检测器输出的峰值与所述阈值控制器输出的阈值之间的大小,如果所述峰值检测器输出的峰值大于所述阈值控制器输出的阈值,则根据所述阈值控制器的外部控制信号的选择模式进行负积分,否则进行正积分,并输出控制信号; [0008] The variable speed integrator, coupled to said peak detector, a threshold controller, VGA and a comparator module, a threshold value of the peak threshold value output from the peak detector output controller size between the peak if the peak detector output is greater than the threshold value output from the threshold value controller, the negative-integration mode selected in accordance with an external control signal the threshold value controller, or for positive integration, and outputs a control signal ;

[0009] 所述比较器,与所述计数器和速度可变积分器相连,用于比较所述速度可变积分器输出的控制信号与外部比较信号的大小,并根据比较结果发送控制信号给所述计数器; [0009] The comparator connected to the counter and the variable speed integrator, for comparing said speed signal with a magnitude of the external control variable the comparison signal output from the integrator, and sends a control signal according to the comparison result said counter;

[0010] 所述计数器,与所述比较器和增益控制器相连,用于根据所述比较器发送的控制信号和外部时钟信号进行计数,并将计数结果发送给所述增益控制器; [0010] The counter, coupled to the comparator and a gain controller, a control signal for counting an external clock signal and transmission of the comparator, and the counting result to the gain controller;

[0011] 所述增益控制器,与所述计数器和VGA模块相连,用于根据所述计数器发送的计数结果,向所述VGA模块发送表示增加增益或降低增益的控制信号。 [0011] The gain controller, coupled to the counter and the VGA module, based on the count result of the counter for transmission to the VGA module transmits a control signal to increase or decrease the gain of the gain.

[0012] 所述VGA模块包括信号输入端,信号输出端和控制信号输入端;所述信号输入端输入差分中频信号,所述控制信号输入端输入的控制信号为模拟增益控制信号或数字增益控制信号。 [0012] The VGA module comprises a signal input terminal, a signal output terminal and a control signal input terminal; signal input terminal of the differential IF signal, said control signal input terminal of the gain control signal into an analog or digital gain control signal.

[0013] 所述VGA模块由多个数字放大子单元和一个模拟放大子单元组成;一个数字放大子单元的输入端与所述VGA模块的信号输入端相连;每个数字放大子单元彼此相互连接, 并且最后一个数字放大子单元的输出端与所述模拟放大子单元的输入端相连;所述模拟放大子单元的输出端与所述VGA模块的信号输出端相连。 [0013] The VGA module by a plurality of sub-unit and a digital amplifier amplifying the analog subunits; is connected to a digital signal input terminal of the amplifying sub-unit input and the VGA module; each subunit digital amplifier connected to each other and the last output terminal digital amplification unit amplifying the analog input terminal is connected subunit; signal output terminal connected to an output terminal of said analog amplifier VGA sub-unit and the module.

[0014] 所述峰值检测器包括信号输入端和信号输出端;所述信号输入端与所述VGA模块的信号输出端相连;所述峰值检测器通过所述信号输出端将峰值信息发送给所述速度可变积分器。 [0014] The peak detector includes a signal input and a signal output terminal; coupled to said signal input terminal and the signal output of the VGA module; the peak output of the peak detector of the information signal to the said variable speed integrator.

[0015] 所述阈值控制器包括控制信号输入端和输出端;所述控制信号输入端与外部控制信号相连,所述输出端输出不同的阈值。 [0015] The threshold controller includes a control signal input terminal and an output terminal; wherein the control signal input terminal is connected to the external control signal, the output terminal different thresholds.

[0016] 所述速度可变积分器包括控制信号输入端、阈值输入端、峰值输入端和积分输出端;所述控制信号输入端用于选择不同的积分常数;所述峰值输入端输入的信号和阈值输入端输入的信号的大小,用于确定积分的方向。 [0016] The integrator comprises a variable speed control signal input, a threshold input terminal, an input terminal and a peak integral output; the control signal input terminal for selecting a different integration constants; a signal input end of said input peak the magnitude of the signal input terminal and a threshold for determining the direction of integration.

[0017] 所述比较器包括第一比较器和第二比较器;所述第一比较器和第二比较器分别包括两个输入端和一个输出端;一个输入端接外部输入信号,另一个输入端与所述速度可变积分器的积分输出端相连;所述第一比较器的输出端用于发送递增计数使能控制信号给所述计数器;所述第二比较器的输出端用于发送递减计数使能控制信号给所述计数器。 [0017] The comparator comprises a first comparator and a second comparator; the first comparator and the second comparator includes two input terminals and an output terminal; a terminating external input signal, the other input terminal of the variable integrator integrating an output terminal coupled to said speed; the first comparator output terminal for transmitting the count-enable control signal to said counter; an output terminal of the second comparator for down counter enable sending control signals to said counter.

[0018] 所述计数器包括第一计数器和第二计数器;所述第一计数器和第二计数器分别包括输入端、时钟输入端和信号输出端;所述第一计数器的输入端与所述第一比较器的输出端相连;所述第二计数器的输入端与所述第二比较器的输出端相连;所述时钟输入端接外部时钟信号;所述第一计数器根据其输入端的输入信号的高低电平,来确定是否递增计数, 并把计数结果发送给所述增益控制器;所述第二计数器根据其输入端的输入信号的高低电平,来确定是否递减计数,并把计数结果发送给所述增益控制器。 [0018] The counter comprises a first and second counters; the first and second counters, respectively, includes an input terminal, a clock signal input terminal and an output terminal; input of the first counter with the first output of the comparator is connected; an input terminal connected to the output of said second counter and the second comparator; said clock input terminal of the external clock signal; level of an input signal at its input according to the first counter level, to determine whether to count up, and sends the count result to the gain controller; the second counter according to the high level input signal at its input, to determine whether the count down, and sends the count result to said gain controller.

[0019] 所述增益控制器包括输入端和输出端;所述增益控制器根据所述输入端的输入大小,进行逻辑运算,向所述VGA模块发送表示增加增益或降低增益的控制信号。 [0019] The gain controller includes an input and an output; said input terminal of said gain controller according to the size of an input, conducts logic operation to the VGA module transmits a control signal to increase or decrease the gain of the gain.

[0020] 所述表示增加增益或降低增益的控制信号为N位增益控制字,其中N为自然数。 [0020] represents the gain to increase or decrease the gain control signal for the N-bit gain control word, where N is a natural number.

[0021] 有益效果:本发明通过VGA模块、速度可变积分器和增益控制器,对差分中频信号增益进行模拟和数字双重模式控制,使得VGA模块的输出信号幅度不随其输入信号变化而变化;本发明提供的AGC环路的电路结构简单且灵活,AGC工作速度可以进行选择,从而可以满足多种系统的要求。 [0021] Advantageous Effects: The present invention is a VGA module variable, and the speed integrator gain controller, the gain of the differential IF signal dual mode analog and digital control, so that the amplitude of the output signal of the VGA module does not change with a change of its input signal changes; AGC loop circuit configuration of the present invention to provide a simple and flexible, AGC operating speed may be selected to meet the requirements of various systems.

附图说明 BRIEF DESCRIPTION

[0022] 图1是本发明实施例提供的AGC环路电路原理结构示意图; [0022] FIG. 1 is a schematic circuit structure diagram of an AGC loop according to an embodiment of the present invention;

[0023] 图2是本发明实施例VGA模块的内部电路原理结构示意图; [0023] FIG. 2 is a schematic circuit diagram illustrating an internal configuration example of the VGA module embodiment of the present invention;

[0024] 图3是本发明实施例速度可变积分器的电路原理结构示意图; [0024] FIG. 3 is a schematic circuit diagram of the variable integrator configuration example embodiment of the present invention, the speed;

[0025] 图4是本发明实施例混合模式AGC环路的计算机仿真结果曲线图。 [0025] FIG. 4 is a graph illustrating computer simulation results of the AGC loop mixed-mode embodiment of the present invention. 具体实施方式 Detailed ways

[0026] 为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明实施方式作进一步地详细描述。 [0026] To make the objectives, technical solutions, and advantages of the present invention will become apparent in conjunction with the accompanying drawings of the following embodiments of the present invention will be described in further detail.

[0027] 参见图1,本发明实施例提供了一种混合模式AGC环路,包括VGA模块100、峰值检测器200、速度可变积分器400、第一比较器500、第二比较器600、第一计数器700、第二计数器800、阈值控制器300和增益控制器900 ; [0027] Referring to Figure 1, an embodiment of the present invention provides a hybrid mode of AGC loop, including VGA module 100, a peak detector 200, a variable speed integrator 400, a first comparator 500, second comparator 600, a first counter 700, second counter 800, a threshold value controller 300 and the gain controller 900;

[0028] VGA模块100,与峰值检测器200、速度可变积分器400和增益控制器900相连,用于接收外部输入信号,并根据速度可变积分器400输出控制信号(Vc)的大小对输入信号进行放大,将放大后的输入信号发送给峰值检测器200,以及接收增益控制器900输出的控制 [0028] VGA module 100, the peak detector 200, a variable speed integrator 400 and the gain controller 900 is connected to receive an external input signal, and a variable magnitude of the integrator 400 outputs a control signal (Vc) based on the speed a control input signal is amplified, the amplified input signal to a peak detector 200, and a gain controller 900 receiving output

信号; signal;

[0029] 峰值检测器200,与VGA模块100和速度可变积分器400相连,用于检测VGA模块100发送的输出信号的峰值大小,并将峰值发送给速度可变积分器400 ; [0029] The peak detector 200 is connected with the VGA module 100 and a variable speed integrator 400, for detecting the peak magnitude of the output signal transmitted from the VGA module 100, and transmitted to the peak speed of the variable integrator 400;

[0030] 阈值控制器300,与速度可变积分器400相连,用于在外部控制信号的控制下,选择输出不同的阈值; [0030] The threshold value controller 300, an integrator 400 coupled to the variable speed, the control for the next external control signal, selects and outputs different threshold values;

[0031] 速度可变积分器400,与峰值检测器200、阈值控制器300、VGA模块100、第一比较器500和第二比较器600相连,用于在对阈值和检测到的信号峰值比较后,进行正/负积分,并输出控制信号Vc; The variable [0031] the speed integrator 400, the peak detector 200, threshold controller 300, VGA module 100, a first comparator 500 and second comparator 600 is connected for comparing the peak threshold and the detected signal after, a positive / negative integrator, and outputs a control signal Vc of;

[0032] 第一比较器500,与第一计数器700和速度可变积分器400相连,用于比较控制信号Vc与外部比较信号V1的大小,并根据比较结果发送控制信号给第一计数器700 ; [0032] The first comparator 500, the first counter 700 and the integrator 400 is connected to a variable speed, for comparing the magnitude of the external control signal Vc and the comparison signal V1, and sends a control signal to the first counter 700 according to the comparison result;

[0033] 第二比较器600,与第二计数器800和速度可变积分器400相连,用于比较控制信号Vc与外部比较信号V2的大小,并根据比较结果发送控制信号给第一计数器800 ; [0033] The second comparator 600, the second counter 800 and an integrator 400 connected to a variable speed, the control signal Vc for comparing the comparison signal with the external size of V2, and sends a control signal to the first counter 800 according to the comparison result;

[0034] 第一计数器700,与第一比较器500和增益控制器900相连,用于根据第一比较器500发送的控制信号进行计数,并将计数结果发送给增益控制器900 ; [0034] The first counter 700, the first comparator 500 and the gain controller 900 is connected for counting in accordance with a control signal transmitted from the first comparator 500, and the counting result to the gain controller 900;

[0035] 第二计数器800,与第二比较器600和增益控制器900相连,用于根据第二比较器600发送的控制信号进行计数,并将计数结果发送给增益控制器900 ; [0035] The second counter 800, and the second comparator 600 and the gain controller 900 is connected to a control signal for counting the second comparator 600 is transmitted, and the counting result to the gain controller 900;

[0036] 增益控制器900,与第一计数器700、第二计数器800和VGA模块100相连,用于根据第一计数器700和第二计数器800发送的计数结果,向VGA模块100发送表示增加增益或降低增益的控制信号。 [0036] The gain controller 900, 700, the second counter 800 and the VGA module connected to the first counter 100, a first counter 700 according to the counting result and the second transmission counter 800, to increase the gain VGA 100 transmits a module or reduction control signal gain.

[0037] 其中,VGA模块100包括信号输入端101和102,信号输出端103和104,以及控制信号输入端105和106 ;信号输入端101和102输入差分中频信号;控制信号输入端105输入的控制信号Vc为模拟增益控制信号;控制信号输入端106输入的控制信号为数字增益控制信号;在实际应用中,当AGC用于接收机系统时,信号输入端101和102与混频器相连,即信号输入端输入的信号是混频之后的差分中频信号;VGA模块100根据控制信号的大小来确定对输入信号进行放大的倍数,从而将放大后的信号输出给峰值检测器200 ;图2示出了VGA模块100的内部电路原理结构示意图,假设信号输入端101和102的输入信号为VinJf 号输出端103和104的输出信号为Vout,信号输入端与混频器的输出端相连,VGA模块100 由四个数字放大子单元(Al、A2、A3、A4)和一个模拟放大子单元(A5)组成,数字放大子单元由增益 [0037] wherein, VGA module 100 includes a signal input terminal 101 and 102, signal output terminals 103 and 104, and a control signal input terminal 105 and 106; signal inputs 101 and 102 input differential IF signal; a control signal input terminal 105 inputs control signal Vc as an analog gain control signal; control signal input from the signal input terminal 106 into a digital gain control signal; in practice, when a receiver AGC system, and a signal input terminal 102 is connected to the mixer 101, that signal is a differential input terminal of the intermediate frequency signal after mixing; VGA module 100 determines multiple amplifying the input signal according to the magnitude of the control signal, thereby outputting the amplified signal to the peak detector 200; FIG. 2 shows a VGA circuit schematic structure of the internal module 100 of the diagram is assumed that the signal input terminal 101 and the input signal is Vout of 102, an output terminal and the signal input terminal is connected to the mixer output signal VinJf signal output terminal 103 and 104, VGA module four sub-unit 100 is amplified by the digital subunits (Al, A2, A3, A4) and an analog amplification subunit (A5) composed of a digital amplification gain 制器900发送的数字增益控制信号(D0、D1、D2和D3)控制其增益大小,模拟放 Digital gain control signal (D0, D1, D2 and D3) a control system 900 which transmits the gain of the analog put

6大子单元由速度可变积分器400发送的控制信号Vc控制其增益大小;数字放大子单元Al、 A2、A3和A4的增益范围可以根据实际系统要求设置为0〜10dB,或者其他增益范围;数字增益控制信号D0、D1、D2和D3的位数也可以根据实际系统要求进行设置;模拟放大子单元A5的增益和控制信号Vc的大小成正比,可以通过Vc进行动态调整,其增益范围可以根据实际系统要求设置。 6 large subunit by a variable speed transmission of the integrator 400 controls the gain control signal Vc size; subunit digital amplifier Al, A2, A3 and A4 gain range may be set according to actual system requirements 0~10dB, or other gain range ; digital gain control signal D0, D1, D2 and D3 bits may also be set according to actual system requirements; subunit analog amplifier and a gain control signal Vc proportional to the size of A5, can be dynamically adjusted by Vc, gain range It may be set according to actual system requirements.

[0038] 其中,峰值检测器200包括信号输入端201和202,以及信号输出端203 ;信号输入端201和202分别与VGA模块100的信号输出端103和104相连;峰值检测器200通过信号输出端203将峰值信息发送给速度可变积分器400。 [0038] wherein, the peak detector 200 includes a signal input terminal 201 and 202, and a signal output terminal 203; a signal input terminals 201 and 202 connected to the signal output terminal 103 and 104 VGA module 100, respectively; peak detector 200 via the signal output peak information terminal 203 transmits the variable speed integrator 400.

[0039] 其中,阈值控制器300包括控制信号输入端bl和b0,以及输出端301 ;控制信号输入端bl和bo与外部控制信号相连,输出端301输出不同的阈值,从而改变速度可变积分器400的积分速度。 [0039] wherein the threshold controller 300 includes a control signal input terminal bl and b0, and an output terminal 301; a control signal input terminal bl and bo external control signal is connected to a different output terminal 301 outputs the threshold value to change the speed of a variable integration speed integrator 400.

[0040] 其中,速度可变积分器400包括控制信号输入端403和404,阈值输入端402,峰值输入端401和积分输出端405 ;控制信号输入端403和404分别与阈值控制器300的控制信号输入端b0和bl相连,用于选择不同的积分常数,从而选择不同的积分速度;峰值输入端401和阈值输入端402的大小可以确定积分的方向,从而使输出的控制信号Vc增加或减小;图3示出了速度可变积分器400的电路原理结构示意图,阈值输入端402与阈值控制器300的输出端301相连,峰值输入端401与峰值检测器200的信号输出端203相连,速度可变积分器400根据峰值输入端401和阈值输入端402的大小,以及控制信号bl和b0的选择来确定正积分或负积分,从而确定积分速度。 [0040] wherein variable speed integrator 400 includes a control signal input terminals 403 and 404, the threshold input terminal 402, the peak input end 401 and an integrator output terminal 405; control signal input terminals 403 and 404, respectively, with a threshold value controller 300 signal input terminals b0 and bl are connected, to select a different integration constants, to select a different integration speeds; peak input terminal 401 and a threshold input direction size 402 may determine the integral end, so that the control signal Vc output by increasing or decreasing the small; FIG. 3 shows the speed of the variable integrator circuit principle structure 400 of the schematic, the threshold input-output terminal 301 terminal 402 with the threshold value the controller 300 is connected to the peak input signal output terminal 401 of the peak detector 200 is connected to 203, variable speed integrator 400 size 402, and a selection control signal b0 and bl positive integration is determined from the peak integration or negative input terminal 401 and a threshold input terminal, thereby determining the speed of integration.

[0041] 其中,第一比较器500包括输入端V1和502,以及输出端501 ;输入端V1接外部输入信号,输入端502与速度可变积分器400的积分输出端405相连;第一比较器500根据输入端V1和502的大小,发送递增计数使能控制信号给第一计数器700。 [0041] wherein, the first comparator 500 includes an input terminal V1, and 502, 501 and an output; an input terminal connected to an external input signal V1, the output of the integrator is connected to an input terminal 502 and the variable speed integrator 400. 405; a first comparator the input terminals V1 500 and size 502 transmits count-enable control signal to the first counter 700.

[0042] 其中,第二比较器600包括输入端V2和602,以及输出端601 ;输入端V2接外部输入信号,输入端602与速度可变积分器400的积分输出端405相连;第二比较器600根据输入端V2和602的大小,发送递减计数使能控制信号给第二计数器800。 [0042] wherein the second comparator 600 includes an input terminal V2 and 602, 601 and an output; an input terminal connected to an external input signal V2, the output of the integrator 602 and the input terminal of the variable speed integrator 400 is connected to terminal 405; a second comparator the input terminal 600 and V2 602 size, count down transmission enable control signal to the second counter 800.

[0043] 其中,第一计数器700包括输入端702、时钟输入端和信号输出端701 ;输入端702 与第一比较器500的输出端501相连;时钟输入端接外部时钟信号CLK ;第一计数器700根据输入端702的输入信号的高低电平,来确定是否递增计数,并把计数结果发送给增益控制器900。 [0043] wherein the first counter 700 includes an input 702, a clock input and a signal output terminal 701; 702 and a first input terminal connected to the output 501 of comparator 500; a clock input terminal of the CLK external clock signal; a first counter the input terminal 700 of the high and low signal 702, to determine whether to count up, and sends the count result to the gain controller 900.

[0044] 其中,第二计数器800包括输入端802、时钟输入端和信号输出端801 ;输入端802 与第二比较器600的输出端601相连;时钟输入端接外部时钟信号CLK ;第二计数器800根据输入端802的输入信号的高低电平,来确定是否递减计数,并把计数结果发送给增益控制器900。 [0044] wherein, the second counter 800 includes an input terminal 802, a clock input and a signal output terminal 801; 802 and a second input terminal connected to the output of comparator 601 600; and a clock input terminal of the CLK external clock signal; a second counter the high level input signal 800 is an input terminal 802, to determine whether to count down, and sends the count result to the gain controller 900.

[0045] 其中,增益控制器900包括输入端901和902,以及输出端103 ;增益控制器900根据输入端901和902的输入大小,进行逻辑运算,向VGA模块100发送表示增加增益或降低增益的控制信号。 [0045] wherein, the gain controller 900 includes an input 901 and 902, and an output terminal 103; 901 and gain controller 900 in accordance with an input size of the input terminal 902, performs a logic operation, the gain represents the increase or decrease VGA gain module 100 transmits the control signal. 在实际应用中,控制信号可以为N位增益控制字,其中N为自然数。 In practice, the control signal may be an N-bit gain control word, where N is a natural number.

[0046] 本发明实施例提供的混合模式AGC环路的工作原理是:峰值检测器200检测VGA 模块100当前时刻的输入幅度,并将峰值输入到速度可变积分器400 ;速度可变积分器400 比较输入信号401和402的大小,如果401大于402,则根据控制信号b0和bl的选择模式进行负积分,否则,则进行正积分,并输出积分控制信号Vc ;积分控制信号Vc —方面调整VGA 模块100的增益,另一方面被发送给第一比较器500和第二比较600,如果Vc的调整可以使VGA模块100达到输出幅度的要求,则AGC达到了目的;如果Vc的调整不能使VGA模块100 达到输出幅度的要求,则通过第一比较器500输出递增信号或第二比较器600输出递减信号,使第一计数器700开始递增计数或使第二计数器800开始递减计数,并将计数结果发送给增益控制器900 ;增益控制器900根据输入的计数结果,进行逻辑运算,输出调整增益控制 [0046] The mixed mode operation principle according to an embodiment of the AGC loop of the present invention are: the peak detector 200 detects the amplitude of the current input VGA timing module 100, and input to the peak speed of the variable integrator 400; variable speed integrator 400 compares the input magnitude signals 401 and 402, if 401 is greater than 402, is performed depending on the mode control signal b0 and bl negative integration, otherwise, for positive integration, and outputs an integration control signal Vc of; integration control signal Vc - aspect adjustment VGA gain module 100, on the other hand is sent to a first comparator 500 and second comparator 600, if Vc VGA adjustment module 100 can achieve the required output amplitude, to achieve the purpose of the AGC; if Vc adjustment can not VGA module 100 reaches the required output amplitude signal is incremented or decremented output of the second comparator 600 outputs the first comparison signal 500, the first counter 700 starts incrementing or decrementing the second counter 800 starts counting and counts result to the gain controller 900; gain controller 900 based on the count result of the input, performs a logic operation, the gain control output adjustment ,进而控制VGA模块100的增益。 , Then control module 100 of the VGA gain. 图4是本发明实施例混合模式AGC环路的计算机仿真结果,其中输入信号VT(/IN)为一个连续地且有微小变化的弱信号,VT(/0P)为VGA模块100输出的波形,VT(Atrl)为速度可变积分器400输出的控制信号Vc的波形。 FIG 4 is a computer simulation AGC loop mixed mode embodiment of the present invention, wherein the input signal VT (/ IN) is continuously and a slight change in a weak signal, VT (/ 0P) is a waveform of the output module VGA 100, VT (Atrl) is a variable speed waveform of the integrator 400 outputs a control signal Vc.

[0047] 本发明实施例通过VGA模块、速度可变积分器和增益控制器,对差分中频信号增益进行模拟和数字双重模式控制,使得VGA模块的输出信号幅度不随其输入信号变化而变化;本发明提供的AGC环路的电路结构简单且灵活,AGC工作速度可以进行选择,从而可以满足多种系统的要求。 [0047] The embodiments of the present invention, the amplitude of the output signal by VGA module embodiment, the variable speed control gain and an integrator, the gain of the differential IF signal dual mode analog and digital control, so that the VGA module does not vary with changes in the input signal; the present the circuit configuration of the AGC loop of the present invention to provide a simple and flexible, AGC operating speed may be selected to meet the requirements of various systems.

[0048] 以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 [0048] The foregoing is only preferred embodiments of the present invention, not intended to limit the present invention within the spirit and principle of the present invention, any modification, equivalent replacement, or improvement, it should be included in the present within the scope of the invention.

Claims (10)

  1. 1. 一种混合模式AGC环路,其特征在于,所述AGC环路包括VGA模块、峰值检测器、速度可变积分器、比较器、计数器、阈值控制器和增益控制器;所述VGA模块,与所述峰值检测器、速度可变积分器和增益控制器相连,用于接收外部输入信号,并根据所述速度可变积分器输出控制信号的大小对输入信号进行放大,将放大后的输入信号发送给所述峰值检测器,以及接收所述增益控制器输出的控制信号;所述峰值检测器,与所述VGA模块和速度可变积分器相连,用于检测所述VGA模块发送的输出信号的峰值大小,并将峰值发送给所述速度可变积分器;所述阈值控制器,与所述速度可变积分器相连,用于在外部控制信号的控制下,选择输出不同的阈值;所述速度可变积分器,与所述峰值检测器、阈值控制器、VGA模块和比较器相连,用于比较所述峰值检测器输出的峰 1. A hybrid AGC loop mode, wherein the AGC loop includes a VGA module, a peak detector, variable speed integrator, a comparator, a counter, and the controller gain controller threshold; the VGA module , and the peak detector, a variable speed and a gain controller coupled to the integrator, for receiving an external input signal, and to control the size of the variable integrator output signal for amplifying the input signal according to the speed of the amplified the input signal to the peak detector, and the gain controller receives the control signal output; said peak detector, connected to the VGA module integrator and variable speed, for detecting said transmitted VGA module peak magnitude of the output signal, and transmitted to the peak value of the variable speed integrator; coupled to the threshold controller, the integrator variable speed, under control of an external control signal, selecting different output threshold value ; said variable speed integrator, the peak detector, connected to the threshold controller, VGA module and a comparator for comparing the peak detector output peak 与所述阈值控制器输出的阈值之间的大小,如果所述峰值检测器输出的峰值大于所述阈值控制器输出的阈值,则根据所述阈值控制器的外部控制信号的选择模式进行负积分,否则进行正积分,并输出控制信号;所述比较器,与所述计数器和速度可变积分器相连,用于比较所述速度可变积分器输出的控制信号与外部比较信号的大小,并根据比较结果发送控制信号给所述计数器;所述计数器,与所述比较器和增益控制器相连,用于根据所述比较器发送的控制信号和外部时钟信号进行计数,并将计数结果发送给所述增益控制器;所述增益控制器,与所述计数器和VGA模块相连,用于根据所述计数器发送的计数结果,向所述VGA模块发送表示增加增益或降低增益的控制信号。 Magnitude between the threshold and the threshold value of the controller output peak if the peak detector output is greater than the threshold value of the threshold value output from the controller, the integration is performed depending on the mode of negative external control signal of the threshold value controller otherwise, a positive integrator, and outputs a control signal; said comparator, coupled to the counter and the variable speed integrator for comparing the magnitude of the variable speed control signal and the comparison signal of the external output of the integrator, and transmission control according to the comparison result signal to the counter; the counter, and a gain of the comparator is connected to a controller, for counting the control signals and the external clock signal sent by the comparator and the counting result to the the gain controller; said gain controller, coupled to the counter and the VGA module, based on the count result of the counter for transmission to the VGA module transmits a control signal to increase or decrease the gain of the gain.
  2. 2.如权利要求1所述的混合模式AGC环路,其特征在于,所述VGA模块包括信号输入端,信号输出端和控制信号输入端;所述信号输入端输入差分中频信号,所述控制信号输入端输入的控制信号为模拟增益控制信号或数字增益控制信号。 2. The mixed mode of the AGC loop of claim 1, wherein said module comprises a VGA signal input terminal, a signal output terminal and a control signal input terminal; signal input terminal of the differential IF signal, the control a control signal input terminal of the gain control signal into an analog or digital gain control signal.
  3. 3.如权利要求1所述的混合模式AGC环路,其特征在于,所述VGA模块由多个数字放大子单元和一个模拟放大子单元组成;一个数字放大子单元的输入端与所述VGA模块的信号输入端相连;每个数字放大子单元彼此相互连接,并且最后一个数字放大子单元的输出端与所述模拟放大子单元的输入端相连;所述模拟放大子单元的输出端与所述VGA模块的信号输出端相连。 3. The mixed mode of the AGC loop of claim 1, wherein said plurality of digital amplifying module VGA subunit and a subunit analog amplifying composition; subunit of a digital amplifier input and the VGA module is connected to the signal input terminal; amplifying each digital sub-unit connected to each other, and the last number of the amplified output of the analog sub-unit connected to an input terminal of amplifying subunit; amplifying the analog output terminal of the sub-unit and VGA signal output terminal connected to said module.
  4. 4.如权利要求1所述的混合模式AGC环路,其特征在于,所述峰值检测器包括信号输入端和信号输出端;所述信号输入端与所述VGA模块的信号输出端相连;所述峰值检测器通过所述信号输出端将峰值信息发送给所述速度可变积分器。 4. The hybrid AGC loop mode according to claim 1, wherein said peak detector includes a signal input and a signal output terminal; coupled to said signal output terminal and the signal input of the VGA module; the transmitting said peak detector to the peak information rate through said variable integrator signal output terminal.
  5. 5.如权利要求1所述的混合模式AGC环路,其特征在于,所述阈值控制器包括控制信号输入端和输出端;所述控制信号输入端与外部控制信号相连,所述输出端输出不同的阈值。 5. The hybrid mode of the AGC loop of claim 1, wherein said threshold controller comprises a control signal input terminal and an output terminal; and a control signal input terminal is connected to an external control signal, the output terminal different thresholds.
  6. 6.如权利要求1所述的混合模式AGC环路,其特征在于,所述速度可变积分器包括控制信号输入端、阈值输入端、峰值输入端和积分输出端;所述控制信号输入端用于选择不同的积分常数;所述峰值输入端输入的信号和阈值输入端输入的信号的大小,用于确定积分的方向。 6. The mixed mode of the AGC loop of claim 1, wherein said integrator comprises a variable speed control signal input, a threshold input terminal, an input terminal and a peak integral output; the control signal input terminal for selecting different integral constant; said peak magnitude of the signal input terminal and a threshold input terminal inputted an input signal for determining the direction of integration.
  7. 7.如权利要求1所述的混合模式AGC环路,其特征在于,所述比较器包括第一比较器和第二比较器;所述第一比较器和第二比较器分别包括两个输入端和一个输出端;一个输入端接外部输入信号,另一个输入端与所述速度可变积分器的积分输出端相连;所述第一比较器的输出端用于发送递增计数使能控制信号给所述计数器;所述第二比较器的输出端用于发送递减计数使能控制信号给所述计数器。 7. The hybrid mode of the AGC loop of claim 1, wherein said comparator comprises a first comparator and a second comparator; the first comparator and the second comparator comprises two inputs respectively and an output terminal; a external input signal input end, and the other input terminal of the variable speed integrated output of the integrator is connected; a first comparator output terminal for transmitting the count-enable control signal to the counter; an output terminal of the second comparator for transmitting down-count enable control signal to said counter.
  8. 8.如权利要求7所述的混合模式AGC环路,其特征在于,所述计数器包括第一计数器和第二计数器;所述第一计数器和第二计数器分别包括输入端、时钟输入端和信号输出端; 所述第一计数器的输入端与所述第一比较器的输出端相连;所述第二计数器的输入端与所述第二比较器的输出端相连;所述时钟输入端接外部时钟信号;所述第一计数器根据其输入端的输入信号的高低电平,来确定是否递增计数,并把计数结果发送给所述增益控制器; 所述第二计数器根据其输入端的输入信号的高低电平,来确定是否递减计数,并把计数结果发送给所述增益控制器。 8. The mixed mode of the AGC loop of claim 7, wherein said counter comprises a first and second counters; the first and second counters, respectively, includes an input terminal, a clock input signal and an output terminal; a first output of the input of the counter and the first comparator is connected; an input terminal connected to the output of said second counter and the second comparator; said external clock input termination a clock signal; the first counter according to a high level input signal at its input, to determine whether the count is incremented, and sends the count result to the gain controller; level of an input signal at its input according to the second counter level, to determine whether to count down, and sends the count result to the gain controller.
  9. 9.如权利要求1所述的混合模式AGC环路,其特征在于,所述增益控制器包括输入端和输出端;所述增益控制器根据所述输入端的输入大小,进行逻辑运算,向所述VGA模块发送表示增加增益或降低增益的控制信号。 9. The hybrid AGC loop mode according to claim 1, wherein said gain controller comprises an input and an output; an input of said gain controller according to the size of said input terminals, a logic operation to the said module transmits a VGA gain to increase or decrease the gain control signal.
  10. 10.如权利要求1或8所述的混合模式AGC环路,其特征在于,所述表示增加增益或降低增益的控制信号为N位增益控制字,其中N为自然数。 10. A mixed mode or claim 18 wherein N is a natural number claim AGC loop, wherein the gain represents the increase or decrease of the gain control signal for the N-bit gain control word.
CN 200910302631 2009-05-26 2009-05-26 Mixed-mode AGC loop CN101557205B (en)

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CN102386869A (en) * 2010-08-27 2012-03-21 杭州中科微电子有限公司 Analog/digital configurable variable-gain amplifier
US8638249B2 (en) * 2012-04-16 2014-01-28 Infineon Technologies Ag System and method for high input capacitive signal amplifier
CN102647164B (en) * 2012-04-26 2014-06-18 中国科学院微电子研究所 Automatic gain control loop of medical equipment with ultra-low power consumption
CN106571787A (en) * 2016-11-13 2017-04-19 天津大学 Digital-analog hybrid automatic gain control amplifier

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FR2745666A1 (en) 1996-02-29 1997-09-05 Sgs Thomson Microelectronics Automatic gain control circuit for mixed analogue-digital signal processing circuits
CN1236504A (en) 1997-06-03 1999-11-24 皇家菲利浦电子有限公司 Automatic gain control circuit, e. g. for use in a hard disk drive
JP2005057595A (en) 2003-08-06 2005-03-03 Matsushita Electric Ind Co Ltd Agc circuit
CN1665128A (en) 2005-03-30 2005-09-07 哈尔滨工业大学 Multi-level auto-gain control integrated circuit system having gain indication function
US6977550B2 (en) 2003-03-11 2005-12-20 Matsushita Electric Industrial Co., Ltd. AGC circuit

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Publication number Priority date Publication date Assignee Title
FR2745666A1 (en) 1996-02-29 1997-09-05 Sgs Thomson Microelectronics Automatic gain control circuit for mixed analogue-digital signal processing circuits
CN1236504A (en) 1997-06-03 1999-11-24 皇家菲利浦电子有限公司 Automatic gain control circuit, e. g. for use in a hard disk drive
US6977550B2 (en) 2003-03-11 2005-12-20 Matsushita Electric Industrial Co., Ltd. AGC circuit
JP2005057595A (en) 2003-08-06 2005-03-03 Matsushita Electric Ind Co Ltd Agc circuit
CN1665128A (en) 2005-03-30 2005-09-07 哈尔滨工业大学 Multi-level auto-gain control integrated circuit system having gain indication function

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