CN101557205B - Mixed mode AGC loop - Google Patents
Mixed mode AGC loop Download PDFInfo
- Publication number
- CN101557205B CN101557205B CN2009103026318A CN200910302631A CN101557205B CN 101557205 B CN101557205 B CN 101557205B CN 2009103026318 A CN2009103026318 A CN 2009103026318A CN 200910302631 A CN200910302631 A CN 200910302631A CN 101557205 B CN101557205 B CN 101557205B
- Authority
- CN
- China
- Prior art keywords
- signal
- input
- output
- counter
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000010354 integration Effects 0.000 claims description 19
- 230000003321 amplification Effects 0.000 claims description 9
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 9
- 238000004088 simulation Methods 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 4
- 230000000052 comparative effect Effects 0.000 claims description 4
- 230000009467 reduction Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 5
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
The invention discloses a mixed mode AGC loop, and belongs to the technical field of electronics. The AGC loop comprises a VGA module, a peak detector, a speed variable integrator, a comparator, a counter, a threshold controller and a gain controller; the VGA module is connected with the peak detector, the speed variable integrator and the gain controller; the peak detector is connected with the VGA module and the variable speed integrator; the threshold controller is connected with the speed variable integrator; the speed variable integrator is connected with the peak detector, the threshold controller, the VGA module and the comparator; the comparator is connected with the counter and the speed variable integrator; the counter is connected with the comparator and the gain controller; the gain controller is connected with the counter and the VGA module. The invention controls the gain of the differential intermediate frequency signal in an analog and digital dual mode, so that the amplitude of the output signal of the VGA module does not change along with the change of the input signal; the AGC loop circuit is simple and flexible in structure.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of mixed-mode AGC loop.
Background technology
Automatic gain control (AGC, Automatic Gain Control) is widely used in all kinds of electronic systems, is used to increase the dynamic range of electronic system.An AGC mainly is made up of variable gain amplifier (VGA, VariableGain Amplifier) and detection control circuit two parts; Detect the amplitude that control circuit is used to detect the VGA output signal, and produce the output gain that control signal is adjusted VGA, the amplitude of VGA output signal is not changed with its input by certain algorithm.In the prior art, detecting control circuit has two kinds of implementation methods: one is to adopt analogy method to detect the peak value of VGA output signal, and peak signal is carried out feeding back to VGA after low pass filtered involves amplification, and then the gain of control VGA output signal; Its two, be to adopt digital method to detect the peak value of VGA output signal, and after peak signal necessarily handled, produce digital control amount, adjust the output gain signal of VGA.
But all there is defective in the implementation method of above-mentioned two kinds of detection control circuits; At first, the analog detection control method is difficult to realize the control of broad gain ranging, and AGC speed is slower; Secondly, though Digital Detecting Method can obtain the control of broad gain ranging, if electronic system does not have A/D converter, AGC can't realize so.
Summary of the invention
Can't realize the control of broad gain ranging in order to solve the analog detection control method, AGC speed is slow, and Digital Detecting Method can't realize problems such as AGC sometimes, the invention provides a kind of mixed-mode AGC loop, described AGC loop comprises VGA module, peak detector, variable speed integrator, comparator, counter, threshold controller and gain controller;
Described VGA module, link to each other with described peak detector, variable speed integrator and gain controller, be used to receive external input signal, and input signal is amplified according to the size of described variable speed integrator output control signal, input signal after amplifying is sent to described peak detector, and the control signal that receives described gain controller output;
Described peak detector links to each other with variable speed integrator with described VGA module, is used to detect the peak value size of the output signal that described VGA module sends, and peak value is sent to described variable speed integrator;
Described threshold controller links to each other with described variable speed integrator, is used under the control of control signal externally, selects the different threshold value of output;
Described variable speed integrator, link to each other with comparator with described peak detector, threshold controller, VGA module, size between the threshold value that the peak value that is used for the output of more described peak detector and described threshold controller are exported, if the peak value of described peak detector output is greater than the threshold value of described threshold controller output, then bear integration according to the preference pattern of the external control signal of described threshold controller, otherwise carry out positive integration, and output control signal;
Described comparator links to each other with variable speed integrator with described counter, is used for the control signal of more described variable speed integrator output and the size of outside comparison signal, and transmits control signal to described counter according to comparative result;
Described counter links to each other with gain controller with described comparator, is used for counting according to control signal and external timing signal that described comparator sends, and count results is sent to described gain controller;
Described gain controller links to each other with the VGA module with described counter, is used for the count results according to described counter transmission, sends the control signal that expression increases gain or reduction gain to described VGA module.
Described VGA module comprises signal input part, signal output part and signal input end; Described signal input part input difference intermediate-freuqncy signal, the control signal of described signal input end input is analog gain control signal or digital gain control signal.
Described VGA module amplifies subelement by a plurality of numerals and a simulation amplification subelement is formed; The input of a numeral amplification subelement links to each other with the signal input part of described VGA module; Each numeral is amplified subelement and is interconnected with one another, and the output of last numeral amplification subelement links to each other with the input that subelement is amplified in described simulation; The output that subelement is amplified in described simulation links to each other with the signal output part of described VGA module.
Described peak detector comprises signal input part and signal output part; Described signal input part links to each other with the signal output part of described VGA module; Described peak detector sends to described variable speed integrator by described signal output part with peak information.
Described threshold controller comprises signal input end and output; Described signal input end links to each other with external control signal, the different threshold value of described output output.
Described variable speed integrator comprises signal input end, threshold value input, peak value input and integration output; Described signal input end is used to select different integral constants; The size of the signal of the signal of described peak value input input and the input of threshold value input is used for determining the direction of integration.
Described comparator comprises first comparator and second comparator; Described first comparator and second comparator comprise two inputs and an output respectively; An input termination external input signal, another input links to each other with the integration output of described variable speed integrator; The output of described first comparator is used for sending and increases progressively counting and enable control signal to described counter; The output of described second comparator is used to send countdown and enables control signal to described counter.
Described counter comprises first counter and second counter; Described first counter and second counter comprise input, input end of clock and signal output part respectively; The input of described first counter links to each other with the output of described first comparator; The input of described second counter links to each other with the output of described second comparator; Described input end of clock connects external timing signal; Described first counter determines whether to increase progressively counting according to the high-low level of the input signal of its input, and count results is sent to described gain controller; Described second counter determines whether countdown according to the high-low level of the input signal of its input, and count results is sent to described gain controller.
Described gain controller comprises input and output; Described gain controller carries out logical operation according to the input size of described input, sends the control signal that expression increases gain or reduces gain to described VGA module.
Described expression increases gain or reduces the control signal that gains is N position gain controlling word, and wherein N is a natural number.
Beneficial effect: the present invention is by VGA module, variable speed integrator and gain controller, and analog-and digital-double-mode control is carried out in gain to differential intermediate frequency, makes the amplitude output signal of VGA module not change with its input signal; The circuit structure of AGC loop provided by the invention is simple and flexibly, the AGC operating rate can be selected, thereby can satisfy the requirement of multiple systems.
Description of drawings
Fig. 1 is the AGC loop circuit theory structure schematic diagram that the embodiment of the invention provides;
Fig. 2 is the internal circuit theory structure schematic diagram of embodiment of the invention VGA module;
Fig. 3 is the circuit principle structure schematic diagram of embodiment of the invention variable speed integrator;
Fig. 4 is the computer artificial result curve chart of embodiment of the invention mixed-mode AGC loop.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
Referring to Fig. 1, the embodiment of the invention provides a kind of mixed-mode AGC loop, comprises VGA module 100, peak detector 200, variable speed integrator 400, first comparator 500, second comparator 600, first counter 700, second counter 800, threshold controller 300 and gain controller 900;
VGA module 100, link to each other with peak detector 200, variable speed integrator 400 and gain controller 900, be used to receive external input signal, and input signal is amplified according to the size of variable speed integrator 400 output control signals (Vc), input signal after amplifying is sent to peak detector 200, and the control signal of receiving gain controller 900 outputs;
Peak detector 200 links to each other with variable speed integrator 400 with VGA module 100, is used to detect the peak value size of the output signal that VGA module 100 sends, and peak value is sent to variable speed integrator 400;
Threshold controller 300 links to each other with variable speed integrator 400, is used under the control of control signal externally, selects the different threshold value of output;
First comparator 500 links to each other with variable speed integrator 400 with first counter 700, is used for comparison control signal Vc and outside comparison signal V
1Size, and transmit control signal to first counter 700 according to comparative result;
Second comparator 600 links to each other with variable speed integrator 400 with second counter 800, is used for comparison control signal Vc and outside comparison signal V
2Size, and transmit control signal to first counter 800 according to comparative result;
First counter 700 links to each other with gain controller 900 with first comparator 500, is used for counting according to the control signal that first comparator 500 sends, and count results is sent to gain controller 900;
Second counter 800 links to each other with gain controller 900 with second comparator 600, is used for counting according to the control signal that second comparator 600 sends, and count results is sent to gain controller 900;
Gain controller 900, link to each other with VGA module 100 with first counter 700, second counter 800, be used for count results, send the control signal that expression increases gain or reduction gain to VGA module 100 according to first counter 700 and 800 transmissions of second counter.
Wherein, VGA module 100 comprises signal input part 101 and 102, signal output part 103 and 104, and signal input end 105 and 106; Signal input part 101 and 102 input difference intermediate-freuqncy signals; The control signal Vc of signal input end 105 inputs is the analog gain control signal; The control signal of signal input end 106 inputs is the digital gain control signal; In actual applications, when AGC was used for receiver system, signal input part 101 linked to each other with frequency mixer with 102, i.e. the signal of signal input part input is the differential intermediate frequency after the mixing; VGA module 100 is determined input signal is carried out amplification multiple according to the size of control signal, thereby the signal after will amplifying is exported to peak detector 200; Fig. 2 shows the internal circuit theory structure schematic diagram of VGA module 100, the input signal of supposing signal input part 101 and 102 is Vin, signal output part 103 and 104 output signal are Vout, signal input part links to each other with the output of frequency mixer, VGA module 100 is amplified subelement (A1 by four numerals, A2, A3, A4) and a simulation amplify subelement (A5) and form, numeral is amplified the digital gain control signal (D0 that subelement is sent by gain controller 900, D1, D2 and D3) control its gain size, the control signal Vc that simulation amplification subelement is sent by variable speed integrator 400 controls its gain size; The gain ranging that numeral is amplified subelement A1, A2, A3 and A4 can require to be set to 0～10dB, perhaps other gain rangings according to real system; The figure place of digital gain control signal D0, D1, D2 and D3 also can require to be provided with according to real system; The gain of subelement A5 is amplified in simulation and the size of control signal Vc is directly proportional, and can dynamically adjust by Vc, and its gain ranging can require to be provided with according to real system.
Wherein, peak detector 200 comprises signal input part 201 and 202, and signal output part 203; Signal input part 201 links to each other with 104 with the signal output part 103 of VGA module 100 respectively with 202; Peak detector 200 sends to variable speed integrator 400 by signal output part 203 with peak information.
Wherein, threshold controller 300 comprises signal input end b1 and b0, and output 301; Signal input end b1 links to each other with external control signal with b0, the different threshold value of output 301 outputs, thereby the integrating rate of change variable speed integrator 400.
Wherein, variable speed integrator 400 comprises signal input end 403 and 404, threshold value input 402, peak value input 401 and integration output 405; Signal input end 403 links to each other with b1 with the signal input end b0 of threshold controller 300 respectively with 404, is used to select different integral constants, thereby selects different integrating rates; The size of peak value input 401 and threshold value input 402 can be determined the direction of integration, thereby the control signal Vc of output is increased or reduces; Fig. 3 shows the circuit principle structure schematic diagram of variable speed integrator 400, threshold value input 402 links to each other with the output 301 of threshold controller 300, peak value input 401 links to each other with the signal output part 203 of peak detector 200, variable speed integrator 400 is according to the size of peak value input 401 and threshold value input 402, and the selection of control signal b1 and b0 determines positive integration or negative integration, thereby determines integrating rate.
Wherein, first comparator 500 comprises input V
1With 502, and output 501; Input V
1Connect external input signal, input 502 links to each other with the integration output 405 of variable speed integrator 400; First comparator 500 is according to input V
1With 502 size, transmission increases progressively counting and enables control signal to first counter 700.
Wherein, second comparator 600 comprises input V
2With 602, and output 601; Input V
2Connect external input signal, input 602 links to each other with the integration output 405 of variable speed integrator 400; Second comparator 600 is according to input V
2Size with 602 sends countdown and enables control signal to second counter 800.
Wherein, first counter 700 comprises input 702, input end of clock and signal output part 701; Input 702 links to each other with the output 501 of first comparator 500; Input end of clock meets external timing signal CLK; First counter 700 determines whether to increase progressively counting according to the high-low level of the input signal of input 702, and count results is sent to gain controller 900.
Wherein, second counter 800 comprises input 802, input end of clock and signal output part 801; Input 802 links to each other with the output 601 of second comparator 600; Input end of clock meets external timing signal CLK; Second counter 800 determines whether countdown according to the high-low level of the input signal of input 802, and count results is sent to gain controller 900.
Wherein, gain controller 900 comprises input 901 and 902, and output 103; Gain controller 900 carries out logical operation according to the input size of input 901 and 902, sends the control signal that expression increases gain or reduces gain to VGA module 100.In actual applications, control signal can be N position gain controlling word, and wherein N is a natural number.
The operation principle of the mixed-mode AGC loop that the embodiment of the invention provides is: peak detector 200 detects the input range of VGA module 100 current times, and peak value is input to variable speed integrator 400; If variable speed integrator 400 comparator input signals 401 and 402 size 401 greater than 402, are then born integration according to the preference pattern of control signal b0 and b1, otherwise, then carry out positive integration, and output integral control signal Vc; Integral control signal Vc adjusts the gain of VGA module 100 on the one hand, is sent to first comparator 500 and second on the other hand and compares 600, if the adjustment of Vc can make VGA module 100 reach the requirement of output amplitude, then AGC has reached purpose; If the adjustment of Vc can not make VGA module 100 reach the requirement of output amplitude, then by first comparator, the 500 output increment signal or second comparator 600 outputs the successively decreasing signal, make first counter 700 begin to increase progressively counting or make second counter 800 beginning countdowns, and count results is sent to gain controller 900; Gain controller 900 carries out logical operation according to the count results of input, and the gain controlling word is adjusted in output, and then the gain of control VGA module 100.Fig. 4 is the computer artificial result of embodiment of the invention mixed-mode AGC loop, wherein input signal VT (/IN) be one continuously and the weak signal of minor variations arranged, VT (/OP) be the waveform of VGA module 100 output, VT (/Vtrl) be the waveform of the control signal Vc that exports of variable speed integrator 400.
The embodiment of the invention is by VGA module, variable speed integrator and gain controller, and analog-and digital-double-mode control is carried out in gain to differential intermediate frequency, makes the amplitude output signal of VGA module not change with its input signal; The circuit structure of AGC loop provided by the invention is simple and flexibly, the AGC operating rate can be selected, thereby can satisfy the requirement of multiple systems.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a mixed-mode AGC loop is characterized in that, described AGC loop comprises VGA module, peak detector, variable speed integrator, comparator, counter, threshold controller and gain controller;
Described VGA module, link to each other with described peak detector, variable speed integrator and gain controller, be used to receive external input signal, and input signal is amplified according to the size of described variable speed integrator output control signal, input signal after amplifying is sent to described peak detector, and the control signal that receives described gain controller output;
Described peak detector links to each other with variable speed integrator with described VGA module, is used to detect the peak value size of the output signal that described VGA module sends, and peak value is sent to described variable speed integrator;
Described threshold controller links to each other with described variable speed integrator, is used under the control of control signal externally, selects the different threshold value of output;
Described variable speed integrator, link to each other with comparator with described peak detector, threshold controller, VGA module, size between the threshold value that the peak value that is used for the output of more described peak detector and described threshold controller are exported, if the peak value of described peak detector output is greater than the threshold value of described threshold controller output, then bear integration according to the preference pattern of the external control signal of described threshold controller, otherwise carry out positive integration, and output control signal;
Described comparator links to each other with variable speed integrator with described counter, is used for the control signal of more described variable speed integrator output and the size of outside comparison signal, and transmits control signal to described counter according to comparative result;
Described counter links to each other with gain controller with described comparator, is used for counting according to control signal and external timing signal that described comparator sends, and count results is sent to described gain controller;
Described gain controller links to each other with the VGA module with described counter, is used for the count results according to described counter transmission, sends the control signal that expression increases gain or reduction gain to described VGA module.
2. mixed-mode AGC loop as claimed in claim 1 is characterized in that, described VGA module comprises signal input part, signal output part and signal input end; Described signal input part input difference intermediate-freuqncy signal, the control signal of described signal input end input is analog gain control signal or digital gain control signal.
3. mixed-mode AGC loop as claimed in claim 1 is characterized in that, described VGA module amplifies subelement by a plurality of numerals and a simulation amplification subelement is formed; The input of a numeral amplification subelement links to each other with the signal input part of described VGA module; Each numeral is amplified subelement and is interconnected with one another, and the output of last numeral amplification subelement links to each other with the input that subelement is amplified in described simulation; The output that subelement is amplified in described simulation links to each other with the signal output part of described VGA module.
4. mixed-mode AGC loop as claimed in claim 1 is characterized in that described peak detector comprises signal input part and signal output part; Described signal input part links to each other with the signal output part of described VGA module; Described peak detector sends to described variable speed integrator by described signal output part with peak information.
5. mixed-mode AGC loop as claimed in claim 1 is characterized in that described threshold controller comprises signal input end and output; Described signal input end links to each other with external control signal, the different threshold value of described output output.
6. mixed-mode AGC loop as claimed in claim 1 is characterized in that, described variable speed integrator comprises signal input end, threshold value input, peak value input and integration output; Described signal input end is used to select different integral constants; The size of the signal of the signal of described peak value input input and the input of threshold value input is used for determining the direction of integration.
7. mixed-mode AGC loop as claimed in claim 1 is characterized in that, described comparator comprises first comparator and second comparator; Described first comparator and second comparator comprise two inputs and an output respectively; An input termination external input signal, another input links to each other with the integration output of described variable speed integrator; The output of described first comparator is used for sending and increases progressively counting and enable control signal to described counter; The output of described second comparator is used to send countdown and enables control signal to described counter.
8. mixed-mode AGC loop as claimed in claim 7 is characterized in that, described counter comprises first counter and second counter; Described first counter and second counter comprise input, input end of clock and signal output part respectively; The input of described first counter links to each other with the output of described first comparator; The input of described second counter links to each other with the output of described second comparator; Described input end of clock connects external timing signal; Described first counter determines whether to increase progressively counting according to the high-low level of the input signal of its input, and count results is sent to described gain controller; Described second counter determines whether countdown according to the high-low level of the input signal of its input, and count results is sent to described gain controller.
9. mixed-mode AGC loop as claimed in claim 1 is characterized in that described gain controller comprises input and output; Described gain controller carries out logical operation according to the input size of described input, sends the control signal that expression increases gain or reduces gain to described VGA module.
10. as claim 1 or 8 described mixed-mode AGC loops, it is characterized in that described expression increases gain or reduces the control signal that gains is N position gain controlling word, wherein N is a natural number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009103026318A CN101557205B (en) | 2009-05-26 | 2009-05-26 | Mixed mode AGC loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009103026318A CN101557205B (en) | 2009-05-26 | 2009-05-26 | Mixed mode AGC loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101557205A CN101557205A (en) | 2009-10-14 |
| CN101557205B true CN101557205B (en) | 2011-04-06 |
Family
ID=41175179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009103026318A Expired - Fee Related CN101557205B (en) | 2009-05-26 | 2009-05-26 | Mixed mode AGC loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101557205B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386869A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | Analog/digital configurable variable-gain amplifier |
| US8638249B2 (en) * | 2012-04-16 | 2014-01-28 | Infineon Technologies Ag | System and method for high input capacitive signal amplifier |
| CN102647164B (en) * | 2012-04-26 | 2014-06-18 | 中国科学院微电子研究所 | Automatic gain control loop of ultralow-power-consumption medical equipment |
| CN105932974A (en) * | 2016-04-25 | 2016-09-07 | 复旦大学 | Programmable amplifier circuit having pseudo resistor failure detection function |
| US9831836B1 (en) * | 2016-10-07 | 2017-11-28 | Silicon Laboratories Inc. | Automatic gain control (AGC) circuit and method to control amplifier gain based on a duration of an overload condition |
| CN106571787B (en) * | 2016-11-13 | 2019-02-01 | 天津大学 | A kind of numerical model analysis automatic gain control amplifier |
| CN109546983A (en) * | 2018-11-20 | 2019-03-29 | 上海东软载波微电子有限公司 | A kind of automatic gain control equipment and auto gain control method |
| CN113872540A (en) * | 2021-08-16 | 2021-12-31 | 广州润芯信息技术有限公司 | Loop automatic gain control device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2745666A1 (en) * | 1996-02-29 | 1997-09-05 | Sgs Thomson Microelectronics | Automatic gain control circuit for mixed analogue-digital signal processing circuits |
| CN1236504A (en) * | 1997-06-03 | 1999-11-24 | 皇家菲利浦电子有限公司 | Automatic gain control circuit, e. g. for use in a hard disk drive |
| JP2005057595A (en) * | 2003-08-06 | 2005-03-03 | Matsushita Electric Ind Co Ltd | Agc circuit |
| CN1665128A (en) * | 2005-03-30 | 2005-09-07 | 哈尔滨工业大学 | Multi-level auto-gain control integrated circuit system having gain indication function |
| US6977550B2 (en) * | 2003-03-11 | 2005-12-20 | Matsushita Electric Industrial Co., Ltd. | AGC circuit |
-
2009
- 2009-05-26 CN CN2009103026318A patent/CN101557205B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2745666A1 (en) * | 1996-02-29 | 1997-09-05 | Sgs Thomson Microelectronics | Automatic gain control circuit for mixed analogue-digital signal processing circuits |
| CN1236504A (en) * | 1997-06-03 | 1999-11-24 | 皇家菲利浦电子有限公司 | Automatic gain control circuit, e. g. for use in a hard disk drive |
| US6977550B2 (en) * | 2003-03-11 | 2005-12-20 | Matsushita Electric Industrial Co., Ltd. | AGC circuit |
| JP2005057595A (en) * | 2003-08-06 | 2005-03-03 | Matsushita Electric Ind Co Ltd | Agc circuit |
| CN1665128A (en) * | 2005-03-30 | 2005-09-07 | 哈尔滨工业大学 | Multi-level auto-gain control integrated circuit system having gain indication function |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101557205A (en) | 2009-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101557205B (en) | Mixed mode AGC loop | |
| CN101650387B (en) | Envelope detector for high speed applications | |
| CN100492912C (en) | Signal processing method and device | |
| CN110753221B (en) | Real-time correction system for serial image data training of CMOS image sensor | |
| CN101782885B (en) | Method and device for adjusting pull-up resistor of IIC bus and IIC bus device | |
| CN103210582A (en) | RF power amplifier circuit mismatch tolerance | |
| CN101005284A (en) | Automatic gain control apparatus | |
| CN106571787A (en) | Digital-analog hybrid automatic gain control amplifier | |
| JPH0338907A (en) | Transmission output power controller | |
| CN108028632A (en) | Communication equipment with antenna damping compensation | |
| CN102291814B (en) | Radio frequency (RF) automatic gain control (AGC) system and method thereof | |
| CN105490654A (en) | Automatic gain controller control method of voice acquisition system and circuit thereof | |
| CN201674469U (en) | Audio-frequency power amplifier circuit with automatic gain control circuit | |
| CN201114040Y (en) | Radio frequency power open-loop control device | |
| CN101295965B (en) | Digital automatic gain control circuit apparatus | |
| CN112161525B (en) | Data analysis method for receiving circuit of electronic detonator initiator | |
| US20100271074A1 (en) | Comparison circuit, integrated circuit device and electronic apparatus | |
| CN102594743B (en) | Adpative equalizing circuit and method thereof | |
| CN102270971A (en) | Low-power-consumption and high-integration-level automatic gain control amplifier | |
| CN203813771U (en) | Large dynamic-range digital channelized receiver based on FPGA | |
| US11962322B2 (en) | Signal dependent reconfigurable data acquisition system | |
| CN201733282U (en) | Self-adapting amplifier circuit with variable gain and time varying gain | |
| CN102255608A (en) | Automatic gain regulating circuit with large dynamic range | |
| CN103151998B (en) | A kind of feed-forward type AGC device | |
| CN101350675B (en) | Threshold value detection circuit system for limiting amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20091014 Assignee: ZHENJIANG ATEC SEMICONDUCTOR Co.,Ltd. Assignor: Institute of Microelectronics of the Chinese Academy of Sciences Contract record no.: 2013990000128 Denomination of invention: Mixed-mode AGC loop Granted publication date: 20110406 License type: Exclusive License Record date: 20130328 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110406 Termination date: 20210526 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |