CN101553925B - P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same - Google Patents

P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same Download PDF

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CN101553925B
CN101553925B CN 200780042606 CN200780042606A CN101553925B CN 101553925 B CN101553925 B CN 101553925B CN 200780042606 CN200780042606 CN 200780042606 CN 200780042606 A CN200780042606 A CN 200780042606A CN 101553925 B CN101553925 B CN 101553925B
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conductor
diode
dielectric
layer
formula
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CN101553925A (en
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S·布拉德·赫纳
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桑迪士克3D公司
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Priority to US11/560,289 priority patent/US8018024B2/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only

Abstract

本发明描述一种用于形成具有减小的编程电压的非易失性一次性可编程存储器单元的方法。 The present invention describes a method for forming a one-time programmable non-volatile memory cell programming method has a reduced voltage. 将相连式pin二极管与介电破裂反熔丝配成对,所述介电破裂反熔丝由具有大于约8的介电常数的高介电常数材料形成。 The pin diode is connected to the formula and the dielectric rupture antifuse paired to the dielectric rupture antifuse is formed of a high dielectric constant material having a dielectric constant greater than about 8. 在优选实施例中,通过原子层沉积形成所述高介电常数材料。 In a preferred embodiment, the high dielectric constant material is formed by atomic layer deposition. 所述二极管优选地由与硅化物接触而结晶的沉积的低缺陷半导体材料形成。 The diode is preferably formed of a low-defect crystal semiconductor material being deposited in contact with the silicide. 可在晶片衬底上方的经堆叠存储器层级中形成此类单元的单片三维存储器阵列。 Monolithic three dimensional memory array of such cells may be formed in the stacked memory hierarchy above the wafer substrate.

Description

邻近于硅化物而结晶的与介电反熔丝串联的PH-N 二极管及其形成方法 Crystallized adjacent to a silicide and the dielectric antifuse in series with PH-N diode and method of forming

[0001] 相关串请案交叉参考 [0001] CROSS-REFERENCE please dependent crosstalk

[0002] 此申请案主张2006年11月15日申请的标题为“邻近于硅化物而结晶的与介电反溶丝串联的P-1-N 二极管(P-1-N Diode Crystallized Adjacent to a Silicide inSeries witha Dielectric Antifuse) ”的美国专利申请案第11/560,289 号以及2006 年11月15日申请的标题为“用于制作邻近于硅化物而结晶的与介电反熔丝串联的P-1-N二极管的方法(Method for Making a P-1-N Diode Crystallized Adjacent to a Silicide inSeries with aDielectric Antifuse,) ”的美国专利申请案第11/560,283号的优先权,所述申请案的每一者均出于所有目的以全文引用的方式并入本文中。 [0002] This application claims priority of November 15, 2006, filed, entitled "adjacent to the silicide crystalline dielectric anti-solvent wire serial P-1-N diode (P-1-N Diode Crystallized Adjacent to a silicide inSeries witha dielectric antifuse) "title of US patent application Ser. No. 11 / 560,289 and 15 November 2006, the application is" used to make adjacent to the silicide crystalline dielectric antifuse series P -1-N diode method (method for Making a P-1-N diode Crystallized Adjacent to a Silicide inSeries with aDielectric Antifuse,) "U.S. Patent application No. 11 / 560,283 priority application the each caught for all purposes entirety by reference herein.

背景技术 Background technique

[0003] 本发明涉及包括电串联地形成于导体之间的二极管及介电破裂反熔丝的非易失性存储器单元。 [0003] The present invention relates to a series electrical connection is formed in the nonvolatile memory cell diode between the conductor and dielectric rupture antifuse. 一般来说,其有利于将编程此存储器单元所需的电压降到最低。 Generally speaking, it is conducive to the voltage required to program the memory cell to a minimum.

发明内容 SUMMARY

[0004] 本发明由以上权利要求书界定,且此段落中任何内容均不应视为对那些权利要求的限制。 [0004] The present invention is defined by the following claims, and nothing in this paragraph shall be construed as a limitation on those claims. 一般来说,本发明针对非易失性存储器单元,其包括由高介电常数反熔丝材料形成的介电破裂反熔丝及由低电阻率半导体材料形成的半导体二极管。 In general, the present invention is directed to a nonvolatile memory cell comprising a dielectric formed of a high dielectric constant material antifuse rupture antifuse and semiconductor diode formed of a low resistivity semiconductor material.

[0005] 本发明的第一方面提供一种用于形成及编程非易失性存储器单元的方法,所述方法包含:形成相连式P-1-n 二极管,所述相连式p-1-n 二极管包含沉积的半导体材料;形成与所述沉积的半导体材料接触的硅化物、硅化物-锗化物、或锗化物层;使与所述硅化物、硅化物-锗化物、或锗化物层接触的所述沉积的半导体材料结晶;形成具有大于8的介电常数的介电材料层;及使所述介电材料层的一部分经受介电击穿,其中所述存储器单元包含所述相连式P-1-n 二极管及所·述介电材料层。 Method [0005] providing a first aspect of the present invention and a method of forming a nonvolatile memory cell for programming, said method comprising: forming connected formula P-1-n diode, is connected to the p-1-n of formula diode comprising a deposited semiconductor material; forming a silicide in contact with the semiconductor material of the deposited silicide - germanide or germanide layer; so that the silicide, a silicide - layer contacting germanide or germanide of the deposition of the semiconductor crystalline material; forming a layer of dielectric material having a dielectric constant greater than 8; and the portion of the dielectric material layer is subjected to dielectric breakdown, wherein the unit comprises a memory connected to the formula P- 1-n-diodes and the said dielectric material layer.

[0006] 本发明的另一方面提供一种第一存储器层级,所述第一存储器层级包含:在衬底上方形成的多个第一大致平行大致共面的导体;在所述第一导体上方形成的多个第二大致平行大致共面的导体;包含半导体材料的多个垂直定向的相连式P-1-n 二极管,所述半导体材料邻近于硅化物、硅化物-锗化物、或锗化物层而结晶;由具有大于约8的介电常数的介电材料形成的多个介电破裂反熔丝,其中所述相连式P-1-n 二极管的每一者安置于所述第一导体中的一者与所述第二导体中的一者之间,且其中所述介电破裂反熔丝的每一者安置于所述第一导体中的一者与所述相连式P-1-n 二极管中的一者之间或所述第二导体中的一者与所述相连式P-1-n 二极管中的一者之间;及多个存储器单元,每一存储器单元包含所述相连式P-1-n 二极管中的一者及所述介电破裂反熔丝中的一者 [0006] Another aspect of the present invention, there is provided a first memory level, the first memory level comprising: a first plurality of substantially parallel formed over the substrate substantially coplanar conductors; above said first conductor forming a second plurality of substantially parallel substantially coplanar conductors; a plurality of vertically oriented connected formula P-1-n diode including a semiconductor material, the semiconductor material adjacent to the silicide, silicides - germanide or germanide crystallized layer; a plurality of dielectric formed of a dielectric material having a dielectric constant greater than about 8 to rupture antifuse, wherein each of the coupled formula P-1-n diode is disposed in the first conductor between each of one and the second conductor of one, and wherein the dielectric rupture antifuse is disposed in the first conductor is connected to said one of formula P-1 between the second conductor is connected to said one of formula P-1-n diodes one diode between -n or one; and a plurality of memory cells, each memory cell comprising a coupled formula P-1-n diode of one and the dielectric rupture antifuse of one .

[0007] 本发明的优选实施例提供一种形成于衬底上方的单片三维存储器阵列,所述单片三维存储器阵列包含:a)单片地形成于所述衬底上方的第一存储器层级,所述第一存储器层级包含:i)沿第一方向延伸的多个第一大致平行大致共面的导体;ii)沿不同于所述第一方向的第二方向延伸的多个第二大致平行大致共面的导体,所述第二导体在所述第一导体上方;iii)由沉积的半导体材料形成的多个垂直定向的相连式p-1-n 二极管,所述半导体材料邻近于硅化物、硅化物-锗化物、或锗化物层而结晶,每一二极管垂直安置于所述第一导体中的一者与所述第二导体中的一者之间;iv)由具有大于8的介电常数的介电材料形成的多个介电破裂反熔丝;及4多个存储器单元,每一存储器单元包含串联布置的所述二极管中的一者及所述介电破裂反熔丝中的一者;及13)单片地形成于 [0007] Preferred embodiments of the present invention provides a method of forming a monolithic three dimensional memory array above a substrate, a monolithic three dimensional memory array comprising: a) monolithically formed above the first memory level of the substrate , the first memory level comprising: i) a first plurality of substantially parallel extending in a first direction substantially coplanar conductors; a second plurality of substantially ii) a second direction different from the first direction extending parallel substantially coplanar conductors, the second conductors above the first conductors; a plurality of vertically oriented connected formula p-1-n diode is formed of a semiconductor material deposited III), the semiconductor material adjacent to the silicide silicides - germanide or germanide layer is crystallized, each diode vertically disposed between said first conductor and said second conductor is one of one; IV) having from greater than 8 a plurality of dielectric permittivity of the dielectric material forming the rupture antifuse; 4 and a plurality of memory cells, each memory cell comprising a diode arranged in series in one and the dielectric rupture antifuse one; and 13) monolithically formed in 述第一存储器层级上方的第二存储器层级。 Said second memory level above the first memory level.

[0008] 本发明的再一方面提供一种装置,所述装置包含:包含半导体材料的相连式P-1-n 二极管;与所述相连式p-1-n 二极管的半导体材料接触的硅化物或硅化物-锗化物层;及包含介电材料的介电破裂反熔丝,所述介电材料具有8或更大的介电常数,其中所述相连式P-1-n 二极管及所述介电破裂反熔丝电串联地布置于第一导体与第二导体之间。 [0008] another aspect of the present invention to provide an apparatus, said apparatus comprising: coupled to formula P-1-n diode comprising a semiconductor material; a silicide with the semiconductor material is connected to the formula p-1-n diode contact or a silicide - germanide layer; and a dielectric material comprising a dielectric rupture antifuse, said dielectric material having a dielectric constant of 8 or greater, wherein said formula is connected to P-1-n diode and the the dielectric rupture antifuse are arranged in series electrically between the first and second conductors.

[0009] 本发明的又一方面提供一种用于形成及编程非易失性存储器单元的方法,所述方法包含:形成相连式P-1-n 二极管,所述相连式p-1-n 二极管包含沉积的半导体材料;形成与所述沉积的半导体材料接触的硅化物、硅化物-锗化物、或锗化物层;使与所述硅化物、硅化物-锗化物、或锗化物层接触的所述沉积的半导体材料结晶;形成具有大于8的介电常数的介电材料层;及使所述介电材料层的一部分经受介电击穿,其中所述存储器单元包含所述相连式P-1-n 二极管及所述介电材料层。 Method [0009] In another aspect of the present invention and a method of forming a nonvolatile memory cell for programming, said method comprising: forming connected formula P-1-n diode, is connected to the p-1-n of formula diode comprising a deposited semiconductor material; forming a silicide in contact with the semiconductor material of the deposited silicide - germanide or germanide layer; so that the silicide, a silicide - layer contacting germanide or germanide of the deposition of the semiconductor crystalline material; forming a layer of dielectric material having a dielectric constant greater than 8; and the portion of the dielectric material layer is subjected to dielectric breakdown, wherein the unit comprises a memory connected to the formula P- 1-n diode and the dielectric material layer.

[0010] 本发明的额外方面提供一种用于在衬底上方单片地形成第一存储器层级的方法,所述方法包含:在所述衬底上方形成多个第一大致平行大致共面的导体,所述第一导体沿第一方向延伸;在所述第一导体上方形成多个垂直定向的相连式P-1-n 二极管,所述相连式p-1-n 二极管包含与硅化物、硅化物-锗化物、或锗化物层接触而结晶的半导体材料;形成多个第二大致平行大致共面的导体,所述第二导体在所述相连式P-1-n 二极管上方,所述第二导体沿不同于所述第一方向的第二方向延伸,每一相连式P-1-n 二极管垂直安置于所述第一导体中的一者与所述第二导体中的一者之间;及形成多个介电破裂反熔丝,每一介电破裂反熔丝安置于所述相连式P-1-n 二极管中的一者与所述第一导体中的一者之间或所述相连式P-1-n 二极管中的一者与所述第二导体中的一者之间, [0010] Additional aspects of the present invention to provide a substrate for the above method of monolithically forming a first memory level, the method comprising: forming a first plurality of substantially parallel over the substrate in a substantially coplanar conductor, the first conductor extending in a first direction; forming a plurality of vertically oriented connected formula P-1-n diode above the first conductor, connected to the p-1-n type diode comprising a silicide, suicide - germanide or germanide layer of semiconductor material is crystallized in contact; a second plurality of substantially parallel conductors forming a substantially coplanar, said second conductor P-1-n diode is connected to the above, the a second conductor extending in a second direction different from the first direction, each connected to the formula P-1-n diode disposed perpendicular to said first conductor and said second conductor is one of one of the between; and forming a plurality of dielectric rupture antifuse, each dielectric rupture antifuse is disposed between the coupled formula P-1-n diode of one of said first conductor of one or the connected between said formula P-1-n diode of one and the second conductor of one, 中所述介电破裂反熔丝包含介电材料, 所述介电材料具有大于约8的介电常数。 Said dielectric rupture antifuse comprising a dielectric material, the dielectric material having a dielectric constant of greater than about 8.

[0011] 本发明的优选实施例提供一种用于在衬底上方形成单片三维存储器阵列的方法,所述方法包含:a)在所述衬底上方单片地形成第一存储器层级,所述第一存储器层级通过包含以下步骤的方法形成:i)形成沿第一方向延伸的多个第一大致平行大致共面的导体; Preferred [0011] embodiment of the present invention provides a method for forming a monolithic three dimensional memory array over the substrate, the method comprising: a) forming a first memory level monolithically in the substrate above, the forming a first plurality of substantially parallel conductors extending in a first direction substantially coplanar i);: said first memory level formed by a method comprising the steps of

ii)形成沿不同于所述第一方向的第二方向延伸的多个第二大致平行大致共面的导体,所述第二导体在所述第一导体上方;iii)形成由沉积的半导体材料形成的多个垂直定向的相连式P-1-n 二极管,所述沉积的半导体材料与硅化物、硅化物-锗化物、或锗化物层接触而结晶,每一二极管垂直布置于所述第一导体中的一者与所述第二导体中的一者之间;iv)形成由具有大于8的介电常数的介电材料形成的多个介电破裂反熔丝;及0形成多个存储器单元,每一存储器单元包含串联布置的所述二极管中的一者及所述介电破裂反熔丝中的一者;及13)在所述第一存储器层级上方单片地形成第二存储器层级。 ii) forming a plurality of second conductors extending substantially parallel to a second direction different from the first direction is substantially coplanar, said second conductor is above the first conductor; forming a semiconductor material deposited iii) connected to a plurality of vertically oriented formula P-1-n diode formed, the deposited semiconductor material and silicides, silicide - germanide or germanide layer contacting crystallization, each disposed perpendicular to said first diode between one of the conductors and the second conductor of one; IV) forming a plurality of dielectric formed of a dielectric material having a dielectric constant greater than 8 rupture antifuse; and forming a plurality of memory 0 the diode cell, each memory cell comprises a series arrangement of one and the dielectric rupture antifuse of one; and 13) a second memory level formed in said first memory level monolithically above .

[0012] 本文中描述的本发明的各方面及实施例的每一者可单独地使用或者可彼此组合地使用。 [0012] Each of the various aspects and embodiments of the present invention described herein may be used alone or in combination with each other may be used. [0013] 现在,将参照附图描述这些优选的方面及实施例。 [0013] Now, reference will be described with reference to these preferred aspects and embodiments.

附图说明 BRIEF DESCRIPTION

[0014] 图1是美国专利第6,952,030号的存储器单元的透视图。 [0014] FIG. 1 is a perspective view of a memory cell U.S. Patent No. 6,952,030 to.

[0015] 图2是包含若干存储器单元的存储器层级的透视图。 [0015] FIG. 2 is a perspective view of the memory hierarchy comprising a plurality of memory cells.

[0016] 图3是电路图,其显示用于编程选定单元S同时避免无意中编程交叉点阵列中的半选定单元H和F及未选单元U的偏置方案。 [0016] FIG. 3 is a circuit diagram showing a selected cell for programming S while avoiding inadvertently programmed cross-point array and half-selected cells H and F unit U unselected bias scheme.

[0017] 图4是电路图,其显示交叉点阵列中在减小的编程电压下选定单元S、半选定单元H和F及未选单元U上的电压。 [0017] FIG. 4 is a circuit diagram showing a cross point array selected cell S under reduced programming voltage, the voltage across the cell is selected from H and F unit U and the non-half-selected.

[0018] 图5是根据本发明的优选实施例形成的存储器单元的截面图。 [0018] FIG. 5 is a sectional view of a memory cell formed according to a preferred embodiment of the present invention.

[0019] 图6是根据本发明的替代实施例形成的存储器单元的截面图。 [0019] FIG. 6 is a sectional view of a memory cell formed in accordance with an alternative embodiment of the present invention.

[0020] 图7是根据本发明另一替代实施例形成的存储器单元的截面图。 [0020] FIG. 7 is a sectional view of an alternative embodiment of a memory cell formed in accordance with another embodiment of the present invention.

[0021] 图8a_8c是显示在形成根据本发明的优选实施例形成的单片三维存储器阵列的第一存储器层级中的各阶段的截面图。 [0021] FIG 8a_8c is a cross-sectional view is formed in each stage of the first memory level of a monolithic three dimensional memory array formed in accordance with a preferred embodiment of the present invention.

具体实施方式 Detailed ways

[0022] 图1显示赫尔内(Herner)等人的美国专利第6,952,030号“高密度三维存储器单兀(High-density three-dimensional memory cell) ”中描述的存储器单兀的实施例,后文中将此专利称为'030专利。 [0022] FIG. 1 shows an embodiment of the memory unit as described in Wu, "High-density three-dimensional memory unit Wu (High-density three-dimensional memory cell)" the Hull (Herner) et al., U.S. Patent No. 6,952,030 embodiment, this hereinafter referred to as Patent '030 patent. 在此非易失性存储器单元中,柱300 (包含二极管302及介电破裂反熔丝118)电串联地布置于顶部导体400与底部导体200之间。 The nonvolatile memory cell, the post 300 (comprising diodes 302 and dielectric rupture antifuse 118) electrically arranged in series in the top conductor 400 and bottom conductor 200. 在此存储器单元的初始状态中,当在顶部导体400与底部导体200之间施加读取电压时,极小的电流在所述顶部导体400与所述底部导体200之间流动。 In the initial state of the memory cell, when a read voltage is applied between top conductor 400 and bottom conductor 200, a very small current flows between the conductor 400 and the bottom conductor 200 at the top. 持久地施加相对大的编程电流改变图1的存储器单元,使得在编程之后,在同一读取电压下更多电流流动。 Relatively large memory cell programming current is applied to change permanently in FIG. 1, such that after programming, the read current flows more under the same voltage. 同一所施加读取电压下的此电流差允许将经编程单元与未编程单元区分开;例如,将数据“0”与数据“I”区分开。 This same current is applied at a read voltage difference allows to distinguish the unprogrammed and programmed cell cell region; for example, to separate the data "0" and data "I" region.

[0023] 如在赫尔内等人于2004年9月29日申请的美国专利申请案第10/955,549号“不包括具有高及低阻抗状态的介电反熔丝的非易失性存储器单元(NonvolatileMemoryCell Without a Dielectric Antifuse Having High—and Low-1mpedanceStates) ”且后文中将此专利申请案称为'549申请案中,且在赫尔内等人于2005年6月8日申请的美国专利申请案第11/148,530号“在多晶半导体材料中以升序操作的非易失性存储器单兀(Nonvolatile Memory Cell Operating by Increasing Order inPolycrystallineSemiconductor Material,) ”且后文中将此专利申请案称为'530申请案中(所述两个申请案由本发明的受让人拥有且以引用的方式并入本文中)的详细描述,二极管302由在初始未编程装置中处于相对高电阻率状态的半导体材料形成。 [0023] The dielectric antifuse does not include a nonvolatile memory cell having a high and a low impedance state in the U.S. Patent Application Hull et al, filed September 29, 2004 Serial No. 10 / 955,549 " (NonvolatileMemoryCell Without a Dielectric Antifuse Having High-and Low-1mpedanceStates) "and later in this patent application, known as the '549 application, and the application on June 8, 2005 in Hull, et al., US Patent application No. 11 / 148,530 "in a polycrystalline semiconductor material to a single non-volatile memory Wu ascending operation (nonvolatile memory Cell operating by Increasing order inPolycrystallineSemiconductor material,)" and hereinafter referred to as this patent application ' in application 530 (two assignee of the present invention has application for the cause of action, and is incorporated by reference herein) is described in detail, the diode 302 is a semiconductor material of a relatively high-resistivity state in an initial unprogrammed device form. 在二极管302上施加编程电压将半导体材料从高电阻率状态改变为较低电阻率状态。 Applying a programming voltage across the semiconductor material of the diode 302 is changed from the high-resistivity state to a lower resistivity state.

[0024] 在类似图1中所示单元的单元中,编程电压必须执行两种任务。 [0024] In the unit cell shown in FIG. 1 is similar to the program voltage must perform two tasks. 所述编程电压必须将二极管302的半导体材料从高电阻率状态转换为低电阻率状态,且还必须致使介电破裂反熔丝118的介电材料经历介电击穿,在介电击穿期间永久地形成穿过介电破裂反熔丝118的至少一个传导路径。 The programming voltage must be the semiconductor material diode 302 is converted from a high resistivity state to a low resistivity state, and dielectric rupture must cause antifuse dielectric material 118 is subjected to dielectric breakdown, the dielectric breakdown during permanently formed through the dielectric rupture antifuse 118 of the at least one conductive path.

[0025] 图2显示布置于包含多个存储器单元的交叉点阵列中的类似图1的那些单元的单元的第一存储器层级的一部分。 [0025] Figure 2 shows a portion disposed in the first memory level unit comprises a plurality of cross-point array of memory cells is similar to Figure 1 of those units. 每一存储器单元包含安置于顶部导体400中的一者与底部导体200中的一者之间的柱300 (其包含图1中所示的二极管302及反熔丝118)。 Each memory cell comprises a pillar 300 between one of the conductors 200 disposed in the top 400 and bottom conductor one (which includes a diode shown in FIG. 1 118 302 and the anti-fuse). 顶部导体400在底部导体200上方且沿不同方向(优选地,垂直于底部导体200)延伸。 And 400 (at the bottom of the conductor 200 is preferably vertically) extending top conductor above the bottom conductor 200 in different directions. 两个、三个或更多个此类存储器层级可彼此上下垂直堆叠,以形成单片三维存储器阵列。 Two, three, or more such memory levels can be stacked vertically above one another, to form a monolithic three dimensional memory array.

[0026] 图3图解说明可用于编程类似图2中所示交叉点存储器阵列的交叉点存储器阵列中的存储器单元的偏置方案。 [0026] FIG. 3 illustrates a similar program may be used as shown in FIG. 2 cross-point memory array biasing scheme cross point memory array of the memory cell. 假设选定单元S将经受10伏的编程电压(此处供应的电压仅为实例)。 S is assumed that the selected cell is subjected to program voltage of 10 volts (supply voltage here are merely examples). 将选定位线BO设定为10伏且将选定字线WO设定为0伏,从而跨越选定单元S置放10伏。 The selected bit lines BO is set to 10 volts and the selected word line is set to 0 volts WO thereby placed across selected cell S 10 volts. 为避免无意中编程单元F(其与选定单元S共享位线B0),将未选字线Wl设定为9伏;因此单元F仅经受I伏,此低于二极管的接通电压。 To avoid inadvertent programming unit F (S cells which share the bit line B0 is selected), the unselected word line Wl is set to 9 volts; thus only subjected unit F V I, this is lower than the ON voltage of the diode. 类似地,将未选位线BI设定为I伏;因此单元H(其与选定单元S共享字线W0)仅经受I伏。 Similarly, the unselected bit line is set to I BI volts; thus means H (S shared with the selected cell word line W0) I only subjected volts. 未选单元U(其不与选定单元S共享字线或位线)经受-8伏。 Unselected cells U (unit S which is not shared with the selected word line or bit line) is subjected to -8 volts. 注意,在此简化图中,显示仅一个未选位线BI及仅一个未选字线W1。 Note that in this simplified figure, shows only one unselected bit line and only one BI unselected word lines W1. 现实中,将存在许多未选字线及未选位线。 In reality, there will be many unselected word lines and unselected bit lines. 具有N个位线及M个字线的阵列将包括N-1个F单元、M-1个H单元以及极大数量(N-1)* (M-1)的U单元。 Array having M and N bit lines of the word lines comprises units of N-1 F, M-1, and a maximum number of H-cell (N-1) * (M-1) U-section.

[0027] 所述U单元的每一者中的二极管在电压低于所述二极管的击穿电压时处在反向偏置下,从而使流过此单元的电流降到最低。 The [0027] Each diode unit U is under the reverse bias voltage lower than the breakdown voltage of the diode, so that the current flowing through the unit to a minimum. (二极管不对称地传导电流,从而在一个方向上比在另一方向上更容易地传导电流。)然而,将不可避免地存在一些反向泄露电流,且由于大数量的U单元,因此编程选定单元期间的反向泄露电流可浪费显著量的电力。 (Asymmetrically diode conducts current, so than in the other direction more easily conduct current in one direction.) However, there will inevitably be some of the reverse leakage current, and due to the large number of U cells, thus programming the selected the leakage current during the reverse unit to waste a significant amount of power. 在编程选定单元S期间,已编程的H单元及F单元上的正向电流尽管小但还是类似地浪费电力。 During programming a selected cell S, the forward current programmed H F unit cell and smaller but still similarly although wasteful power consumption. 高编程电压本身通常难以产生。 High programming voltage itself is generally difficult to generate. 出于所有这些原因,需要使编程此交叉点存储器阵列中的选定存储器单元所需的电脉冲的量值降到最低。 For all these reasons, it is necessary to program the magnitude of the required cross-point memory array selected memory cell to minimize the electrical pulses.

[0028] 特征大小是可通过光刻工艺形成的最小特征。 [0028] feature is the smallest feature size that can be formed by a photolithography process. 注意,对于水平定向的装置(例如,晶体管),一般来说,随着特征大小降低,操作所述装置所需的电压也降低。 Note that, means for horizontally oriented (e.g., transistors), generally speaking, as the feature sizes decrease, the voltage required for operation of the apparatus is reduced. 然而,在图1的存储器单元中,由于存储器单元的垂直定向,因此一般来说变换二极管的半导体材料及使反熔丝破裂所需的电脉冲的量值不随着特征大小降低。 However, in the memory cell of FIG. 1, due to the vertical orientation of the memory cell, thus converting semiconductor material in general, and anti-fuse diode break electrical pulse magnitude is not required with feature sizes decrease.

[0029] 在'510申请案中,将介电破裂反熔丝与由半导体材料(例如,硅)形成的半导体二极管配成对,其中所述二极管的半导体材料处于其形成时的低电阻率状态,且无需转换。 [0029] In the '510 application, the dielectric rupture antifuse is formed of a semiconductor diode with a semiconductor material (e.g., silicon) are paired, wherein the semiconductor material of the diode in a low resistivity state is formed and without conversion.

[0030] ,030专利及'549申请案的二极管是通过以下步骤形成的:沉积半导体材料,例如处在无定形状态的娃,接着执行热退火以使娃结晶,形成多晶娃(polycrystallinesilicon)或多晶娃(polysilicon) 二极管。 [0030], 030 patent and '549 application is a diode formed by the steps of: depositing a semiconductor material, such as baby in an amorphous state, and then thermal annealing is performed to make the baby crystallized to form a polycrystalline Wa (polycrystallinesilicon) or baby polycrystalline (polysilicon) diode. 如'530申请案中所述,当沉积的无定形娃唯独与所述沉积的无定形硅与之具有高晶格失配的材料(例如,二氧化硅及氮化钛)接触而结晶时,多晶硅形成有高数量的晶体缺陷,从而致使其成为高电阻率。 As described in '530 application, where the deposition of amorphous silicon and the amorphous baby except the deposited with a material having high lattice mismatch (e.g., silica and titanium nitride) contact crystalline , polysilicon is formed with a high number of crystal defects, causing it to become a high resistivity. 通过此高缺陷多晶硅施加编程脉冲显而易见地改变所述多晶硅,致使其成为较低电阻率。 This high defect polysilicon programming pulse is applied to change the apparent polysilicon, so that it becomes lower resistivity.

[0031] 然而,已发现当沉积的无定形硅与适当的硅化物(例如,硅化钛或硅化钴)层接触而结晶时,所得的经结晶硅的质量高得多,缺陷更少,且具有低得多的电阻率。 [0031] However, it has been found that when amorphous silicon is deposited with a suitable silicide (e.g., titanium silicide or cobalt silicide) layer in contact with the crystal, the resulting mass crystallized silicon is much higher, fewer defects, and has much lower resistivity. 硅化钛或硅化钴的晶格间距非常接近于硅的晶格间距,且据信无定形硅与适当的硅化物层接触而以有利的定向结晶时,所述硅化物为硅的晶体生长提供模板,从而使缺陷的形成降到最低。 Lattice spacing of titanium suicide or cobalt suicide is very close to the lattice spacing of silicon, and it is believed that non-contact with a suitable amorphous silicon layer while a silicide advantageously oriented crystallization, the silicide provides a template for crystal growth of silicon form, so that the defects to a minimum. 不同于仅邻近于高缺陷硅与之具有高晶格失配的材料结晶的高缺陷硅,施加大电脉冲不会可观地改变与硅化物层接触而结晶的此低缺陷、低电阻率硅的电阻率。 Unlike high defect only adjacent to the silicon with a high defect having a high silicon lattice mismatched crystalline material, applying a large electric pulse does not appreciably change this low defect crystalline silicide layer in contact with a low resistivity silicon resistivity.

[0032] 通过将介电破裂反熔丝与此低缺陷、低电阻率二极管配成对,可形成编程电压仅需足以使介电破裂反熔丝破裂的存储器单元;二极管由在其初始状态已经是低电阻率且无需遭受高电阻率到低电阻率转换的半导体材料形成。 [0032] By a dielectric rupture antifuse this low defect, low-resistivity diode paired to form a programming voltage may be only sufficient to rupture the dielectric rupture anti-fuse memory cell; already in its initial state by the diode It is subjected to a low resistivity and no high resistivity to low resistivity semiconductor material forming conversion.

[0033] 在'510申请案的实施例中,将低缺陷二极管与由常规介电材料(二氧化硅)形成的介电破裂反熔丝配成对。 [0033] In the '510 application in the embodiment, the low-defect diode and the dielectric formed by the conventional dielectric material (silicon dioxide) rupture antifuse paired right. 此装置中的介电破裂反熔丝必须足够厚以实现可靠绝缘,因此需要相对大的编程电压。 This device a dielectric rupture antifuse must be thick enough for reliable insulation, and therefore requires a relatively large programming voltage. 可通过减小二氧化硅反熔丝的厚度来减小此编程电压。 This programming voltage can be reduced by reducing the thickness of the antifuse silica. 然而,当二氧化硅反熔丝变得较薄时,所述反熔丝变得更容易有缺陷,此将允许不想要的泄露电流。 However, when the silica antifuse becomes thinner, the easier antifuse defective, this will allow the undesired leakage current.

[0034] 所述二氧化硅层(其充当反熔丝)通常是热生长的。 [0034] The silicon dioxide layer (which acts as an anti-fuse) is usually thermally grown. 可通过使反熔丝在较高温度(例如,1000摄氏度)下生长来改善反熔丝的质量,并降低缺陷。 By reacting at a higher temperature (e.g., 1000 degrees Celsius) grown under the antifuse to improve quality, and reduce defects antifuse. 然而,高温具有其它缺点,导致掺杂剂在二极管中且在形成于存储器层级下面的CMOS控制电路中不想要的扩散,从而损坏且可能毁坏所述装置。 However, temperature has other drawbacks, resulting in the diode and the dopant in the diffusion circuit formed unwanted CMOS level below the memory control, such that damage to the device and may damage.

[0035] 材料具有特性介电常数k。 [0035] The material having a dielectric constant characteristic k. 材料的介电常数描述其作为绝缘体的行为。 The dielectric constant of the insulator material is described as behavior. 好的绝缘体(例如,以常规方式形成的二氧化硅)具有3.9的低介电常数。 Good insulator (e.g., silicon dioxide formed in a conventional manner) having a low dielectric constant of 3.9. 真空被定义为具有I的最低可能介电常数。 Vacuum may be defined to have the lowest dielectric constant of I. 许多材料(例如,包括HfO2及Al2O3)被视为电介质,但具有的介电常数高于二氧化硅的介电常数。 Many materials (e.g., including HfO2 and Al2O3) is regarded as a dielectric, the dielectric having a dielectric constant higher than silicon dioxide.

[0036] 充当介电破裂反熔丝的较高_k材料(例如,HfO2或Al2O3)层可厚于在质量上差别不大同时具有相同电行为的较低_k材料(例如,二氧化硅)层。 [0036] _k acts as a high dielectric rupture antifuse material (e.g., HfO2, or Al2O3) layer may be thicker than the little difference in quality while having the same electrical behavior lower _k material (e.g., silicon dioxide )Floor.

[0037] 麦克珀森(McPherson)等人在2002 IEDM学报第633-636页的“建议的介电击穿与介电常数之间的通用关系(Proposed universal relationship betweendielectricbreakdow n and dielectric constant,) ” 中演不了具有较高介电常数k 的材料在比较低介电常数材料低的电场下遭受介电击穿。 [0037] Maikeposen (McPherson) and others in the "universal relationship between the dielectric constant and dielectric breakdown proposed (Proposed universal relationship betweendielectricbreakdow n and dielectric constant,)" 2002 IEDM Journal of 633-636 pages of not play a material having a higher dielectric constant k suffer dielectric breakdown at a low electric field is a relatively low dielectric constant material. 出于早期已描述的原因,需要减小存储器阵列中的编程电压。 For reasons described earlier, it is necessary to reduce the programming voltage of the memory array. 在本发明中,将由邻近于硅化物而结晶的低缺陷沉积半导体材料形成的二极管与由具有大于约8的介电常数k的高-k材料形成的介电破裂反熔丝配成对。 In the present invention, will be adjacent to the silicide deposition of low-defect crystal semiconductor diode is formed of the dielectric material is formed of a high -k material having a dielectric constant k greater than about 8 to rupture antifuse paired right. 术语“沉积的半导体材料”是指已沉积的半导体材料(例如,硅、锗、或硅-锗合金),且排除其上方可构造所述装置的单晶晶片衬底。 The term "deposited semiconductor material" refers to a semiconductor material has been deposited (e.g., silicon, germanium, or a silicon - germanium alloy), and excluding single crystal wafer substrate on which the device before configuration. 编程单元所需的电压仅是通过使反熔丝经受介电击穿而使所述反熔丝破裂所需的电压。 Only the cell voltage required to program antifuse is subjected to a voltage by the breakdown of the dielectric rupture antifuse required. 形成高_k材料的反熔丝是用于在以低泄漏电流进行编程之前在编程之后维持高可靠性的反熔丝的同时减小编程电压。 Forming a high _k for the antifuse material while maintaining a high reliability after programming the antifuse programming prior to programming voltage low leakage current reduction.

[0038] 注意,已对高_k介电材料进行了研究以供在晶体管的闸极氧化物中使用,因为高-k介电材料可比闸极氧化物(即,二氧化硅)制作得更薄同时具有相同或更好的电容。 [0038] Note that, _k has high dielectric materials have been studied for use in a transistor gate oxide is used, because of the high -k dielectric material than the gate oxide (i.e., silica) produced more thin while having the same or better capacitance. 然而,这些闸极氧化物在晶体管中起到不同于此处所述反熔丝的作用。 However, the gate oxide is different from the functions described herein in the anti-fuse transistor. 并不打算使这些闸极氧化物在所述装置的寿命中的任一点时经历介电击穿。 Does not intend any of these gate oxide over the life of the device is that when subjected to dielectric breakdown.

[0039] 在优选实施例中,使用原子层沉积(ALD)来形成高_k材料的介电破裂反熔丝。 [0039] In a preferred embodiment, to form a high dielectric rupture antifuse _k material using atomic layer deposition (ALD). ALD技术最近取得的进步已允许形成极薄且质量极高的高-k材料层,例如,50、30、20、或10埃或更少。 Progress has been made recently ALD technique allows the formation of high quality thin layer of material and high -k, e.g., 50,30,20, or 10 angstroms or less. 此极薄层具有如此高的质量而使得泄漏电流在可接受的低程度,且此薄层需要较低的击穿电压。 This very thin layer has so high quality so that the leakage current at an acceptable low level, and the thin layer requires a lower breakdown voltage.

[0040] 麦克珀森等人描述较高_k电介质具有以下额外优点:所述高_k电介质往往展现比较低-k电介质(例如,二氧化硅)更均匀的击穿行为。 [0040] _k Maikeposen et al describes high dielectric has the following additional advantage: _k the high dielectric breakdown tends to exhibit a more uniform behavior of low -k dielectrics (e.g., silica). 当存储器阵列的介电破裂反熔丝跨越宽范围的编程电压而破裂时,所述编程电压必须足够高以使反熔丝在分布的高端破裂,即使较低电压将满足阵列中的多数存储器单元。 When the memory array dielectric rupture antifuse programming voltage across a wide range of rupture, the programming voltage must be high enough to cause rupture antifuse high profile, most of the memory cell array even when a lower voltage will meet . 较紧密的分布允许进一步降低编程电压。 Tighter distribution allows to further reduce the programming voltage. [0041] 许多高-k电介质可通过各种沉积工艺(包括ALD)在相对低的温度下形成。 [0041] Many high -k dielectrics may be formed at a relatively low temperature by various deposition processes (including ALD). 一般来说,减小处理温度对制作复杂半导体装置总是有利的,因为此可使掺杂剂扩散、剥落等降到最低。 Generally, the processing temperature for reducing the complexity of making a semiconductor device is always advantageous, since this allows dopant diffusion, minimizing peeling.

[0042] 二极管不对称地传导电流,从而在正向偏置下比在反向偏置下更容易传导。 [0042] asymmetrically diode conducts current, so that under forward bias than the reverse bias is more easily conducted. 反向泄漏电流,即在反向偏置下流动的电流是不需要的。 Reverse leakage current, i.e. the current flowing in the reverse bias is not required. 反向泄漏电流随着二极管上减小的负电压而超线性地减小。 Reverse leakage current decreases as the voltage on the negative diode decreases linearly over. 例如,如在本发明中,在具有由低电阻率半导体材料形成的0.15微米特征大小的二极管中,当二极管在-7伏下时,反向泄漏电流为-7.5X 10_n安。 For example, as in the present invention, a diode having a 0.15 micron feature size formed of a low resistivity of the semiconductor material, -7 volts when the diode reverse leakage current -7.5X 10_n Ann. 当电压为-5.5伏时,反向泄漏电流大致减小到-3.0X 10_n安。 When the voltage is -5.5 volts, reverse leakage current is substantially reduced to -3.0X 10_n Ann. 在-4.5伏电压下,反向泄漏电流减小到1.6X IO-11A安。 At -4.5 volts, reverse leakage current is reduced to 1.6X IO-11A Ann. 在图2中所描绘的交叉点阵列中,恢复编程选定单元S所需的较低电压会跨越未选单元U产生较低负电压,例如,翻到图4,假设选定单元S上的编程电压仅需为5.4伏。 A cross point array depicted in FIG. 2, the lower voltage required to restore the selected program unit S across the unselected cells U will produce a lower negative voltage, e.g., turn to FIG. 4, assume the selected cell S programming voltage is only 5.4 volts. 在跨越选定单元S为5.4伏的情况下,选定位线BO上的电压为5伏,选定字线WO处在0伏。 In the case where the selected cell S across 5.4 volts, the voltage on the selected bit line BO is 5 volts, the selected word line in WO 0 volts. 如果未选位线BI设定为I伏且未选字线Wl设定为4.4伏,那么单元H和F两者均经受I伏。 If the unselected bit line is set to BI I V and the unselected word line Wl is set to 4.4 volts, the cell is subjected to both the H and F I V. 未选单元U经受-3.4伏,此显著地低于图3的实例中的-8伏。 Unselected cells U is subjected to -3.4 volts, which is significantly lower than in the example of FIG. 3 -8 volts.

[0043] 在迄今所描述的单片存储器阵列中,一般来说优选地使用硅来形成二极管。 [0043] In a monolithic memory array described so far, in general preferably formed using a silicon diode. 锗具有比硅小的带隙,且已发现由硅及锗的合金形成的二极管具有比纯硅二极管高的反向泄漏电流。 Ge has a smaller band gap than silicon, and have found that the diode formed of silicon and germanium alloy has a higher leakage current than that of pure silicon diode reverse. 泄漏电流随着锗的份数而增加。 Leakage current increases with the number of copies of germanium. 在交叉点存储器阵列中,由于未选单元U仅处在-3.4伏,因此泄漏电流将明显较低,从而减轻此缺点。 In the cross-point memory array, since only the unselected cells U at -3.4 V, so the leakage current is significantly lower, so as to reduce this drawback. 如在赫尔内等人于2005年5月9日申请的美国专利申请案11/125,606 “在低温下制作的包含半导体二极管的高密度非易失性存储器阵列(High-Density Nonvolatile Memory Array Fabricated at LowTemperatureComprising Semiconductor Diodes,) ”中所描述,此申请案由本发明的受让人拥有且以引用的方式并入本文中并在后文中称为'606申请案,以常规方法沉积硅且使其结晶所需的温度通常不与铝及铜金属化(其不可容忍高温)兼容。 As Fabricated at the in U.S. Patent Application Hull et al, filed May 9, 2005 11 / 125,606, "produced at a low temperature high density non-volatile memory array (High-Density Nonvolatile Memory Array semiconductor diode comprising LowTemperatureComprising Semiconductor Diodes,) "as described in this application, the assignee of the present invention has a cause of action, and are incorporated herein by reference and hereinafter referred to as the '606 application, a conventional method for depositing silicon and the crystallized the required temperature is generally not compatible with aluminum metallization and copper (which is intolerable temperature). 如此申请案中所述,使用具有充足高锗含量的硅-锗二极管可使总的制作温度降低,从而允许使用这些低电阻率金属,改善装置性能。 Thus the application case, a silicon germanium content have a high enough - the germanium diode can reduce the total manufacturing temperature, allowing the use of these low-resistivity metal, improving device performance.

[0044] 图5显示根据本发明的优选实施例形成的存储器单元。 [0044] FIG. 5 shows a memory cell formed according to a preferred embodiment of the present invention. 底部导体200包括优选地为氮化钛的粘附层104及优选地为钨的传导层106。 Bottom conductors 200 preferably includes a titanium nitride adhesion layer 104 and the conductive layer is preferably 106 tungsten. 由高_k介电材料形成的介电破裂反熔丝Il8形成于底部导体200上方。 The dielectric is formed of a high dielectric material _k Il8 rupture antifuse 200 is formed above the bottom conductor. 例如为氮化钛的阻挡层110介于介电破裂反熔丝118与垂直定向的相连式P-1-n 二极管302之间。 For example, a titanium nitride barrier layer 110 interposed dielectric rupture antifuse 118 is connected to the vertical orientation of formula P-1-n diode 302 between. 在一些实施例中,可省略层110。 In some embodiments, layer 110 may be omitted. 柱300包括阻挡层110及二极管302。 Column 300 includes a barrier layer 110 and the diode 302. 硅化物层122 (优选地为硅化钴或硅化钛)是顶部导体400的一部分,顶部导体400进一步包括例如氮化钛层404及钨层406的传导层。 Silicide layer 122 (preferably cobalt silicide or titanium silicide) is part of the top conductor 400, 400 further comprises a top conductor layer 404 and a tungsten conductive layer 406 such as titanium nitride layer. (如将看到,硅化物仅形成在硅化物形成金属与二极管302的硅接触之处;层122的画有交叉阴影线的部分是未反应的金属,而非硅化物。)顶部导体400 (其显示为与下伏柱300稍微不对准)优选地为轨道形状,以延伸出图页的截面形式显示。 (As will be seen, the silicide formed only in the metal silicide is formed in contact with the diode 302 of silicon;. Metal layer 122 Videos cross-hatched portions of unreacted, rather than silicide) a top conductor 400 ( 300 which is shown as slightly misaligned with the underlying column) is preferably a rail shape, shown in cross section in FIG extending form page. 供在反熔丝118中使用的优选材料包括Hf02、Al2O3' ZrO2, Ti02、La2O3' Ta2O5' RuO2' ZrSiOx, AlSiOx,HfSiOx, HfAlOx, HfSiON, ZrSiAlOx,HfSiAlOx, HfSiAlON、及ZrSiAlON。 Preferred materials for use in the anti-fuse 118 includes Hf02, Al2O3 'ZrO2, Ti02, La2O3' Ta2O5 'RuO2' ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. 二极管302的硅优选地以无定形形式沉积,且接着使其结晶。 Silicon diodes 302 are preferably deposited in amorphous form and then crystallized. 在一些实施例中,使二极管302结晶,接着剥离硅化物122以使最终装置中不存在硅化物可是优选的。 In some embodiments, the crystallization of the diode 302, and then release the silicide 122 to make the silicide does not exist in the final device may be preferable. 可存在若干额外层(未显示),例如,阻挡层及粘附层;另一选择是,在一些实施例中可省略所包括的一些阻挡层。 Alternatively, in some embodiments, some of the barrier layers may be omitted comprising; a plurality of additional layers (not shown), e.g., a barrier layer and adhesive layers may be present.

[0045] 图6显示替代实施例。 [0045] Figure 6 shows an alternative embodiment. 底部导体200如同图5的实施例中那样形成。 As bottom conductors 200 are formed as in the embodiment of FIG. 5. 柱300包括阻挡层110(优选地为氮化钛)、相连式P-1-n 二极管302、硅化物层122、传导阻挡层123、高_k介电材料形成的介电破裂反熔丝118及传导阻挡层125。 Column 300 includes a barrier layer 110 (preferably titanium nitride), is connected to the formula P-1-n diode 302, silicide layer 122, conductive barrier layer 123, the dielectric material of high dielectric _k rupture antifuse 118 and a conductive barrier layer 125. 顶部导体400包括传导粘附层404 (优选地为氮化钛)及传导层406 (例如,钨)。 Top conductor 400 includes a conductive adhesive layer 404 (preferably titanium nitride), and the conductive layer 406 (e.g., tungsten).

[0046] 图7显示另一替代实施例。 [0046] Figure 7 shows another alternative embodiment. 底部导体200如同图5及6的实施例中那样形成。 As bottom conductors 200 are formed as in Example 5, and 6 in FIG. 柱300包括阻挡层110 (优选地为氮化钛)及相连式p-1-n 二极管302。 Column 300 includes a barrier layer 110 (preferably titanium nitride) and connected to the formula p-1-n diode 302. 短柱304(以不同的蚀刻步骤从柱300蚀刻而成)包括硅化物层122及传导阻挡层123。 Studs 304 (different from the etching step from the column 300) includes a silicide layer 122 and conductive barrier layer 123. 顶部导体400包括传导粘附层402(优选地为氮化钛)及传导层406 (例如,钨)。 Top conductor 400 includes a conductive adhesive layer 402 (preferably titanium nitride), and the conductive layer 406 (e.g., tungsten). 高_k介电材料形成的介电破裂反熔丝118介于顶部导体400与传导阻挡层123之间。 The dielectric material of high dielectric _k rupture antifuse 118 is formed between top conductor 400 and the conductive barrier layer 123 between. 介电破裂反熔丝118可以是连续的毯覆物,或可与顶部导体400 —起图案化,如图所示。 Dielectric rupture antifuse 118 may be a continuous blanket material, or may be a top conductor 400-- from patterned, as shown in FIG. 可设想出类似地包括相连式p-1-n二极管及高_k介电破裂反熔丝的许多其它替代实施例。 May assume many embodiments other alternative embodiments of Formula coupled similarly includes p-1-n diodes and high _k dielectric rupture anti-fuse.

[0047] 这些实施例的每一者均是包含以下各项的半导体装置:由沉积的半导体材料形成的相连式P-1-n 二极管,其中所述半导体材料已邻近于硅化物、锗化物、或硅化物-锗化物层而结晶;及与所述二极管电串联布置的介电破裂反熔丝,所述介电破裂反熔丝包含具有大于8的介电常数的介电材料。 [0047] Each of these embodiments is caught following a semiconductor device comprising: connected to the formula P-1-n diode is formed of a semiconductor material deposited, wherein the semiconductor material is adjacent to the silicide, germanium compound, or a silicide - crystallized germanide layer; the dielectric and diode arranged in series with the antifuse rupture, the rupture antifuse comprising a dielectric material having a dielectric constant greater than 8. 在每一实施例中,垂直定向的二极管均安置于底部导体与顶部导体之间,介电破裂反熔丝均安置于二极管与顶部导体之间或二极管与底部导体之间。 In each embodiment, a vertically oriented diode are disposed between the top conductor and the bottom conductor, a dielectric rupture antifuse are disposed between the diode and the top conductor or the bottom conductor diode. 在这些实例中,无论顶部导体还是底部导体均不包含硅层。 In these examples, either the top conductor or the bottom conductor layer not containing silicon.

[0048] 术语“相连式p-1-n 二极管”描述由半导体材料形成的在一端具有重掺杂P-型半导体材料且在另·一端具有重掺杂n-型半导体材料的二极管,在P-型区与n-型区之间具有本征或轻掺杂的半导体材料,但没有介于P-型区与n-型区之间在其破裂之前足以防止多数电流流动的介电破裂反熔丝。 [0048] The term "connected to the formula p-1-n diode" formed of a semiconductor material is described having at one end a heavily doped with P- type semiconductor material and heavily doped n- type semiconductor material on the other-end of the diode, the P - having an intrinsic or lightly doped semiconductor material between the region and the n- type region type, but not between the P- type region and the n- type region before it breaks majority current flow is sufficient to prevent dielectric rupture anti fuse. P-1-n 二极管优选地供在大存储器阵列中使用,因为此二极管可使反向偏置下的泄漏电流降到最低。 P-1-n diode is preferably for use in large memory arrays, since this allows the diode leakage current at a reverse bias to a minimum.

[0049] 在这些单元中的任一者中,在编程之前,反熔丝118是完整无缺的且阻止电流流动。 [0049] In any of these units, prior to programming, the antifuse 118 is intact and prevents current flow. 在编程期间,当在顶部导体400与底部导体200之间供应编程电压时,介电破裂反熔丝的一部分经历介电击穿,从而在相连式P-1-n 二极管302与顶部导体400之间或在相连式P-1-n 二极管302与底部导体200之间形成穿过介电破裂反熔丝118的传导路径。 During programming, the programming voltage when the supply between top conductor 400 and bottom conductor 200, a dielectric rupture antifuse dielectric portion undergoes breakdown, so connected to the formula P-1-n diode 302 and the top conductor 400 occasionally formed through the dielectric rupture antifuse 118 is conductive path connected between a formula P-1-n diode 302 and the bottom conductor 200.

[0050] 在本发明的实施例中,优选地可将由高_k介电材料形成的介电破裂反熔丝安置于两个金属或金属性层(例如,氮化钛或传导金属硅化物)之间。 [0050] In an embodiment of the present invention, the dielectric may preferably be formed by the high-_k rupture antifuse dielectric material disposed in two layers of metal or metal (e.g., titanium nitride, or conductive metal silicides) between. 这些传导层帮助跨越反熔丝建立电容,从而允许反熔丝比在反熔丝安置于半导体层之间或半导体层与金属或金属性层之间的情况下更容易地破裂。 These help create the conductive layer across the antifuse capacitor, the antifuse so as to allow more easily than in the case of rupture antifuse is disposed between the semiconductor layer or a semiconductor layer with a metal or metallic layer.

[0051] 将提供形成根据本发明的优选实施例形成的单片三维存储器阵列的详细实例。 [0051] The detailed examples provided forming a monolithic three dimensional memory array formed in accordance with a preferred embodiment of the present invention. 出于完整目的,将提供特定工艺条件、尺寸、方法及材料。 For purposes of full, we will provide particular process conditions, dimensions, materials and methods. 然而,应了解,此类细节并不打算成为限制性的,且可修改、省略或扩大这些细节中的许多细节,而结果仍属于本发明的范围之内。 However, it should be understood that such details are not intended to be limiting, and may be modified, omitted, or expanded many details of these details, while the results fall within the scope of the invention. 例如,来自'030专利,'549、' 530及'510申请案的一些细节可以是有用的。 For example, from the '030 patent,' 549, some details of the '530 and' 510 application may be useful. 为避免使本发明变得模糊,本发明并未将来自所述专利及这些申请案的所有细节都包括在内,但将了解并不打算排除相关的教示。 To avoid obscure the present invention, the present invention is not from all of the details of these patents and application are included, but will be understood not intended to exclude the relevant teachings.

[0052] 实例 [0052] Examples

[0053] 翻到图8a,存储器的形成开始于衬底100。 [0053] Turning to Figure 8a, the memory is formed in the substrate 100 begins. 此衬底100可以是此项技术中已知的任何半传导衬底,例如,单晶硅、IV-1V化合物(例如,硅-锗、或硅-锗-碳)、II1-V化合物、I1-VII化合物、此类衬底上的外延层、或任何其它半传导材料。 This substrate 100 can be any semiconducting substrate known in the art, e.g., monocrystalline silicon, IV-1V compound (e.g., a silicon - germanium, or a silicon - germanium - carbon), II1-V compound, I1 -VII compound, an epitaxial layer on such substrates, or any other semi-conductive materials. 所述衬底可包括制造于其中的集成电路。 The substrate may include integrated circuits fabricated therein.

[0054] 在衬底100上方形成绝缘层102。 [0054] The insulating layer 102 is formed over the substrate 100. 绝缘层102可以是氧化硅、氮化硅、S1-COH膜,或任一其它合适的绝缘材料。 Insulating layer 102 can be silicon oxide, silicon nitride, S1-COH film, or any other suitable insulating material.

[0055] 在衬底100及绝缘体102上方形成第一导体200。 [0055] The first conductor 200 formed over the substrate 100 and insulator 102. 绝缘层102与传导层106之间可包括粘附层104以帮助将传导层106粘附到绝缘层102。 102 may include an insulating layer between the conductive layer 106 and the adhesive layer 104 to help conducting layer 106 adhere to insulating layer 102. 如果上覆传导层106为钨,那么优选地使用氮化钛作为粘附层104。 If the overlying conductive layer 106 is tungsten, it is preferably used as an adhesion layer 104 of titanium nitride. 传导层106可包含此项技术中已知的任何传导材料,例如,钨或其它材料,包括钽、钛、铜、钴或其合金。 The conductive layer 106 may comprise any conductive material known in the art, e.g., tungsten, or other materials, including tantalum, titanium, copper, cobalt, or alloys thereof.

[0056] 一旦沉积了将形成导体轨道的所有层,那么将使用任何适合的掩蔽及蚀刻工艺来图案化及蚀刻所述层,以形成如图8a中以截面形式所示的大致平行大致共面的导体200。 [0056] Once all of the deposited layers forming the conductor rails, then using any suitable masking and etching process for patterning and etching the layer to form a substantially parallel as shown in FIG. 8a as shown in cross section in the form of a substantially coplanar the conductor 200. 导体200延伸出图页。 FIG conductor 200 extends page. 在一个实施例中,沉积并通过光刻图案化光致抗蚀剂,且蚀刻所述层,并接着使用标准工艺技术来移除所述光致抗蚀剂。 In one embodiment, the deposition and patterned by photolithography a photoresist, and etching the layer, and then removed using standard process techniques of the photoresist.

[0057] 接下来,在导体轨道200上及其之间沉积介电材料108。 [0057] Next, the conductor rails 200 and 108 between the dielectric material is deposited. 介电材料108可以是任何已知的电绝缘材料,例如氧化硅、氮化硅或氧氮化硅。 The dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. 在优选实施例中,将通过高密度等离子方法沉积的二氧化硅用作介电材料108。 In a preferred embodiment, silica is used as a dielectric material deposited by high-density plasma method 108.

[0058] 最后,移除导体轨道200顶部上的过量介电材料108,暴露由介电材料108分离的导体轨道200的顶部,并留下大致平面表面。 [0058] Finally, excess dielectric material 200 on top of conductor rails 108 is removed, exposing the top by a dielectric material 108 separating the conductor rails 200, and leaving a substantially planar surface. 所得结构显示于图8a中。 The resulting structure is shown in Figure 8a. 可通过此项技术中已知的任何工艺(例如,化学机械平面化(CMP)或回蚀)来执行此电介质过填充物的移除以形成平面表面。 This may be performed by removing a dielectric filler to form a planar surface by any process known in the art (e.g., chemical mechanical planarization (CMP) or etch-back). 在替代实施例中,导体200可改为通过镶嵌方法来形成。 In an alternative embodiment, the conductor 200 may instead be formed by a damascene method.

[0059] 翻到图8b,接下来形成具有大于约8的介电常数k的高-k介电材料的薄层118。 [0059] Turning to Figure 8b, a thin layer of high -k dielectric material having a dielectric constant k greater than about 8 118 is formed next. (为简明起见,从图8b及随后配置中省略衬底100,但将假定其存在。)此材料的介电常数k的值优选地在8与50之间,最优选地在约8与约25之间。 (For simplicity, omitted from Figure 8b the substrate 100 and the following arrangement, its presence will be assumed.) Dielectric constant k value of the material is preferably between 8 and 50, most preferably from about 8 to about 25. 此层优选地在约10与约200埃之间,例如,在约20与约100埃之间。 This layer is preferably between about 10 and about 200 Angstroms, e.g., between about 20 and about 100 angstroms. 层118的优选材料包括HfO2, Al2O3' ZrO2, TiO2'La2O3' Ta2O5' RuO2' ZrSiOx, AlSiOx' HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx、HfSiAlON、及ZrSiAlON。 Material layer 118 preferably comprises HfO2, Al2O3 'ZrO2, TiO2'La2O3' Ta2O5 'RuO2' ZrSiOx, AlSiOx 'HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. 在一些实施例中,可混合这些材料中的两种或两种以上材料。 In some embodiments, these materials may be mixed in two or more materials. 最优选的材料包括HfO2 (其具有约25的介电常数)或Al2O3 (其具有约9的介电常数)。 The most preferred materials include HfO 2 (which has a dielectric constant of about 25), or Al2O3 (having a dielectric constant of about 9). 在优选实施例中,层118通过ALD形成,以形成极高质量的膜。 Embodiment, the layer 118 is formed by ALD in the preferred embodiment, to form high quality films. 优选地,高质量膜是致密的(尽可能接近其理论密度);具有几乎没有针孔的完整覆盖;具有低密度的电缺陷。 Preferably, a high-quality film is dense (as close to the theoretical density); having no pinholes almost complete coverage; electrical defects having a low density. 一般来说,使在膜质量上差别不大具有较高介电常数的材料厚于具有较低介电常数的材料将是优选的。 Generally, the thickness of the material on the film quality is not very different in having a higher dielectric constant material having a lower dielectric constant would be preferred. 例如,通过ALD形成的Al2O3膜优选地具有在约5与约80埃之间,优选地约30埃的厚度,而通过ALD形成的HfO2膜优选地具有在约5与约100埃之间,优选地约40埃的厚度。 For example, Al2O3 film is preferably formed by ALD has between about 5 and about 80 angstroms, preferably a thickness of about 30 angstroms, and the HfO2 film is preferably formed by ALD has between about 5 and about 100 angstroms, preferably a thickness of about 40 angstroms. 层118将充当介电破裂反熔丝。 The dielectric layer 118 serving as rupture antifuse. 在一些实施例中,在沉积层118之前沉积传导阻挡层(未显示)可以是优选的。 In some embodiments, layer 118 is deposited prior to depositing the conductive barrier layer (not shown) may be preferred. 此阻挡层(例如,约100埃的氮化钛)将提供均匀表面,在所述均匀表面上沉积高_k介电破裂反熔丝层118,此可改善所述高-k介电破裂反熔丝层的均匀性。 This barrier layer (e.g., titanium nitride about 100 Angstroms) to provide a uniform surface, depositing a high dielectric _k rupture antifuse layer 118 uniformly on the surface, which can improve the high -k dielectric rupture anti uniformity of the fuse layer.

[0060] 阻挡层111沉积于层118上。 [0060] The barrier layer 111 is deposited on the layer 118. 所述阻挡层可以是具有任何适当的厚度(例如,50至IJ 200 ±矣,优选地100埃)的任何适当的传导阻挡材料,例如,氮化钛。 The barrier layer may be any suitable thickness (e.g., 50 to IJ 200 ± men, preferably 100 angstrom) barrier of any suitable conductive material, such as titanium nitride. 在一些实施例中,可省略阻挡层111。 In some embodiments, the barrier layer 111 may be omitted.

[0061] 接下来,沉积将被图案化成若干柱的半导体材料。 [0061] Next, will be deposited into a plurality of pillars of semiconductor material pattern. 所述半导体材料可以是硅、锗、硅-锗合金或其它适合的半导体或半导体合金。 The semiconductor material may be silicon, germanium, a silicon - germanium alloy, or other suitable semiconductors or semiconductor alloys. 为简明起见,此说明将半导体材料称为硅,但应了解,所属领域的技术人员可改为选择这些其它适合材料中的任何材料。 For simplicity, this description will be referred to as a silicon semiconductor material, it is to be appreciated that those skilled in the art can be changed to any other material suitable selection of these materials. [0062] 可通过此项技术中已知的任何沉积及掺杂方法来形成底部重掺杂区112。 [0062] may be formed by any deposition and doping method known in the art a bottom heavily doped region 112. 可沉积硅且接着对其掺杂,但优选地通过在沉积硅期间使提供n型掺杂剂原子(例如磷)的供体气体流动来原位掺杂所述硅。 Its silicon may be deposited and then doped, but is preferably provided by making the n-type dopant atoms (e.g. phosphorus) donor gas flows situ doping the silicon during the silicon deposition. 重掺杂区112优选地在约100与约800埃厚之间。 The heavily doped region 112 is preferably between about 100 and about 800 angstroms thick places.

[0063] 接着,可通过此项技术中已知的任何方法形成本征区114。 [0063] Next, the intrinsic region 114 may be formed by any method known in the art. 区114可以是硅、锗或者硅或锗的任何合金且具有在约1100与约3300埃之间,优选地约2000埃的厚度。 Region 114 may be silicon, germanium, or any alloy of silicon or germanium and having between about 1100 and about 3300 angstroms, preferably a thickness of about 2000 Angstroms. 重掺杂区112及本征区114的硅在沉积时优选地为无定形的。 When silicon is preferably deposited as an amorphous region 112 and the intrinsic region 114 is heavily doped.

[0064] 刚刚沉积的半导体区114及112连同下伏阻挡层111、高_k介电层118及阻挡层110将被图案化及蚀刻以形成柱300。 [0064] The semiconductor regions 114 and 112 just deposited, along with underlying barrier layer 111, the high dielectric layer 118 _k and the barrier layer 110 will be patterned and etched to form pillars 300. 柱300应具有与下方的导体200约相同的间距和约相同的宽度,以使每一柱300都形成在导体200的顶部上。 Column 300 has the same conductor should be about 200 downward pitch of about the same width, so that each pillar 300 is formed on the top conductor 200. 可容忍一些不对准。 We can tolerate some misalignment.

[0065] 可使用任一适合的掩蔽及蚀刻工艺来形成柱300。 [0065] using any suitable masking and etching process to form the post 300. 例如,可沉积、使用标准光刻技术图案化及蚀刻光致抗蚀剂,接着移除所述光致抗蚀剂。 For example, it may be deposited, patterned using standard photolithographic techniques and etching the photoresist, followed by removing the photoresist. 另一选择是,可在半导体层堆叠顶部上形成某种其它材料(例如,二氧化硅)的硬掩模,其上面具有底部抗反射涂层(BARC),接着图案化并蚀刻所述硬掩模。 Alternatively, the stack may be formed in the semiconductor layer on top of some other material (e.g., silica) hard mask thereon with a bottom antireflective coating (a BARC), and etching followed by patterning the hard mask mold. 类似地,可将介电抗反射涂层(DARC)用作硬掩模。 Similarly, dielectric antireflective coating (the DARC) can be used as a hard mask.

[0066] 在陈(Chen)于2003年12月5日申请的美国申请案第10/728436号“具有使用交替相移的内部非印刷窗口的光掩模特征(hotomask Features with InteriorNonprintingffindow Using Alternating Phase Shifting),,或陈(Chen)于2004 年4 月I日申请的美国申请案第10/815312号“具有无铬非印刷相移窗口的光掩模特征(hotomaskFeatureswith Chromeless Nonprinting Phase Shifting Window) ” 中(所述两个申请案由本发明的受让人拥有并以引用的方式并入本文中)描述的光刻技术可有利地用于执行在根据本发明形成存储器阵列中使用的任何光刻步骤。 [0066] In US Application No. 10/728436 Chen (Chen) on December 5, 2003 filed "with the use of alternating phase shift of internal non-printed window of photomask features (hotomask Features with InteriorNonprintingffindow Using Alternating Phase Shifting ) ,, or Chen (Chen) US application No. 10/815312 in April 2004, I filed "with a light mask features chrome-free non-printing phase shift window (hotomaskFeatureswith Chromeless Nonprinting phase shifting window)" in ( the assignee of the present invention, two applications have the cause of action and is incorporated by reference herein) described photolithographic technique can advantageously be used to perform any photolithography step used in formation of a memory array according to the present invention.

[0067] 在半导体柱300上及其之间沉积介电材料108,以填充所述半导体柱之间的间隙。 [0067] In the semiconductor pillar between 300 and depositing a dielectric material 108, filling the gaps between the semiconductor pillar to. 介电材料108可以是任何已知的电绝缘材料,例如氧化硅、氮化硅或氧氮化硅。 The dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. 在优选实施例中,使用二氧化硅作为绝缘材料。 In a preferred embodiment, silica is used as the insulating material.

`[0068] 接下来,移除柱300顶部上的介电材料,暴露由介电材料108分离的柱300的顶部,并留下大致平面表面。 `[0068] Next, remove the dielectric material on top of the column 300, the exposed dielectric material 108 on top of the separation column 300, and leaving a substantially planar surface. 可通过此项技术中已知的任何工艺(例如,CMP或回蚀)来执行电介质过填充物的此移除。 May be performed by any process known in the art (e.g., CMP or etchback) through this removal dielectric filler. 在CMP或回蚀之后,执行离子植入,以形成重掺杂P-型顶部区116。 After CMP or etchback, ion implantation performed to form a heavily doped P- type region 116 at the top. 所述P-型掺杂剂优选地为浅植入的硼,其中植入能量例如为2keV,且剂量约为3x.10/cm。 The P- type dopant is preferably a light boron implant, wherein the implantation energy is, for example 2keV, and the dose is about 3x.10 / cm. 此植入步骤完成二极管302的形成。 This implant step completes formation of diodes 302. 所得结构显示于图Sb中。 The resulting structure is shown in FIG. And Sb. 在刚刚形成的二极管中,底部重掺杂区112为n-型而顶部重掺杂区116为P-型;明显地,可反转二极管的极性。 Diode just formed, bottom heavily doped region 112 is heavily doped n- type region 116 and the top of the P- type; Obviously, the polarity of the diode may be reversed.

[0069] 总之,通过在第一导体200上方沉积半导体层堆叠;在单个图案化步骤中以柱300的形式图案化并蚀刻所述半导体层堆叠来形成柱300。 [0069] In summary, the first conductor 200 is deposited over the semiconductor layer stack; in a single patterning step in a pattern of column 300 and etching the semiconductor layer stack 300 to form pillars. 在完成装置之后,将相连式p-1-n 二极管安置于所述柱内。 After completion of the means to connect the formula p-1-n diode disposed within the column.

[0070] 翻到图8c,在清理已形成在柱300顶部上的任何原生氧化物之后,沉积一层120硅化物形成金属,例如、钛、钴、铬、钽、钼、镍、铌或钯。 After [0070] Turning to FIG 8C, the cleaning of any native oxide formed on the top of the column 300, a layer 120 is deposited silicide-forming metal, e.g., titanium, cobalt, chromium, tantalum, molybdenum, nickel, niobium, palladium, or . 层120优选地为钛或钴;如果层120为钛,那么其厚度优选地在约10与约100埃之间,最优选地约20埃。 Layer 120 is preferably titanium or cobalt; if the layer 120 is titanium, the thickness thereof is preferably between about 10 and about 100 angstroms, most preferably about 20 Angstroms. 层120的后面是氮化钛层404。 Rear layer 120 is titanium nitride layer 404. 两个层120及404优选地在约20与约100埃之间,最优选地约50埃。 Two layers 120 and 404 is preferably between about 20 and about 100 angstroms, most preferably about 50 Angstroms. 接下来,沉积一层406传导材料,例如,钨。 Next, depositing a layer of conductive material 406, such as tungsten. 将层406、404及120图案化并蚀刻为若干轨道形状的顶部导体400,所述顶部导体400优选地沿垂直于底部导体200的方向延伸。 The top conductor layers 406,404 and 120 are patterned and etched to form a number of track 400, the top conductor 400 preferably extends along a direction perpendicular to the bottom conductor 200.

[0071] 接下来,在导体400上及其之间沉积介电材料(未显示)。 [0071] Next, depositing a dielectric material over and between conductor 400 (not shown). 所述介电材料可以是任何已知的电绝缘材料,例如,氧化硅、氮化硅或氧氮化硅。 The dielectric material may be any known electrically insulating material, e.g., silicon oxide, silicon nitride or silicon oxynitride. 在优选实施例中,将氧化硅用作此介电材料。 In a preferred embodiment, silicon oxide is used as this dielectric material.

[0072] 已描述了第一存储器层级的形成。 [0072] have described the formation of the first memory level. 可在此第一存储器层级上方形成若干额外的存储器层级以形成单片三维存储器阵列。 It may be formed of a number of additional memory levels above this first memory level to form a monolithic three dimensional memory array. 刚刚描述的阵列仅是一个实例;且可以其它方式变化,例如,包括图6及7中所示的存储器单元的任一者。 Array just described is merely one example; and may vary in other ways, e.g., including the memory cell shown in FIG. 6 and 7 of any one.

[0073] 参照图10c,注意硅化物形成金属的层120与顶部重掺杂区116的硅接触。 [0073] Referring to FIG. 10c, note silicide forming metal layer 120 and a top heavily doped silicon contact region 116. 在随后升温步骤期间,层120的金属将与重掺杂区116的硅的某一部分反应,以形成硅化物层(未显示)。 During the heating step Subsequently, the metal layer 120 will react with a portion of the silicon heavily doped region 116 to form a silicide layer (not shown). 此硅化物层在低于使硅结晶所需的温度下形成,且因此将在区112、114及116在很大程度上仍为无定形时形成。 This silicide layer is formed below the silicon crystal so that the desired temperature, and when the thus formed amorphous remained largely in the region 112, 114 and 116. 如果将硅-锗合金用于顶部重掺杂区116,那么可形成例如硅化钴-锗化钴或硅化钛-锗化钛的硅化物-锗化物层。 If silicon - germanium alloy for a top heavily doped region 116, it may be formed, for example, cobalt suicide - germanium, titanium silicide or cobalt - germanium titanium silicide - germanide layer.

[0074] 优选地,在已形成所有存储器层级之后,执行单个结晶退火以使二极管302例如在750摄氏度下保持约60秒而结晶,虽然可在形成每一存储器层级时对其进行退火。 [0074] Preferably, after all of the memory hierarchy has been formed, performing recrystallization annealing to a single diode 302, for example, for about 60 seconds at 750 ° C crystallized, then annealed although each may be formed in the memory hierarchy. 所得二极管通常将是多晶的。 The resulting diodes will typically be polycrystalline. 由于这些二极管的半导体材料是与所述半导体材料与之具有良好晶格匹配的硅化物或硅化物-锗化物层接触而结晶,因此二极管302的半导体材料将是低缺陷及低电阻率的。 Since these diodes are semiconductor materials of the semiconductor material having good lattice matching with the suicide or suicide - germanide layer contacting the crystallized semiconductor material of the diode 302 and therefore will be low and the low resistivity defect.

[0075] 如果将HfO2用于介电破裂反熔丝118,那么应留意将处理温度保持在HfO2的结晶温度以下,所述结晶温度可以是约700到约800摄氏度。 [0075] If a HfO2 dielectric rupture antifuse 118, it should be aware that the process temperature is maintained at the crystallization temperature or less of HfO2, the crystallization temperature may be from about 700 to about 800 degrees Celsius. 完整无缺的晶体HfO2反熔丝层具有比无定形HfO2层高得多的泄露。 Intact crystalline HfO2 antifuse layer has a higher amorphous HfO2 storey much leakage.

[0076] 在一些实施例中,可在存储器层级之间共享导体,S卩,顶部导体400将充当下一存储器层级的底部导体。 [0076] In some embodiments, may be shared between memory levels conductors, S Jie, top conductor 400 would serve as the bottom conductor of the next memory level. 在其它实施例中,在图8c的第一存储器层级上方形成层级间电介质(未显示),其表面经平面化,且由于第二存储器层级的构造在此经平面化的层级间电介质上开始,因此不具有共享的导体。 In other embodiments, is formed above the first memory level of FIG. 8c inter-level dielectric (not shown), which surface is planarized, and since the configuration of the second memory level here by between planarized level electrical medium starts, therefore they do not share conductors.

[0077] 本发明允许减小编程电压。 [0077] The present invention allows reducing the programming voltage. 在'030专利的实施例中,足以编程阵列中的几乎所有(例如,99%以上)的单元的编程电压包括跨越将要编程的单元至少为8伏的脉冲。 In the '030 patent Example, almost all (e.g., 99% or more) of the programming voltage across the cell comprises a cell to be programmed in the array sufficient programming of at least 8 volt pulse. 在本发明的实施例中,类似刚刚描述的阵列,可减小编程电压。 In an embodiment of the present invention, similar to the array just described, the programming voltage can be reduced. 例如,可以小于约8伏(且在一些实施例中,以小于6伏或小于4.0伏)的编程脉冲来编程阵列中的几乎所有单元。 Almost all units e.g., less than about 8 volts (and in some embodiments, less than 6 volts or less than 4.0 volts) of programming pulses to program the array.

[0078] 在一些实施例中,在二极管处于反向偏置中时施加编程脉冲可是优选的。 [0078] In some embodiments, the programming pulse is applied when the diode is in reverse bias may be preferable. 此可具有以下优点:减小或消除跨越阵列中的未选单元的泄露;如在库玛(Kumar)等人于2006年7月28日申请的美国专利申请案第11/496,986号“使用包含具有可修整电阻的可切换半导体存储器兀件的存储器单兀的方法(Method For Using A Memory CellComprisingSwitchable Semiconductor Memory Element With Trimmable Resistance,),,中所述,所述专利申请案由本发明的受让人拥有且以引用的方式并入本文中。 This may have the following advantages: to reduce or eliminate the leakage across unselected cell array; U.S. Patent Application Kumar (Kumar) et al, filed July 28, 2006 No. 11 / 496,986 on " Wu memory unit containing a semiconductor memory having a switching device trimmable resistor Wu a method (method For using a memory CellComprisingSwitchable semiconductor memory element with trimmable resistance,) ,, said, the cause of action assigned patent application of the present invention owned and hereby incorporated herein by reference.

[0079] 单片三维存储器阵列是一种其中多个存储器层级形成于单个衬底(例如,晶片)上方而无中间衬底的存储器阵列。 [0079] The monolithic three dimensional memory array is one in which multiple memory levels are formed on a single substrate (e.g., wafer) without intermediate memory array over the substrate. 形成一个存储器层级的若干层直接沉积或生长于现有的一或多个层级的若干层上。 Forming a plurality of layers of a memory level are deposited or grown directly on the existing number of layers of one or more levels. 相反,如在利迪(Leedy)的美国专利第5,915,167号“三维结构存储器(Three dimensional structure memory) ”中,已通过在单独衬底上形成若干存储器层级并使所述存储器层级彼此上下黏附在一起而构造出若干堆叠式存储器。 In contrast, as in Leedy (Leedy,) U.S. Patent No. 5,915,167 "Three-dimensional structure of the memory (Three dimensional structure memory)", it has been formed by a plurality of memory level of the memory hierarchy and each other on a separate substrate adhesion constructed vertically together a plurality of stacked memory. 可在接合之前使所述衬底变薄或将其自存储器层级移除,但由于存储器层级最初形成于单独衬底上,因此此类存储器并非真正的单片三维存储器阵列。 The substrate may be thinned before bonding or removed from the memory levels, but as the memory levels are initially formed over separate substrates, such memories therefore not true monolithic three dimensional memory array. [0080] 形成于衬底上方的单片三维存储器阵列至少包括:第一存储器层级,其形成于所述衬底上方的第一高度处;及第二存储器层级,其形成于与所述第一高度不同的第二高度处。 [0080] is formed over a substrate at least a monolithic three dimensional memory array comprising: a first memory level formed at a first height above the substrate; and a second memory level formed in the first the second height different place. 在此多层级阵列中,可在衬底上方形成三个、四个、八个或任何实际数目的存储器层级。 The multi-level array, may be formed in three, four, eight, or any practical number of memory levels over the substrate.

[0081] 瑞迪根(Radigan)等人于2006年5月31日申请的美国专利申请案第11/444,936号“用以在沟槽蚀刻期间保护经图案化特征的传导硬掩模(Conductive Hard MasktoProtect Patterned Features During Trench Etch,) ” 中描述了用于形成其中使用壤嵌构造形成导体的类似阵列的替代方法,所述专利申请案受让与本发明的受让人且借此以引用的方式并入本文中。 [0081] U.S. Patent Application Reddy root (Radigan) et al, filed May 31, 2006 in / 444,936 No. 11, "for protection during trench etching by conducting patterned hardmask features (Conductive Hard MasktoProtect Patterned Features During Trench Etch,) "is described in which alternative method for forming a similar array structure is formed using the conductor embedded soil, the patent application assigned to the assignee of the embodiment of the present invention and thereby the reference incorporated herein. 可改为使用瑞迪根等人的方法来形成根据本发明的阵列。 Root may be used instead Reddy et al method for forming an array according to the present invention.

[0082] 本文已描述了详细的制作方法,但还可使用形成相同结构的任何其它方法而结果仍属于本发明的范围。 [0082] This article has described in detail the production method, but any other methods may also be formed using the same structures and the result is still the scope of the present invention.

[0083] 以上详细说明仅描述了本发明可采取的许多形式中的几种形式。 [0083] described in detail above described only several forms of the present invention can take many forms in. 出于此原因,此详细说明打算作为说明性而非限定性说明。 For this reason, this detailed description is intended as illustrative rather than restrictive description. 本发明的范围将仅由以上权利要求(包括所有等效的权利要求)来界定。 Scope of the present invention will be limited only by the following claims (including all equivalents of the claims) be defined.

Claims (44)

1.一种半导体装置,其包含: 由沉积的半导体材料形成的相连式p-1-n 二极管,其中所述半导体材料已邻近于硅化物、硅化物-锗化物、或锗化物层而结晶'及与所述二极管电串联布置的介电破裂反熔丝,所述介电破裂反熔丝包含具有大于8的介电常数的介电材料; 其中所述介电破裂反熔丝由一沉积工艺形成,其厚度为50埃或更少,且安置于第一金属性层和第二金属性层之间。 1. A semiconductor device, comprising: connected to the p-1-n type diode is formed from a deposited semiconductor material, wherein the semiconductor material is adjacent to the silicide, silicides - germanide or germanide layer crystallized ' and a diode arranged in series with the dielectric rupture antifuse, said dielectric rupture antifuse comprising a dielectric material having a dielectric constant greater than 8; wherein the dielectric rupture anti-fuse by a deposition process It is formed having a thickness of 50 angstroms or less, and is disposed between the first metal layer and second metallic layer.
2.如权利要求1所述的半导体装置,其中所述半导体材料是多晶的。 The semiconductor device according to claim 1, wherein said semiconductor material is polycrystalline.
3.如权利要求1所述的半导体装置,其中所述介电材料选自由Hf02、Al203、Zr02、Ti02、La2O3' Ta2O5' RuO2' ZrSiOx, AlSiOx' HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx、HfSiAlON,及ZrSiAlON组成的群组。 The semiconductor device according to claim 1, wherein said dielectric material is selected from the group consisting of Hf02, Al203, Zr02, Ti02, La2O3 'Ta2O5' RuO2 'ZrSiOx, AlSiOx' HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and the group consisting of ZrSiAlON.
4.如权利要求3所述的半导体装置,其中所述介电材料是HfO2或八1203。 The semiconductor device according to claim 3, wherein said dielectric material is HfO2 or eight 1203.
5.如权利要求1所述的半导体装置,其中所述硅化物、硅化物-锗化物、或锗化物层是a)硅化钛、硅化钛-锗化钛、或锗化钛,或者b)硅化钴、硅化钴-锗化钴、或锗化钴。 Titanium silicide, germanium, germanium, or titanium, or b) - 5. The semiconductor device as claimed in claim 1, wherein said silicide silicide - germanide or germanide layer is a) titanium silicide, titanium silicide, cobalt, cobalt silicide - germanium, cobalt, germanium, or cobalt.
6.如权利要求1所述的半导体装置,其中所述半导体材料包含硅、锗、及/或硅-锗合金。 The semiconductor device as claimed in claim 1, wherein the semiconductor material comprises silicon, germanium, and / or a silicon - germanium alloy.
7.如权利要求6所述的半导体装置,其中所述相连式p-1-n 二极管垂直定向且安置于所述相连式P-1-n 二极管下方的底部导体与所述相连式p-1-n 二极管上方的顶部导体之间,且所述介电破裂反熔丝安置于所述相连式P-1-n 二极管与所述顶部导体之间或所述相连式p-1-n 二极管与所述底部导体之间。 The semiconductor device according to claim 6, wherein said formula is connected to p-1-n diode is vertically oriented and disposed in said formula is connected to the bottom of the P-1-n diode and the underlying conductor is connected to the formula p-1 -n between a top conductor above the diode and the dielectric rupture antifuse is disposed between the coupled formula P-1-n diode is connected to the top conductor or the formula p-1-n diode and the between said bottom conductor.
8.如权利要求7所述的半导体装置,其中所述顶部导体或所述底部导体不包含硅层。 8. The semiconductor device according to claim 7, wherein the top conductor or the bottom conductor layer does not contain silicon.
9.如权利要求7所述的半导体装置,其中所述硅化物、硅化物-锗化物、或锗化物层在所述相连式P-1-n 二极管上方且所述介电破裂反熔丝在所述相连式p-1-n 二极管下方。 9. The semiconductor device according to claim 7, wherein said suicide, silicide - germanide or germanide layer P-1-n in the above formula is connected to the diode and the dielectric rupture antifuse the formula below is connected to p-1-n diode.
10.如权利要求1所述的半导体装置,其中所述介电破裂反熔丝为20埃厚或更少。 10. The semiconductor device according to claim 1, wherein the dielectric rupture antifuse 20 angstroms thick or less.
11.如权利要求1所述的半导体装置,其中所述介电破裂反熔丝是通过原子层沉积形成的。 11. The semiconductor device according to claim 1, wherein the dielectric rupture antifuse is formed by atomic layer deposition.
12.如权利要求7所述的半导体装置,其中所述介电破裂反熔丝的一部分已经历介电击穿,从而在所述相连式P-1-n 二极管与所述顶部导体之间或在所述相连式p-1-n 二极管与所述底部导体之间形成穿过所述介电破裂反熔丝的传导路径。 12. The semiconductor device according to claim 7, wherein a portion of the dielectric rupture antifuse dielectric breakdown has undergone so connected between said formula P-1-n diode and the top conductor or forming a conductive path through the dielectric rupture antifuse connected between said formula p-1-n diodes and the bottom conductor.
13.如权利要求7所述的半导体装置,其中所述底部导体、所述相连式p-1-n 二极管及所述顶部导体均形成在半导体衬底上方。 13. The semiconductor device according to claim 7, wherein the bottom conductor, is connected to the p-1-n type diode, and the top conductor are each formed over the semiconductor substrate.
14.如权利要求6所述的半导体装置,其中所述相连式p-1-n 二极管呈柱形式。 14. The semiconductor device according to claim 6, wherein said formula is connected to p-1-n diode as a column format.
15.—种第一存储器层级,其包含: 形成于衬底上方的多个平行且共面的第一导体; 形成于所述第一导体上方的多个平行且共面的第二导体; 包含半导体材料的多个垂直定向的相连式P-1-n 二极管,所述半导体材料邻近于硅化物、硅化物-锗化物、或锗化物层而结晶; 由具有大于8的介电常数的介电材料形成的多个介电破裂反熔丝, 其中所述介电破裂反熔丝中的每一者是由一沉积工艺形成且厚度为50埃或更少,且安置于第一金属性层和第二金属性层之间; 其中所述相连式P-1-n 二极管的每一者安置于所述第一导体中的一者与所述第二导体中的一者之间,且其中所述介电破裂反熔丝的每一者安置于所述第一导体中的一者与所述相连式P-1-n二极管中的一者之间或所述第二导体中的一者与所述相连式P-1-n 二极管中的一者之间; 及多个存储器单元,每一存储器单元 15.- species first memory level comprising: a first conductor formed on the substrate over the plurality of parallel and coplanar; forming a plurality of parallel second conductors above the first conductors and coplanar; comprising connected to a plurality of vertically oriented formula P-1-n diode semiconductor material, the semiconductor material adjacent to the silicide, silicides - germanide or germanide layer is crystallized; dielectric having a dielectric constant greater than 8 a plurality of dielectric material rupture antifuse, wherein each of said dielectric rupture antifuse is formed by a deposition process and a thickness of 50 angstroms or less, and is disposed on the first metal layer and between the second metal layer; wherein said formula is connected to each of the P-1-n diode is disposed between the first conductor and the second conductor one of one, and wherein between each of said dielectric rupture antifuse is disposed in the first conductor is connected to one of the one of formula P-1-n diodes or the second conductor of one of the connected between said formula P-1-n diode of one; and a plurality of memory cells, each memory cell 含所述相连式P-1-n 二极管中的一者及所述介电破裂反熔丝中的一者。 Containing the coupled formula P-1-n diode of one and the dielectric rupture antifuse of one.
16.如权利要求15所述的第一存储器层级,其中所述介电材料选自由Hf02、A1203、ZrO2, TiO2, La2O3> Ta2O5' RuO2' ZrSiOx、AlSiOx、HfSiOx、HfAlOx, HfSiON、ZrSiAlOx, HfSiAlOx、HfSiAlON、及ZrSiAlON组成的群组。 16. The first memory level according to claim 15, wherein said dielectric material is selected from the group consisting of Hf02, A1203, ZrO2, TiO2, La2O3> Ta2O5 'RuO2' ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and the group consisting of ZrSiAlON.
17.如权利要求15所述的第一存储器层级,其中所述半导体材料包含硅、锗、及/或硅-锗合金。 17. The first memory level according to claim 15, wherein the semiconductor material comprises silicon, germanium, and / or a silicon - germanium alloy.
18.如权利要求15所述的第一存储器层级,其中所述介电破裂反熔丝安置于所述相连式p-1-n 二极管下方。 18. The first memory level according to claim 15, wherein the dielectric rupture antifuse is disposed below said formula is connected to p-1-n diode.
19.如权利要求15所述的第一存储器层级,其中所述介电破裂反熔丝安置于所述相连式p-1-n 二极管下方且所述硅化物、硅化物-锗化物、或锗化物层安置于所述相连式p-1-n二极管上方。 19. The first memory level according to claim 15, wherein the dielectric rupture antifuse is disposed below said formula is connected to p-1-n diode and the silicide silicide - germanium compound, or germanium compound layer disposed in said formula is connected to the top p-1-n diode.
20.如权利要求15所述的第一存储器层级,其中至少第二存储器层级单片地形成于所述第一存储器层级上方。 20. The first memory level according to claim 15, wherein the at least a second memory level monolithically formed above the first memory level.
21.—种形成于衬底上方的单片三维存储器阵列,其包含a)单片地形成于所述衬底上方的第一存储器层级,所述第一存储器层级包含: i)沿第一方向延伸的、平行且共面的多个第一导体; ϋ)沿不同于所述第一方向的第二方向延伸的、平行且共面的多个第二导体,所述第二导体在所述第一导体上方; iii)由沉积的半导体材料形成的多个垂直定向的相连式p-1-n 二极管,所述半导体材料邻近于硅化物、硅化物-锗化物、或锗化物层而结晶,每一二极管垂直安置于所述第一导体中的一者与所述第二导体中的一者之间; iv)由具有大于8的介电常数的介电材料形成的多个介电破裂反熔丝;其中所述介电破裂反熔丝中的每一者由一沉积工艺形成,其厚度为50埃或更少,且安置于第一金属性层和第二金属性层之间'及V)多个存储器单元,每一存储器单元包含串联布置的所述二极 21.- species monolithic three dimensional memory array formed above a substrate, comprising a) monolithically formed above the first memory level of the substrate, the first memory level comprising: i) a first direction extending a plurality of parallel and coplanar first conductors; ϋ) extending in a second direction different from the first direction, a plurality of parallel and co-planar second conductor, the second conductor in the above the first conductor; iii) is connected to a plurality of vertically oriented p-1-n type diode is formed from a deposited semiconductor material, the semiconductor material adjacent to the silicide, silicides - germanide or germanide layer is crystallized, each diode vertically disposed between the first conductor and the second conductor one of one; IV) formed from a plurality of dielectric material having a dielectric constant greater than 8, broken electrical anti the fuse; wherein each of said dielectric rupture antifuse is formed by a deposition process, a thickness of 50 angstroms or less, and is disposed between the first metal layer and the second metal layer 'and the V) a plurality of memory cells, each memory cell comprising a diode arranged in series 管中的一者及所述介电破裂反熔丝中的一者;及b)单片地形成于所述第一存储器层级上方的第二存储器层级。 Tubes of one and the dielectric rupture antifuse of one; and b) monolithically forming a second memory level above the first memory level.
22.如权利要求21所述的单片三维存储器阵列,其中所述介电材料选自由Hf02、Al203、ZrO2, TiO2, La2O3' Ta2O5' RuO2' ZrSiOx, AlSiOx' HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx、HfSiAlON、及ZrSiAlON组成的群组。 22. The monolithic three dimensional memory array as claimed in claim 21, wherein said dielectric material is selected from the group consisting of Hf02, Al203, ZrO2, TiO2, La2O3 'Ta2O5' RuO2 'ZrSiOx, AlSiOx' HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx , HfSiAlON, and the group consisting of ZrSiAlON.
23.一种用于形成及编程非易失性存储器单元的方法,所述方法包含: 形成相连式P-1-n 二极管,所述相连式p-1-n 二极管包含沉积的半导体材料; 形成与所述沉积的半导体材料接触的硅化物、硅化物-锗化物、或锗化物层;使与所述硅化物、硅化物-锗化物、或锗化物层接触的所述沉积的半导体材料结晶;形成具有大于8的介电常数的介电材料层;其中所述介电材料层由一沉积工艺形成,其厚度为50埃或更少,且安置于第一金属性层和第二金属性层之间;及使所述介电材料层的一部分经受介电击穿, 其中所述存储器单元包含所述相连式P-1-n 二极管及所述介电材料层。 23. A method of forming and for programming a nonvolatile memory cell, the method comprising: forming connected formula P-1-n diode, is connected to the p-1-n type diode including a semiconductor material is deposited; forming contact with the semiconductor material of the deposited silicide, silicides - germanide or germanide layer; so that the silicide silicide - germanide, or a semiconductor material of the layer in contact with the deposited crystalline germanium; forming a dielectric material layer having a dielectric constant greater than 8; wherein said layer of dielectric material is formed by a deposition process, a thickness of 50 angstroms or less, and is disposed on the first metal layer and second metal layer between; and the dielectric layer of dielectric material so that a portion subjected to dielectric breakdown, which is connected to the memory cell comprising the formula P-1-n diode and the dielectric material layer.
24.如权利要求23所述的方法,其中通过原子层沉积来沉积所述介电材料层。 24. The method according to claim 23, wherein by atomic layer deposition to deposit the dielectric layer of dielectric material.
25.如权利要求23所述的方法,其中所述介电材料层为20埃厚或更少。 25. The method according to claim 23, wherein said dielectric material layer is 20 angstroms thick or less.
26.如权利要求 23 所述的方法,其中从由HfO2, Al2O3' ZrO2, Ti02、La203、Ta2O5' RuO2,ZrSiOx, AlSiOx, HfSiOx、HfAIOx、HfSiON、ZrSiAlOx, HfSiA10x、HfSiAlON、及ZrSiAlON 组成的群组中选择所述介电材料。 26. The method according to claim 23, wherein from the group consisting of HfO2, Al2O3 'ZrO2, Ti02, La203, Ta2O5' RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAIOx, HfSiON, ZrSiAlOx, HfSiA10x, HfSiAlON, composition and ZrSiAlON selecting the dielectric material.
27.如权利要求26所述的方法,其中所述介电材料为HfO2或A1203。 27. The method according to claim 26, wherein said dielectric material is HfO2 or A1203.
28.如权利要求23所述的方法,其中所述沉积的半导体材料包含硅、锗、或硅-锗合金。 28. The method according to claim 23, wherein the deposited semiconductor material comprises silicon, germanium, or a silicon - germanium alloy.
29.如权利要求23所述的方法,其中所述硅化物、硅化物-锗化物、或锗化物是a)硅化钛、硅化钛-锗化钛、或锗化钛,或b)硅化钴、硅化钴-锗化钴、或锗化钴。 Germanium, titanium silicide, cobalt, titanium, or germanium, or b), - 29. A method as claimed in claim 23, wherein said suicide, silicide - germanide or germanide of a) titanium silicide, titanium silicide, cobalt silicide - germanium, cobalt, germanium, or cobalt.
30.如权利要求23所述的方法,其中将所述相连式p-1-n 二极管安置于第一导体与第二导体之间,且其中将所述介电材料层安置于a)所述相连式p-1-n 二极管与所述第一导体之间或b)所述相连式p-1-n 二极管与所述第二导体之间。 30. The method according to claim 23, wherein said formula is connected to p-1-n diode is disposed between the first and second conductors, and wherein said dielectric material layer is disposed on a) the formula is connected between the p-1-n diode and the first conductor or b) is connected between the p-1-n type diode and the second conductor.
31.如权利要求30所述的方法,其中通过在所述第一导体与所述第二导体之间施加编程电压来实现所述使所述介电材料层的所述部分经受介电击穿的步骤。 31. A method according to claim 30, wherein the programming voltage is applied between the first conductor and the second conductor is achieved so that the portion of the said layer of dielectric material is subjected to dielectric breakdown by a A step of.
32.如权利要求31所述的方法,其中所述编程电压不超过8伏。 32. The method according to claim 31, wherein the programming voltage is not more than 8 volts.
33.如权利要求30所述的方法,其中将所述相连式p-1-n二极管垂直定向,并垂直安置于所述第一导体之间及所述第二导体之间,且其中所述第二导体在所述第一导体上方。 33. The method according to claim 30, wherein said formula is connected to p-1-n diode is oriented vertically and perpendicularly disposed between the first conductor and the second conductor, and wherein said the second conductor is above the first conductor.
34.如权利要求33所述的方法,其中所述形成所述相连式p-1-n 二极管的步骤包含: 形成所述第一导体; 在所述形成所述第一导体的步骤之后,在所述第一导体上方沉积半导体层堆叠; 在单个图案化步骤中以柱的形式图案化及蚀刻所述半导体层堆叠;及在所述图案化及蚀刻所述半导体层堆叠的步骤之后,在所述柱上方形成所述第二导体。 34. The method according to claim 33, wherein said step of forming said formula is connected to p-1-n diode, comprising: forming the first conductor; after said step of forming said first conductor, in the first conductor is deposited over the semiconductor layer stack; patterned and etched to form the semiconductor layers stacked in a single column patterning step; and after said step of patterning and etching the semiconductor layer stack, in the said second side forming said column conductor.
35.如权利要求23所述的方法,其中在所述使所述介电材料层的所述部分经受介电击穿的步骤期间编程所述存储器单元。 35. The method according to claim 23, wherein said portion of said layer of dielectric material is subjected during the step of programming the memory cell dielectric breakdown.
36.如权利要求23所述的方法,其中所述半导体材料是多晶的。 36. The method according to claim 23, wherein said semiconductor material is polycrystalline.
37.一种用于在衬底上方单片地形成第一存储器层级的方法,所述方法包含: 在所述衬底上方形成多个平行且共面的第一导体,所述第一导体沿第一方向延伸; 在所述第一导体上方形成多个垂直定向的相连式p-1-n 二极管,所述相连式p-1-n 二极管包含与硅化物、硅化物-锗化物、或锗化物层接触而结晶的半导体材料; 形成多个平行且共面的第二导体,所述第二导体在所述相连式P-1-n 二极管上方,所述第二导体沿不同于所述第一方向的第二方向延伸,每一相连式P-1-n 二极管垂直安置于所述第一导体中的一者与所述第二导体中的一者之间;及形成多个介电破裂反熔丝,每一介电破裂反熔丝安置于所述相连式P-1-n 二极管中的一者与所述第一导体中的一者之间或所述相连式p-1-n 二极管中的一者与所述第二导体中的一者之间, 其中所述介电破裂反熔丝包含介电材料 37. A method for the substrate monolithically formed above the first memory level, the method comprising: forming a plurality of parallel and co-planar first conductors over the substrate, along the first conductor extending in a first direction; forming connected formula p-1-n diode plurality of vertically oriented above the first conductor, connected to the p-1-n type diode comprising silicides, silicide - germanium compound, or germanium layer of semiconductor material is crystallized in contact; a second plurality of conductors are formed parallel to and coplanar, said second conductor P-1-n diode is connected to the above, the second direction different from said first conductor a direction extending in a second direction, each connected to the formula P-1-n diode vertically disposed between the first conductor and the second conductor one of one; and forming a plurality of dielectric rupture anti-fuse, each dielectric rupture antifuse is disposed between the coupled formula P-1-n diode of one of said first conductor is connected to one or the formula p-1-n diode between the one and the second conductor of one, wherein the dielectric rupture antifuse comprising a dielectric material ,所述介电材料具有大于8的介电常数;且其中所述介电破裂反熔丝中的每一者由一沉积工艺形成,其厚度为50埃或更少,且安置于第一金属性层和第二金属性层之间。 The dielectric material having a dielectric constant greater than 8; and wherein each of the dielectric rupture antifuse is formed by a deposition process, a thickness of 50 angstroms or less, and is disposed in a first metal between the metal layer and the second layer.
38.如权利要求 37 所述的方法,其中从由HfO2, Al2O3' ZrO2, TiO2' La203、Ta2O5' RuO2,ZrSiOx, AlSiOx, HfSiOx、HfAIOx、HfSiON、ZrSiAlOx, HfSiA10x、HfSiAlON、及ZrSiAlON 组成的群组中选择所述介电材料。 38. The method according to claim 37, wherein from the group consisting of HfO2, Al2O3 'ZrO2, TiO2' La203, Ta2O5 'RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAIOx, HfSiON, ZrSiAlOx, HfSiA10x, HfSiAlON, composition and ZrSiAlON selecting the dielectric material.
39.如权利要求37所述的方法,其中所述半导体材料包含硅、锗、及/或硅-锗合金。 39. The method according to claim 37, wherein the semiconductor material comprises silicon, germanium, and / or a silicon - germanium alloy.
40.如权利要求37所述的方法,其中a)将所述介电破裂反熔丝安置于所述二极管下方且将所述硅化物、硅化物-锗化物、或锗化物层安置于所述二极管上方。 40. The method according to claim 37, wherein a) the dielectric rupture antifuse is disposed below the diode in the silicide and silicide - germanide or germanide layer disposed on the diode above.
41.如权利要求37所述的方法,其中所述衬底包含单晶硅。 41. The method according to claim 37, wherein the substrate comprises monocrystalline silicon.
42.如权利要求37所述的方法,其中在所述第一存储器层级上方单片地形成至少第二存储器层级。 42. The method according to claim 37, wherein forming at least a second memory level above the first memory level monolithically.
43.一种用于在衬底上方形成单片三维存储器阵列的方法,所述方法包含: a)在所述衬底上方单片地形成第一存储器层级,所述第一存储器层级通过包含以下步骤的方法形成: i)形成沿第一方向延伸的多个平行且共面的第一导体; ii)形成沿不同于所述第一方向的第二方向延伸的多个平行且共面的第二导体,所述第二导体在所述第一导体上方; iii)形成由沉积的半导体材料形成的多个垂直定向的相连式P-1-n 二极管,所述沉积的半导体材料与硅化物、硅化物-锗化物、或锗化物层接触而结晶,每一二极管垂直安置于所述第一导体中的一者与所述第二导体中的一者之间; iv)形成由具有大于8的介电常数的介电材料形成的多个介电破裂反熔丝;其中所述介电破裂反熔丝中的每一者由一沉积工艺形成,其厚度为50埃或更少,且安置于第一金属性层和第二金属性层之间 43. A method for forming a monolithic three dimensional memory array over the substrate, the method comprising: a) forming a first memory level monolithically in the substrate above the first memory level comprising by forming method steps: i) forming a plurality of parallel extending in a first direction and a first conductor of the coplanar; ii) forming a second section extending in a direction different from the first direction, a plurality of parallel and co-planar second conductor, said second conductor is above the first conductor; forming a plurality of vertically oriented connected formula P-1-n diode is formed of a semiconductor material deposited III), the deposited semiconductor material and silicides, suicide - germanide or germanide layer is crystallized in contact with, each diode vertically disposed between said first conductor and said second conductor is one of one; IV) is formed from greater than 8 a plurality of dielectric permittivity of the dielectric material forming the rupture antifuse; wherein each of said dielectric rupture antifuse is formed by a deposition process, a thickness of 50 angstroms or less, and is disposed between the first metal layer and the second metal layer ;及v)形成多个存储器单元,每一存储器单元包含串联布置的所述二极管中的一者及所述介电破裂反熔丝中的一者;及b)在所述第一存储器层级上方单片地形成第二存储器层级。 ; Said diode and v) forming a plurality of memory cells, each memory cell comprises a series arrangement of one and the dielectric rupture antifuse of one; and b) above the first memory level a second memory level monolithically formed.
44.如权利要求 43 所述的方法,其中从由HfO2, Al2O3' ZrO2, TiO2' La203、Ta2O5' RuO2,ZrSiOx, AlSiOx, HfSiOx、HfAIOx、HfSiON、ZrSiAlOx, HfSiA10x、HfSiAlON、及ZrSiAlON 组成的群组中选择所述介电材料。 44. The method according to claim 43, wherein from the group consisting of HfO2, Al2O3 'ZrO2, TiO2' La203, Ta2O5 'RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAIOx, HfSiON, ZrSiAlOx, HfSiA10x, HfSiAlON, composition and ZrSiAlON selecting the dielectric material.
CN 200780042606 2003-12-03 2007-11-13 P-I-N diode crystallized adjacent to silicide in series with a dielectric antifuse and methods of forming the same CN101553925B (en)

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