CN101552883B

CN101552883B - Electronic apparatus, dispersion adjustment method of ic internal component section of electronic apparatus and ic

Info

Publication number: CN101552883B
Application number: CN2009101302224A
Authority: CN
Inventors: 青木裕; 新桥龙男
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 2008-03-31
Filing date: 2009-03-26
Publication date: 2011-10-05
Anticipated expiration: 2029-03-26
Also published as: EP2107687B1; JP2009246854A; CN101552883A; US8032101B2; US20090244397A1; EP2107687A3; EP2107687A2; JP5029467B2

Abstract

An electronic apparatus includes: a first integrated circuit including an internal component section capable of being adjusted with adjustment data, a nonvolatile memory in which beforehand acquired adjustment data of a result of adjustment carried out in advance for the internal component section are stored, and an interface section having a data transfer function of transferring the beforehand acquired adjustment data read out from the nonvolatile memory to the outside and a data storage function of storing actual use adjustment data sent from the outside and supplying the stored actual use adjustment data to the internal component section; and a second integrated circuit including a signal processor, to which the interface section of the first integrated circuit is connected.

Description

The dispersion adjustment method and the integrated circuit of the IC interior building block of electronic equipment, electronic equipment

The application comprises 2008-093575 number relevant theme of Japanese patent application JP of submitting in Japan Patent office with on March 31st, 2008, by reference its full content is incorporated into this.

Technical field

The present invention relates to electronic equipment, as dispersion (dispersion) control method and the IC of the inner building block of IC (integrated circuit) of TV-set broadcasting receiver, electronic equipment.

Background technology

For example, the leading section of the tuner of TV-set broadcasting receiver needs various types of adjustings, as adjusting to the gain of the tuned frequency of tuning circuit or tracking filter, and the adjusting that the image disruption of the band pass filter that is used for the image intermediate frequency is removed characteristic.

For example, if varicap is incorporated among the IC, characteristic is even between these diodes usually.Yet owing to coil can not be incorporated among the IC, disperseing can appear in the inductance between them.As a result, the breaking up of the branch of the inductance of syntonizing coil causes the trail-and-error of the tuned frequency of tuning circuit.

Although carry out the adjusting of trail-and-error in the prior art by manual adjustments air-core coil, can hinder miniaturization, because the size of air-core coil is very big.In addition, this adjusting has shortcoming, because it needs manual operation.

For example, solution example to the problem of just having described is disclosed in TOHKEMY Hei 11-168399 (hereinafter referred to as patent documentation 1).Especially, patent documentation 1 discloses a kind of receiver, the adjusting data (that is adjusting data of giving varicap to be supplied) that wherein will be used for the trail-and-error of each receive frequency are stored in the nonvolatile memory in advance and are used for regulating automatically trail-and-error.

Especially, in the actual reception machine, the tuning data that will offer varicap is regulated, made the receiving sensitivity of receiver can have maximum horizontal, to determine optimal value at each receive frequency.Then, this optimal value is regulated storage in nonvolatile memory as the trail-and-error that obtains in advance.Then, for user-selected any receive frequency, read accordingly acquisition in advance from nonvolatile memory and regulate data, with automatic adjusting trail-and-error.

Summary of the invention

Point out in passing, when preferably each user changes selected channel, all carry out to use being stored in the trail-and-error adjusting operation that obtaining in advance in the nonvolatile memory regulated data.Therefore, in the prior art, when electronic configurations is changed selected channel for making at every turn, all read and obtain to regulate data in advance with automatic adjusting trail-and-error from nonvolatile memory.

Therefore, the frequent memory access of carrying out nonvolatile memory, there are the following problems for electronic equipment: it be not preferred aspect the useful life of current drain and nonvolatile memory.

Therefore, expectation provides a kind of electronic equipment that can solve the problem of describing just now.

According to one embodiment of present invention, provide a kind of electronic equipment, having comprised: comprised first integrated circuit that can use the inside building block of regulating the data adjusting; Nonvolatile memory, data are regulated in the acquisition in advance that wherein stores the adjusting result that described inner building block is carried out in advance; And interface unit, have and to be sent to the data transport functions of outside and storage sends to it from the outside actual use adjusting data and the data storage function that the actual use adjusting data of being stored is offered described inner building block from the adjusting of the acquisition in advance data that described nonvolatile memory is read; With second integrated circuit, comprise signal processor as inner building block, the described interface unit of described first integrated circuit is connected to this signal processor.Described signal processor can be operated to receive the acquisition in advance of reading from described nonvolatile memory by described interface unit when the power connection and regulate data, received obtaining in advance regulated storage in the embedded memory of described signal processor, when power supply keeps connecting, read acquisition in advance and regulate data from described embedded memory, regulate data according to the acquisition in advance of reading and generate actual use adjusting data, then data are regulated in the actual use that is generated and send to described interface unit from described embedded memory.

In electronic equipment, when the power connection of this electronic equipment, read the acquisition in advance that is stored in the nonvolatile memory by signal processor and regulate data, and it is stored in the embedded memory of signal processor.Then, when the power supply of electronic equipment kept connecting, signal processor used the adjusting of the acquisition in advance data that are stored in the embedded memory that the inside building block of first integrated circuit is carried out and regulates.

According to another embodiment of the present invention, provide a kind of dispersion adjustment method that is used for the inner building block of IC of electronic equipment.This method may further comprise the steps: will regulate in the nonvolatile memory that data write first integrated circuit, first integrated circuit comprises: can use and regulate the inside building block that data are regulated; Described nonvolatile memory is wherein stored the adjusting result's that described inner building block is carried out in advance acquisition in advance and is regulated data; And interface unit, have and to be sent to outside data transport functions and to store the data storage function that the actual use that sends from the outside is regulated data and the actual use adjusting data of being stored offered described inner building block from the adjusting data that obtain in advance that described nonvolatile memory is read; Signal processor by second integrated circuit receives the adjusting of the acquisition in advance data of reading from described nonvolatile memory by interface unit when power supply is switched on, and received the acquisition in advance regulated storage in the embedded memory of signal processor, described second integrated circuit comprises the described signal processor as inner building block, and the interface unit of described first integrated circuit is connected to described signal processor; And by described signal processor, when keeping connecting, power supply reads the described data that obtain in advance to regulate from described embedded memory, regulate data according to the acquisition in advance of reading and generate actual use adjusting data, then data are regulated in the actual use that is generated and send to described interface unit from described embedded memory.

Go back an embodiment according to the present invention, a kind of integrated circuit is provided, comprise: integrated circuit, comprise signal processor as inner building block, the interface unit of another integrated circuit is connected to this signal processor, and this another integrated circuit comprises: can use and regulate the inside building block that data are regulated; Nonvolatile memory, data are regulated in the acquisition in advance that wherein stores the adjusting result that this inside building block is carried out in advance; And interface unit, have and to be sent to outside data transport functions and to store the data storage function that the actual use that sends from the outside is regulated data and the actual use adjusting data of being stored offered this inside building block from the adjusting data that obtain in advance that described nonvolatile memory is read.Described signal processor can be operated to receive the adjusting of the acquisition in advance data of reading from described nonvolatile memory by described interface unit when power supply is switched on, received obtaining in advance regulated storage in the embedded memory of described signal processor, when power supply keeps connecting, read acquisition in advance and regulate data from described embedded memory, regulate data according to the acquisition in advance of reading and generate actual use adjusting data, then data are regulated in the actual use that is generated and send to described interface unit from described embedded memory.

According to an also embodiment of the present invention, a kind of electronic equipment is provided, comprising: first integrated circuit comprises using and regulates the inside building block that data are regulated; And data storage part, be configured to that data are regulated in the actual use that sends from the outside and offer described inner building block; Nonvolatile memory, data are regulated in the acquisition in advance that wherein stores the adjusting result that the described inner building block of described first integrated circuit is carried out in advance; And second integrated circuit, comprising signal processor as inner building block, the described data storage part and the described nonvolatile memory of described first integrated circuit are connected to this signal processor.Described signal processor can be operated the adjusting of the acquisition in advance data of reading from described nonvolatile memory to receive when power supply is switched on, received obtaining in advance regulated storage in the embedded memory of described signal processor, when power supply keeps connecting, read acquisition in advance and regulate data from described embedded memory, regulate data according to the acquisition in advance of reading and generate actual use adjusting data, and the actual use adjusting data that generated are sent to described data storage part from described embedded memory.

Use described electronic equipment, can only when the power connection of electronic equipment, just carry out from nonvolatile memory and read the data of acquisition adjusting in advance.Therefore, the current drain of nonvolatile memory and the problem in useful life have been alleviated.

In conjunction with the accompanying drawings, according to following specification and claims, above and other purpose of the present invention, feature and advantage will become obvious, and in the accompanying drawing, identical parts or element are represented by identical reference symbol.

Description of drawings

Fig. 1 is the block diagram that the topology example summary of the TV-set broadcasting receiver of using a kind of form as electronic equipment of the present invention is shown;

Fig. 2 is the block diagram of concrete structure example of front-end circuit part that the TV-set broadcasting receiver of Fig. 1 is shown;

Fig. 3 is the figure of the adjusting data instance used in the front-end circuit part of illustration Fig. 2;

Fig. 4 is that illustration will be regulated the block diagram in the nonvolatile memory of the front-end circuit part that data write Fig. 2;

Fig. 5 is the block diagram that is illustrated in the processing when writing the adjusting data in the nonvolatile memory shown in Figure 2;

Fig. 6 is the diagram figure that illustration writes the data format of the adjusting data in the nonvolatile memory shown in Figure 2;

Fig. 7 A is to be illustrated in to regulate the diagram figure of the error correction encoding process example of data when writing in the nonvolatile memory shown in Figure 2 to 7C;

Fig. 8 A and 8B are the diagram figure that is illustrated in another error correction encoding process example when writing the adjusting data in the nonvolatile memory shown in Figure 2;

Fig. 9 A and 9B are the also diagram figure of an error correction encoding process example that is illustrated in when writing the adjusting data in the nonvolatile memory shown in Figure 2;

Figure 10 is the diagram figure of the memory contents management method of illustration nonvolatile memory shown in Figure 2;

Figure 11 is the flow chart of the memory contents management method of illustration nonvolatile memory shown in Figure 2;

Figure 12 A is the diagram figure that is illustrated in after the energized processing operation of the TV-set broadcasting receiver of Fig. 1 when the deenergization to 12C;

Figure 13 is illustrated in the flow chart that the processing of the TV-set broadcasting receiver of Fig. 1 is operated when deenergization after the energized;

Figure 14 is the figure that obtains to regulate data instance in advance of the illustration TV-set broadcasting receiver that is used for Fig. 1;

Figure 15 is that the TV-set broadcasting receiver of illustration Fig. 1 produces the actual flow chart that uses the processing example of regulating data according to obtaining to regulate data in advance;

Figure 16 is the figure that illustration is represented the expression formula of processing shown in Figure 15;

Figure 17 is that the TV-set broadcasting receiver of illustration Fig. 1 is regulated the figure that the interpolation of using when the data generation is actual uses the adjusting data is handled example according to acquisition in advance;

Figure 18 illustrates the block diagram that the TV-set broadcasting receiver that is used for Fig. 1 is carried out the needed building block of calibration;

Figure 19 is the flow chart of calibration operation handling process of the TV-set broadcasting receiver of illustration Fig. 1;

Figure 20 illustrates the block diagram that the TV-set broadcasting receiver that is used for Fig. 1 is carried out needed another building block example of calibration; And

Figure 21 illustrates the block diagram of using another electronic equipment of the present invention.

Embodiment

Below to be example with the TV-set broadcasting receiver be described electronic equipment according to the preferred embodiment of the invention.

Fig. 1 illustrates the topology example according to the part of the TV-set broadcasting receiver of the embodiment of the invention.With reference to Fig. 1, TV-set broadcasting receiver of the present invention has the simplified structure that adopts IC, and comprise front-end circuit IC 1, demodulator circuit IC 2, image output amplifier 3 and the system controller 4 that constitutes by microcomputer as its basic element of character.Demodulator circuit IC 2 comprises the signal processor 61 that is made of microcomputer.

Remote signal receiving-member 8 is connected to system controller 4.Remote signal receiving-member 8 receives remote signal from remote signal transmitter 9, and sends remote signal to system controller 4.4 pairs of received remote signals of system controller are analyzed, and user's operation of decision such as power on/off operations or channel handover operation is carried out suitable control in response to this determination result then.

The television broadcasting signal that television broadcasting signal reception antenna 5 is received by switching circuit 6 and antenna terminal pin T11 offers front-end circuit IC 1.TV-set broadcasting receiver comprises that also test signal generates parts 7, and it is used to generate the test signal that the adjusting of following front-end circuit parts 10 is partly calibrated.The test signal that generates parts 7 by switching circuit 6 and antenna terminal pin T11 self-test in the future signal offers front-end circuit IC 1.

In the present embodiment, in the adjusting portion timesharing of regulating described front-end circuit parts 10, for example when receiving channels switched, the signal processor 61 of demodulator circuit IC 2 entered calibration mode automatically, and it is carried out such as following calibration in this pattern.

When calibration mode began, signal processor 61 switched to switching circuit 6 test signal automatically and generates parts 7, and made test signal generation parts 7 begin to generate test signal.The test signal that generates parts 7 from test signal is the signal with specific single frequency.On the other hand, when calibration mode finished, signal processor 61 switches switching circuit 6 to wire back looked broadcast singal reception antenna 5 sides, to recover the state of received tv broadcast signal.

In the present embodiment, front-end circuit IC 1 comprises: front-end circuit parts 10, as the example that can use the intraware of regulating the data adjusting; Be used to store the nonvolatile memory 51 that obtains to regulate data in advance; And interface (I/F) parts 52.

Front-end circuit parts 10 comprise such as following a plurality of adjusting parts.During these regulate partly each all is conditioned at one or more adjustings items.Before manufacturing works shipments TV-set broadcasting receiver, will be at the adjusting item of the adjusting part of front-end circuit parts 10 and predetermined adjusting storage in nonvolatile memory 51, as obtaining to regulate data in advance.It is to be noted this TV-set broadcasting receiver is configured to, make after its shipment, also can additionally be stored in the nonvolatile memory 51 obtaining to regulate data in advance.

Nonvolatile memory 51 is connected to interface unit 52.Interface unit 52 is connected to the signal processor 61 of demodulator circuit IC 2 by the terminal supportor T14 of front-end circuit IC 1, and signal processor 61 has the form of following microcomputer.

In the case, in order to obtain to obtain in advance to regulate data, at first the use test device is regulated described adjusting data at the adjusting item of regulating part, thereby can obtain optimum state on the value of determining before the parameter that changes (in the present embodiment) channel frequency to be selected.Then, with the corresponding relation of corresponding parameter value (that is, frequency value corresponding), adjusting data in the time of will obtaining optimum state by signal processor 61 are regulated storage in nonvolatile memory 51 as obtaining in advance.

It may be noted that as another kind of and select that tester can not write acquisition in advance by signal processor 61 by interface unit 52 and regulate data.

In the present embodiment, the parameter value when regulating data in advance for storage is described needn't be for obtaining to obtain to regulate data in advance with the corresponding frequency of all channels to be selected, and can be the discrete parameter value.As described below, can regulate data according to the acquisition in advance that is stored in the nonvolatile memory, by the corresponding adjusting data of parameter value between interpolation processing acquisition and a plurality of discrete parameter value.

For example, under removing as the situation of regulating item with the image disruption of carrying out band pass filter from middle frequency band, for example, in two the highest or minimum VCO frequencies or carries out image disturb to be removed on other VCO frequencies of high frequency band or low-frequency band or UHF frequency band adjusting.Then, the adjusting data in the time of will obtaining optimum state with the relation related with frequency parameter are regulated storage in nonvolatile memory 51 as obtaining in advance.

Then, obtain in advance to regulate the error correction encoding process that data are subjected to signal processor as described below 61, be stored in then in the nonvolatile memory 51.

It may be noted that writing acquisition in advance by interface unit 52 at tester regulates under the data conditions, tester is carried out the error correction encoding process that obtains to regulate data in advance.

Be stored in some the adjusting data that do not change in the adjusting of the acquisition in advance data in the nonvolatile memory 51 with parameter such as frequency, if be subjected to the error correction encoding process, can former state ground offer front-end circuit parts 10 as the practical adjustments data some regulate parts.

Yet, if attempt to regulate data (it is used channel frequency as parameter) for all parameter value storages are main, so as mentioned above must the storage mass data.Therefore, as mentioned above, storage is only regulated data at a spot of acquisition in advance of discrete parameter value.Therefore, in the case, to regulate data in advance and be not that former state offers front-end circuit parts 10 that each regulates the practical adjustments data of part, but handling the master data of using when producing the practical adjustments data by interpolation as the signal processor of the employing microcomputer form of following demodulator circuit IC 2.

Read the acquisition in advance that is stored in the nonvolatile memory 51 according to interface unit 52 from the request of reading of signal processor 61 receptions of demodulator circuit IC 2 and regulate data.Interface unit 52 has according to this request of reading will regulate the function that data send signal processor 61 to from the acquisition in advance that nonvolatile memory 51 is read.

As described below, signal processor 61 is regulated data according to the acquisition in advance of reading from nonvolatile memory 51 and is produced actual use adjusting data, and uses the adjusting data to send to front-end circuit IC 1 reality.Interface unit 52 has following function: receive actual the use from signal processor 61 and regulate data, use the adjusting storage in embedded register wherein reality, reality is used regulated each adjusting part that data offer front-end circuit parts 10 then.

Front-end circuit parts 10 convert the television broadcasting signal that receives to intermediate frequency signal.Then, front-end circuit parts 10 send to demodulator circuit IC 2 by terminal supportor T12 with intermediate frequency signal.

In the present embodiment, demodulator circuit IC 2 comprises demodulator circuit parts 60 and the above-mentioned signal processor 61 as microcomputer that produces picture output signal according to intermediate frequency signal.Demodulator circuit IC 2 also comprises testing circuit 62, AGC voltage generation circuit 63 and the amplifier regulation voltage generative circuit 64 that is used for detecting at calibration mode calibration result.

To offer demodulator circuit parts 60 from the intermediate frequency signal of front-end circuit IC1 by terminal supportor T21.The intermediate frequency signal demodulation of 60 pairs of inputs of demodulator circuit parts offers image output amplifier 3 by terminal supportor T22 with picture output signal then to produce picture output signal.

Signal processor 61 also is connected to system controller 4 via terminal supportor T24 via the interface unit 52 that terminal supportor T23 is connected to front-end circuit IC 1.It may be noted that in the present embodiment, will obtain to regulate data in advance by terminal supportor T24 and send to signal processor 61 that signal processor 61 is carried out by interface unit 52 and will be obtained to regulate processing in the data write non-volatile memory 51 in advance then.

The definite signals of 62 pairs of testing circuits are carried out and are detected, and are used at calibration mode or when determining to obtain to regulate data in advance, and whether data are regulated in each actual use of regulating part of determining to offer front-end circuit parts 10 is optimum.Testing circuit 62 sends definite signal of expression testing result to signal processor 61.

Under calibration mode, signal processor 61 will be according to determining that the optimal adjustment data value that signal produces sends to interface unit 52, to be stored in interface unit 52.Then, when calibration mode finished, signal processor 61 switched to television broadcasting signal reception antenna 5 sides with switching circuit 6, and stopped to generate parts 7 generation test signals from test signal.

Signal processor 61 has carries out the function that writes/read visit to nonvolatile memory 51, and to carrying out error correction and decoding from the adjusting of the acquisition in advance data of nonvolatile memory 51 acquisitions to produce the function of actual use adjusting data.The function that produces actual use adjusting data comprises by interpolation regulates the function that data produce reality use adjusting data from acquisition in advance, and carries out aforesaid calibration to produce the function of optimum actual use adjusting data.

The AGC voltage generation circuit 63 of demodulator circuit IC 2 produces AGC voltage, and AGC voltage is used for controlling in response to the input signal of demodulator circuit parts 60 gain adjusting circuit of front-end circuit parts 10.Under calibration mode, the gain adjusting circuit of front-end circuit parts 10 produces fixedly AGC voltage, makes to obtain fixed gain.AGC voltage generation circuit 63 in the present embodiment is made of PWM (pulse width modulation) signal generating circuit.

Under calibration mode, thereby signal processor 61 is carried out the AGC control signal that 60 generations of demodulator circuit parts are not exported in transformation, but output is used for fixing the control signal of gain to AGC voltage generation circuit 63.AGC voltage generation circuit 63 provides by terminal supportor T25 and terminal supportor T13 forward end circuit block 10 and uses described control signal to regulate the AGC voltage of its pulse duration.Subsequently, carry out the AGC control of intermediate frequency signal as described below.

And then amplifier regulation voltage generative circuit 64 generates the amplifier gain regulation voltage that will offer image output amplifier 3.This amplifier regulation voltage generative circuit 64 also is made of the pwm signal generative circuit in the present embodiment.

From the picture output signal of image output amplifier 3 outputs are analog signals, and must export with accurate levels according to its character.Yet, owing to there is the dispersion of demodulator circuit IC 2, as the dispersion of each resistive element of the dispersion of the dispersion of D/A converter among the demodulator circuit IC 2 or supply voltage, image output amplifier 3 and circuit, so picture output signal not necessarily is output by accurate levels.

In the prior art, variable resistance is connected to image output amplifier 3, makes the output level of picture output signal to drop in the prescribed limit.Therefore, this countermeasure is owing to using variable resistance to have the problem of cost of parts, and has another problem of regulating cost because a lot of times of needs be regulated.

Consider the problem of this countermeasure, in the present embodiment, image output amplifier 3 is made of variable gain amplifier, and as mentioned above the amplifier regulation voltage generative circuit 64 that is made of the pwm signal generative circuit is set in demodulator circuit IC 2.The adjusting data that will be used to regulate the pulse duration of pwm signal to be exported offer amplifier regulation voltage generative circuit 64 from signal processor 61.Amplifier regulation voltage generative circuit 64 offers image output amplifier 3 by the amplifier gain regulation voltage that terminal supportor T26 will use the adjusting data to regulate its pulse duration.Therefore, will drop in the prescribed limit from the output level control of the picture output signal of image output amplifier 3.

Offering the adjusting storage of amplifier regulation voltage generative circuit 64 the nonvolatile memory 51 of front-end circuit IC 1 from signal processor 61.Signal processor 61 obtains to be used for the adjusting data of the gain-adjusted of image output amplifier 3 from nonvolatile memory 51, and should regulate data and offer amplifier regulation voltage generative circuit 64.

Before factory's shipment TV-set broadcasting receiver, by the use test device output level of the picture output signal of image output amplifier 3 is regulated to drop in the prescribed limit, determine the gain-adjusted data of image output amplifier 3.Then, before factory shipment TV-set broadcasting receiver, with the gain-adjusted data determined together with the above-mentioned adjusting data write non-volatile memory 51 that is used for front-end circuit IC 1.

Especially, in the present embodiment, not only will be used for the adjusting part of front-end circuit IC 1 the adjusting data, also will be used for the nonvolatile memory 51 of the adjusting storage of other circuit at front-end circuit IC 1.In addition, because demodulator circuit IC 2 comprises signal processor or microcomputer, so all the adjusting data in the nonvolatile memory 51 are read and obtained to be stored in to signal processor.Then, signal processor 61 applies predetermined process to the adjusting data that obtain as required, will regulate data then and offer corresponding target part.

Therefore, under situation about need regulate to any other circuit block except that front-end circuit IC 1, except being used for the adjusting data of image output amplifier 3, can also adjusting data write non-volatile memory 51 with necessity in.In the case, by following state each is regulated storage in nonvolatile memory 51, promptly signal processor 61 can be discerned and regulate data and with which parts (as front-end circuit parts 10 or image output amplifier 3) be associated.

[specific example of front-end circuit IC 1]

Fig. 2 illustrates the specific example of the front-end circuit IC 1 (especially being front-end circuit parts 10) in the present embodiment.

Country variant uses various frequencies or channel to carry out television broadcasting, and NTSC system, PAL system, SECAM-system etc. can be used as vitascan.In addition, also there are analog broadcasting and digital broadcasting.

Therefore, below seemingly a kind of countermeasure likely: the received signal system area of television broadcasting is divided into the front-end circuit that is used for receiving television broadcasting and exports intermediate frequency signal and is used to handle the output of front-end circuit and the baseband processing circuitry of output color picture signal and voice signal.This countermeasure has solved the difference of the broadcast system of television broadcasting.

Fig. 2 illustrates and is configured in each country and the difference of the forms of broadcasting example of the front-end circuit of receiving television broadcasting irrespectively.The front-end circuit of Fig. 2 will be divided into 3 frequency bands in the frequency that country variant is used for television broadcasting, comprise

(A) 46 to 147MHz (VHF-L frequency band),

(B) 147 to 401MHz (VHF-H frequency band), and

(C) 401 to 887MHz (UHF frequency band),

Thereby can change the frequency that to use according to the target channel in each frequency acceptance band.

With reference to Fig. 2, frame 1 expression that chain line centers on is formed the front-end circuit of monolithic IC as mentioned above.

The broadcast wave signal of antenna receiving television broadcasting optionally offers antenna tuning circuit 12A to 12C to terminal supportor T11 with the received signal of the broadcast wave signal that receives by switching circuit 11.In the case, antenna tuning circuit 12A is ready to (C) for above frequency acceptance band (A) respectively to 12C.Electric capacity that antenna tuning circuit 12A each in the 12C all changes tuning capacitor to be changing tuned frequency, thereby is tuned to the received signal of target frequency or channel.

By high-frequency amplifier circuit 13A to 13C then by inter-stage tuning circuit 14A to 14C, will offer switching circuit 15 to the received signal of 12C from antenna tuning circuit 12A respectively.Therefore switching circuit 15, extracts the received signal SRX of object frequency acceptance band being under the situation of interlocked relationship by switch with switching circuit 11 from switching circuit 15.Then, the received signal SRX that extracts is offered mixer 21I and 21Q.

Although it may be noted that inter-stage tuning circuit 14A also is to form similarly to 12C with antenna tuning circuit 12A to 14C, inter-stage tuning circuit 14A is formed the demodulation tuning circuit.In addition, as described below, the tuning capacitor of tuning circuit 12A to 12C and 14A to 14C is embedded among the front-end circuit IC 1, but syntonizing coil is provided at the outside of front-end circuit IC 1.

VCO (voltage controlled oscillator) 31 forms the oscillator signal of preset frequency.VCO 31 is used to form oscillation signals according and constitutes the part of PLL circuit 30.Especially, the oscillator signal of VCO 31 is offered variable division circuit 32, oscillation signal frequency dividing is become the signal of 1/N (N is a positive integer) frequency by variable division circuit 32.Signal behind the frequency division is offered phase-comparison circuit 33.In addition, the clock of about frequency of 1 to 2MHz is offered waveshaping circuit 34 from the outside, clock division is become the signal of preset frequency f34 by waveshaping circuit 34 by terminal supportor T16.Signal behind the frequency division is offered phase-comparison circuit 33 as reference signal.

Then, the relatively output of phase-comparison circuit 33 is offered loop filter 35, loop filter 35 takes out the dc voltages, and its level changes in response to the phase difference between the output signal of the output signal of variable division circuit 32 and waveshaping circuit 34.This dc voltage is offered VCO 31 as the control voltage to frequency f 31.It may be noted that smmothing capacitor C11 is connected to loop filter 35 via terminal supportor T17 outside.

Therefore, the frequency of oscillation f31 of VCO 31 is provided by following formula

F31=Nf34 ... (formula 2)

Therefore, by using signal processor 61 control frequency dividing ratio N, can change the frequency of oscillation f31 of VCO 31 by system controller 4.For example, in response to frequency acceptance band and receive frequency or receiving channels, frequency of oscillation f31 is 1.8 to 3.6GHz.

Then, the oscillator signal of VCO 31 being offered variable division circuit 36, is the frequency of 1/M (for example, M=2,4,8,16 or 32) with this signal frequency split by variable division circuit 36.Equally, control the frequency dividing ratio M of variable division circuit 36 by signal processor 61 by system controller 4.

Then, will offer frequency dividing circuit 37 from the fractional frequency signal of variable division circuit 36, be signal SL0I and SL0Q by frequency dividing circuit 37 with signal frequency split, and it has the frequency of half and has mutually orthogonal phase place.Fractional frequency signal SL0I and SL0Q are offered mixer 21I and 21Q respectively as oscillation signals according.

At this, if

FL0: the frequency of fractional frequency signal SL0I and SL0Q

So

FL0＝f31/(2M)

＝N·f34/(2M)

＝F34·N/(2M)

Therefore, by changing frequency dividing ratio M and N, can on wide range, press preset frequency step-size change local oscillation frequency fL0.

In addition,

SRX: received signal to be received

SUD: image disruption signal

And, for simplicity,

SRX＝ERX·sinωRXt

The amplitude of ERX: received signal SRX

ωRX＝2πfRX

The centre frequency of fRX: received signal SRX

SUX＝EUD·sinωUDt

EUD: the amplitude of image disruption signal SUD

ωUD＝2πfUD

FUD: the centre frequency of image disruption signal SUD.

In addition, fractional frequency signal SL0I and SL0Q are set at

SL0I＝EL0·sinωL0t

SL0Q＝EL0·cosωL0t

EL0: the amplitude of fractional frequency signal SL0I and SL0Q

ωL0＝2πfL0

Yet, in the case, if

ωIF＝2πfIF

FIF: intermediate frequency.For example, 4 to 5.5MHz (depend on broadcast system and change).Then, under the situation of last heterodyne (heterodyne) system,

fRX＝fL0-fIF

fUD＝fL0+fIF

Therefore, mixer 21I and 21Q export following signal SIFI and SIFQ respectively.Especially, output signal SIFI and SIFQ

SIFI＝(SRX+SUD)×SL0I

＝ERX·sinωRXt×EL0·sinωL0t

+EUD·sinωUDt×EL0·sinωL0t

＝α{cos(ωRX-ωL0)t-cos(ωRX+ωL0)t}

+β{cos(ωUD-ωL0)t-cos(ωUD+ωL0)t}

SIFQ＝(SRX+SUD)×SL0Q

＝ERX·sinωRXt×EL0·cosωL0t

+EUD·sinωUDt×EL0·cosωL0t

＝α{sin(ωRX+ωL0)t+sin(ωRX-ωL0)t}

+β{sin(ωUD+ωL0)t+sin(ωUD-ωL0)t}

α＝ERX·EL0/2

β＝EUD·EL0/2。

Then, signal SIFI and SIFQ are offered low pass filter 22, it has than the wideer bandwidth of the occupied bandwidth of image intermediate frequency signal and sound intermediate frequency signal (it is for for example 6 arriving MHz).As a result, the signal component (and fractional frequency signal SL0I and SL0Q) of low pass filter 22 removals and angular frequency (ω RX+ ω L0) and (ω UD+ ω L0).Therefore, extract from low pass filter 22

SIFI＝αcos(ωRX-ωL0)t+βcos(ωUD-ωL0)t

=α cos ω IFt+ β cos ω IFt ... (formula 4)

SIFQ＝αsin(ωRX-ωL0)t+βsin(ωUD-ωL0)t

=-α sin ω IFt+ β sin ω IFt ... (formula 5).

Then, by following amplitude phase-correcting circuit 23 signal SIFI and SIFQ are offered complex bandpass filter 24, it is the leggy band pass filter.Complex bandpass filter 24 has following characteristic (a) and arrives (d):

(a) it has the frequency characteristic of band pass filter.

(b) it has Phase-Shifting Characteristics, with the phase shifts value of signal SIFI Be arbitrary value.

(c) it has Phase-Shifting Characteristics, similarly with the phase shifts value of signal SIFQ

(d) it has the dual band pass characteristic of frequency f 0 and another frequency-f0, and frequency f 0 and frequency-f0 be with respect to the zero frequency symmetry of its centre frequency of conduct of frequency axis, and can select in the dual band pass characteristic one by the relative phase between the input signal.

Therefore, as shown in the formula given, according to above (b) and (c), complex bandpass filter 24 postpones 90 ° with signal SIFQ with respect to signal SIFI:

SIFI=α cos ω IFt+ β cos ω IFt ... (formula 6)

SIFQ＝-α·sin(ωIFt-90°)+β·sin(ωIFt-90°)

=α cosIFt-β cos ω IFt ... (formula 7)

In brief, in signal SIFI and signal SIFQ, signal component α cos ω IFt has mutually the same phase place, and signal component β cos ω IFt has phases opposite.

Then, signal SIFI and SIFQ are offered level correction amplifier 25, by level correction amplifier 25 with they additions each other.As a result, extract signal SIF as described below from level correction amplifier 25.

Especially, extract

SIF＝SIFI+SIFQ

＝2α·cosωIFt

=ERXEL0cos ω IFt ... (formula 8).

The SIF that is extracted is exactly the intermediate frequency signal when heterodyne system receives received signal SRX on basis.Intermediate frequency signal SIF does not comprise image disruption signal SUD.The amplitude and the phase place that it may be noted that 23 couples of signal SIFI of amplitude phase-correcting circuit and SIFQ are proofreaied and correct, and make fully to satisfy formula 8, and promptly image disruption signal SUD can minimize.

And at this moment, the level of 25 couples of signal SIF of level correction amplifier is proofreaied and correct, and is different even make the level of signal SIFI and SIFQ depend on broadcast system, and following A GC characteristic (especially the beginning level of AGC etc.) can not change yet.

Then, by variable gain amplifier 26 that is used for AGC and the band pass filter 27 that is used for excision of dc component and aliasing, intermediate frequency signal SIF is outputed to terminal supportor T12.

Therefore,, can come select target frequency or channel according to formula 3 so if frequency dividing ratio M and N change, and if according to broadcast system the intermediate frequency signal SIF that outputs to terminal supportor T12 is carried out demodulation, target broadcasting can be enjoyed so.

In this way, use this front-end circuit parts 10, can handle from 46 to 887MHz wide frequency ranges by monolithic IC.In addition, can use the part of the quantity of minimizing to realize front-end circuit parts 10, and can on described wide frequency ranges, not worsen jamproof characteristic.In addition, front-end circuit parts 10 can be tackled the broadcast system difference between analog broadcasting and the digital broadcasting, perhaps tackle the difference of the broadcast system of different regions, the whole world.

In addition, the reception interference reduction of the harmonic wave of clock signal, the result has improved receiving sensitivity.Moreover owing to all circuit units except that capacitor C11 of PLL circuit 30 all can be formed on the chip, so the anti-interference of PLL circuit 30 is very strong thereby be not easy to be disturbed.In addition, have only inter-stage tuning circuit 14A to be connected respectively to high-frequency amplifier circuit 13A to 13C, so load is very light, and high-frequency amplifier circuit 13A is very low to the distorted signals of 13C to 14C.

[AGC example]

AGC voltage VAGC is formed by the AGC voltage generation circuit 63 of the demodulator circuit IC 2 of the next stage that is positioned at front-end circuit IC 1, and offers variable gain amplifier 26 as gain control signal via terminal supportor T13 and be used for AGC.Therefore, use this gain control signal to carry out common AGC, i.e. the AGC of intermediate frequency signal.

In addition, for example, if the level of target received signal SRX is too high or comprise the disturbing wave signal of high level in received signal SRX, then common AGC can not tackle it.Therefore, will offer level sensitive circuit 41, and come detection signal SIFI and the level of SIFQ before AGC amplifier 26 is carried out AGC whether to surpass predetermined value by level sensitive circuit 41 from the signal SIFI and the SIFQ of low pass filter 22 outputs.Then, the detection signal of level sensitive circuit 41 and the AGC voltage VAGC of terminal supportor T15 are offered add circuit 42, the addition output with add circuit 42 offers delay AGC voltage forming circuit 43 then, forms by circuit 43 to postpone AGC voltage VDAGC.To postpone AGC voltage VDAGC as gain control signal offer high-frequency amplifier circuit 13A to 13C carry out to postpone AGC.

Therefore, owing to can realize optimum AGC operation, therefore can from digital broadcasting, analog broadcasting or numeral and analog broadcasting, receive the broadcasting of expectation well according to the D/U of the intensity of the intensity of the signal that will receive and many signals that will can not receive.

[example of test and regulation voltage]

Offer linearity test circuit 44 from the signal SIFI and the SIFQ of low pass filter 22 outputs, by linearity test circuit 44 they are detected with level and smooth, to form the dc voltage V44 of the level of representing signal SIFI and SIFQ.V44 exports to terminal supportor T15 with dc voltage.

When test or adjusting front-end circuit IC 1, use the dc voltage V44 that exports to terminal supportor T15.For example, can use dc voltage V44 on wide frequency ranges, to check the level of input signal (that is received signal).Especially, be different from output, can on broadband, directly check along attenuation characteristic from antenna terminal pin T11 to the holding wire of mixer 21I and 21Q from the intermediate frequency filter of narrow-band.

In addition, to regulate antenna tuning circuit 12A to 12C and inter-stage tuning circuit 14A under the situation of 14C, if test signal is provided and the AGC voltage VAGC that will offer terminal supportor T13 is fixed to predetermined value, can carry out to follow the tracks of according to the variation of dc voltage V44 so and regulate to antenna terminal pin T11.In addition, can use numerical data to carry out the measurement of the characteristic of the adjusting of various functions and front-end circuit IC 1, and can carry out automatic adjusting and measure automatically.

[constant voltage circuit]

Front-end circuit IC 1 in the present embodiment comprises constant voltage circuit 53, provides supply voltage+VCC by terminal supportor T18 to constant voltage circuit 53.Constant voltage circuit 53 is utilized the constant voltage of the band gap of PN junction from supply voltage+VCC formation predetermined value, and the constant voltage that will form in this way offers the built-up circuit of front-end circuit IC 1.It may be noted that and to finely tune the output voltage of constant voltage circuit 53, and it is regulated storage in nonvolatile memory 51.The adjusting data that signal processor 61 obtains from nonvolatile memory 51 to be used to finely tune are regulated data to produce actual use, and use the adjusting data to offer constant voltage circuit 53 reality by interface unit 52.

Therefore, the output supply voltage of constant voltage circuit 53 is to the constant voltage after each front-end circuit IC 1 fine setting.Therefore, even form at MOSFET under the situation of built-up circuit, also can be set at quite high value to the supply voltage that offers these circuit.Therefore, performance that can maximum extracted MOSFET.

Use the structure of front-end circuit IC 1 shown in Figure 2, can receive as more than television broadcasting in 46 to the 887MHz frequency bands pointed out in (A) to (C) that provide.At this moment, because the centre frequency and the bandpass width of complex bandpass filter 24 are variable, therefore not only can handle the earthwave digital television broadcasting and the earthwave analog television broadcast of Japan, and can handle those television broadcastings beyond the Japan.

[being stored in the example of the adjusting data in the nonvolatile memory 51]

Fig. 3 illustrates the example of the adjusting data that are stored in the nonvolatile memory 51.As mentioned above, nonvolatile memory 51 is configured so that it not only stores the adjusting data of the adjusting part that is used to regulate front-end circuit IC 1 itself, and storage is used for removing the adjusting data of the circuit block the adjusting partly of front-end circuit IC 1.

At first, the adjusting adjusting data partly that are used to regulate front-end circuit IC 1 are described.

It is to be used to regulate the data of antenna tuning circuit 12A to 12C and inter-stage tuning circuit 14A to the filter passband of 14C that tracking filter is regulated data.Tracking filter is regulated data and is absorbed and be embedded in the capacitor of antenna tuning circuit 12A to 12C and inter-stage tuning circuit 14A to 14C and the dispersion of the coil of their outside connection.In this example, the configuration information that to regulate data are antenna tuning circuit 12A to 12C and inter-stage tuning circuit 14A to the peak frequency of the frequency band of the filter of 14C.

The IQ amplitude is regulated the adjusting data that data and IQ phase adjusted data are characteristics (especially image disruption removal characteristic) of being used to regulate the intermediate frequency filter.As regulating data, store each the adjusting data of a plurality of receiving channels frequencies of above-mentioned 3 frequency acceptance bands.In other words, be that adjusting data on the receiving channels frequency of a plurality of interruptions of running parameter are stored as the adjusting data with the receiving channels frequency.

In the present embodiment, a plurality of receiving channels frequencies of stored adjustment data also do not mean that all receiving channels frequencies of each frequency acceptance band, but mean the receiving channels frequency of the interruption on a plurality of receiving channels frequency intervals.It regulates the adjusting data of the receiving channels frequency of data according to storage in nonvolatile memory 51, handles by interpolation and determine not store the adjusting data that it regulates those receiving channels frequencies of data in nonvolatile memory 51.Also be applicable to following other adjusting data similarly.

VCO Current Regulation data are that the electric current that the dispersion owing to the internal resistance of the circuit that constitutes VCO produces is disperseed the adjusting data that absorb, to realize normally stable performance.

It is to set the adjusting data of the cut-off frequency of band pass filter 24 that the cut-off frequency of IF BPF is regulated data, and is used for the dispersion of the resistor and the capacitor of absorption band bandpass filter 24.The cut-off frequency of IFBPF is regulated the conversion that data also are used for the cut-off frequency of band pass filter 24 simultaneously.

It is the adjusting data that are used to set these 3 different cut-off frequencies of 6MHz/7MHz/8MHz that the cut-off frequency of IF BPF in the example shown in Figure 3 is regulated data, corresponding to the bandwidth BW of following 3 frequency acceptance bands.

Tuned frequency is provided with and regulates data is to set and regulate the tuned frequency of antenna tuning circuit 12A to 12C and inter-stage tuning circuit 14A to 14C, and stores at a plurality of receiving channels frequencies.

It is the adjusting data that are used for the gain-adjusted of level correction amplifier 25 that the level correction amplifier is regulated data, and absorbs the dispersion of resistor embedded in the level correction amplifier 25.

Regulator voltage is provided with and regulates data is adjusting data that the output voltage of constant voltage circuit 53 is finely tuned.

In the present embodiment, as the adjusting data of the circuit block except that the circuit block of front-end circuit IC 1 itself, store the gain-adjusted data that are used for image output amplifier 3 as mentioned above.As for the gain-adjusted data,, can store the adjusting data relevant with a plurality of receiving channels frequencies according to the needs on opportunity.

[regulating write (the comprising the error correction encoding process) of data]

Fig. 4 illustration is regulated the acquisition of data and will be regulated the processing of data write non-volatile memory 51.

With reference to Fig. 4, controlled plant parts 100 are adjusting parts, band pass filter or amplifiers of the tuning circuit of above-mentioned front-end circuit parts 10.As mentioned above, the regulating step before the television broadcasting signal receiving equipment of factory's shipment present embodiment, each of 200 pairs of controlled plant parts 100 of use test device regulated partly to carry out and regulated.Then, tester 200 obtains the adjusting data that each regulates item when obtaining optimum state by adjusting.The adjusting data that obtain regulating item are to obtain to regulate data in advance.In the case,, under each receiving channels frequency, carry out and regulate, regulate the adjusting data of acquisition when obtaining optimum state at each then for any adjusting item that will on a plurality of receiving channels frequencies, obtain its adjusting data.

Then, by the signal processor 61 of demodulator circuit IC 2 data write non-volatile memory 51 is regulated in the acquisition in advance that tester 200 obtains.At this moment, to regulate the error correction encoding process of the software of control assembly (CPU) 61a that data are subjected to signal processor 61 in advance, be written into then in the nonvolatile memory 51.

Especially, with reference to Fig. 5, regulate data and offer ECC (error-correcting code) encoder 61Ec being stored in acquisition in advance among the adjusting data buffering apparatus 200BF of tester 200, encoder 61Ec provides as the software processes function of the control assembly 61a of signal processor 61.

ECC encoder 61Ec produces GF (2 to the adjusting data of coming self-regulation data buffer device 200BF ⁸) on Reed-Solomon (RS) sign indicating number, then this RS sign indicating number is appended to the adjusting data.Then, according to the control command of signal processor 61, the acquisition in advance that ECC encoder 61Ec has added the RS sign indicating number is regulated in the data write non-volatile memory 51 by interface unit 52.

The form of the RS sign indicating number that uses in Fig. 6 illustration present embodiment.With reference to Fig. 6, regulating data is 3 page datas of 384 bytes, and each page or leaf all is made of 128 bytes.Each 127 byte to one page apply the RS sign indicating number.In addition, in the present embodiment, use 2 byte recoverable RS sign indicating numbers, and produce the parity check bit of 4 bytes and it is appended to the adjusting data (information data) of 123 bytes.

It may be noted that and be not that the data of acquisition adjusting in advance are divided into a plurality of pages the form that is used for each adjusting item is recorded in nonvolatile memory 51 with obtaining the adjusting data in advance, but will be recorded in 3 pages all adjusting of acquisition in advance data of regulating item, be these 3 pages and form and the additional error correcting codes.

Like this, below above-mentioned 3 pages adjusting data are called macrodata, and signal processor 61 is that the adjusting data are read by unit from nonvolatile memory 51 with the macrodata.Then, the macrodata of regulating data is subjected to the error correcting/decoding of error correcting/decoding device and handles, and the error correcting/decoding device provides as the software processes function of the control assembly 61a of signal processor 61.

After correctable error has been proofreaied and correct in the error correcting/decoding processing, will obtain to regulate storage in advance in the cache memory 61b of signal processor 61.If the adjusting data of reading from nonvolatile memory 51 comprise the mistake that can not proofread and correct, signal processor 61 is for example attempted reading from nonvolatile memory 51 again so.

It may be noted that as mentioned above in power supply opening, signal processor 61 uses the acquisition in advance that is stored among the cache memory 61b to regulate data and handles regulating partly to carry out to regulate.

As mentioned above, in the present embodiment, error-correcting code is appended to the acquisition in advance that is stored in nonvolatile memory 51 regulate data.Therefore, even when reading the storage data from nonvolatile memory 51, mistake occurs,, so they are proofreaied and correct if they are correctable errors.Therefore, improved the reliability that obtains to regulate data in advance.

In addition, in the present embodiment, error correcting/decoding is handled and needn't be carried out in providing the front-end circuit IC 1 of nonvolatile memory 51, and can comprise that the signal processor of the demodulator circuit IC 2 of signal processor carries out by script.Therefore, existence needn't be in front-end circuit IC 1 effect of signalization processor, in front-end circuit IC 1, because its structure is difficult to the signalization processor.

In the above description, use test device 200 by the single processing cycle carry out required acquisition that to regulate data in advance, to obtain to regulate the error correction coding of data in advance and will encode after the adjusting of acquisition in advance data write non-volatile memory 51 in.Yet, may not carry out the acquisition that obtains to regulate data in advance by the single processing cycle, in the case, need exchange joint number according to carrying out addition record.Below, description need be carried out the generation and the additional treatments of the error correction code data under the situation of this addition record to adjusting.

＜regulate data to add first example that writes with the ECC additional treatments

Fig. 7 A will regulate the additional write non-volatile memory 51 of data and this additional the write generation of fashionable error correction code data and first example of additional treatments to the 7C illustration.Although as above with reference to Fig. 6 described the error correction code data have the format structure of page unit, but at Fig. 7 A to 7C, for the purpose of convenient for example, with following form illustration macrodata unit, that is, it is divided into information data part (information data memory block) and odd even part (parity check bit memory block).Be applicable to the following second and the 3rd example similarly.

As seeing at Fig. 7 a and since nonvolatile memory 51 after just making not with anything, so be in complete idle condition.Obtain to obtain in advance to regulate data Seq-1 and will obtain to regulate processing in the data Seq-1 write non-volatile memory 51 then in advance in order under this state, to carry out use test device 200, if not considering to exchange the additional of joint number certificate writes, (1) will obtain to regulate the free area of data Seq-1 writing information data division in advance so, (2) are to comprising that the information data that obtains adjusting data Seq-1 in advance partly produces error correction code data ECC/Seq-1 and then it write the odd even part, as seeing at Fig. 7 B then.

Yet, know existence to be connected on first to regulate data Seq-1 in advance after additional writing obtain to regulate under the situation of data Seq-2 method that can not application drawing 7B in advance.This is because in case write the error correction code data midway, just can not write and the additional new error correction code data that writes the new data part correlation of data that comprises afterwards.

Therefore, in this first example, know that existence will be connected on first and obtain in advance to add after regulating data Seq-1 to write to obtain in advance to regulate under the situation of data Seq-2, carry out as the illustrated this processing of Fig. 7 C.Especially, with reference to Fig. 7 C, (1) under the situation of the generation of not execution error correcting code data, obtain in advance to regulate in the free area of data Seq-1 writing information data division with first, (2) obtain to regulate another free area of data Seq-2 writing information data division in advance with next.Then, based on comprising in advance the information data part that obtains to regulate data Seq-1 and Seq-2 assign to generation error correcting code data ECC/Seq-1 and ECC/Seq-2, then it is write in the odd even part, as seeing at Fig. 7 C.

＜regulate data to add second example that writes with the ECC additional treatments

Fig. 8 A will regulate the additional write non-volatile memory 51 of data and this additional the write generation of fashionable error correction code data and second example of additional treatments to the 8B illustration.In second example,, also can write and the additional relevant new error correction code data of new data part that writes data that comprises afterwards even write the error correction code data midway.

With reference to Fig. 8 A to 8B, in illustrated second example, for odd even is partly prepared additional storage, its quantity with to add after having write the error correction code data that to write the number of times of regulating data identical.In the example of Fig. 8 A and 8B, after having write the error correction code data, additional writing once regulated data.Therefore, odd even partly is divided into two parts that comprise first odd even part and second odd even part, makes to write two different error correction code datas.

Write the processing sequence first time that Fig. 8 A illustration obtains to regulate data in advance, itself and Fig. 7 C are illustrated basic identical.Yet for the first time error correction code data ECC 1ST (=ECC/Seq1,2) writes the first odd even part, and it is to be used for the zone that writes for the first time of odd even part.

First the first time that to regulate data in advance write handle sequence after, to handle sequence be shown in Fig. 8 B to writing next second time that obtains to regulate data in advance.Especially, (1) is with the free area that obtains to regulate data Seq-3 writing information data division in advance that writes for the second time.

Then, (2-1) based on comprising that the information data part branch that obtains adjusting data Seq-1, Seq-2 and Seq-3 in advance generates the code data of error correction for the second time ECC 2ND (=ECC/Seq-1,2,3), then it is write the second odd even part, it is to be used for the zone that writes for the second time of odd even part.

Can carry out following process (2-2) and replace said process (2-1).Especially, (2-2) based on comprising that the information data part and the code data of the error correction for the first time ECC 1ST that obtain adjusting data Seq-1, Seq-2 and Seq-3 in advance generate the code data of error correction for the second time ECC 2ND, then it is write the second odd even part, it is to be used for the zone that writes for the second time of odd even part.

According to the method for second example, odd even partly has the capacity of the error correction code data that is enough to write therein and regulate the number of times equal amount.Therefore, even in each regulating cycle, produce and additional error correcting code data, also can add writing the adjusting data.

＜regulate data to add the 3rd example that writes with the ECC additional treatments

Fig. 9 A will regulate the additional write non-volatile memory 51 of data and this additional the write generation of fashionable error correction code data and the 3rd example of additional treatments to the 9B illustration.In the 3rd example, same, even write the error correction code data midway, also can write and the additional relevant new error correction code data of new data part that writes data that comprises afterwards.

In this 3rd example, nonvolatile memory 51 has the n of comprising a memory block B1, B2 ..., the memory areas of Bn, each memory block all has the memory capacity that is used for a macro block.Then, first, second, third ... when acquisition acquisition adjusting in advance data will obtain to regulate data write non-volatile memory 51 then in advance, produce and write error correcting code data in each cycle of write cycle.

But, in this 3rd example, in each write cycle, write different memory blocks with the error correction code data with obtaining to regulate data in advance.In addition, during last write cycle, write the memory block of being write reading and regulate data from nonvolatile memory 51 by the acquisition in advance that signal processor 61 uses.

Especially, when writing for the first time the data of acquisition adjusting in advance, the information data part that obtains to regulate data Seq-1 write memory piece B1 in advance that will be used for writing for the first time, and with the odd even part that comprises the error correction code data ECC 1ST write memory piece B1 that the information data part that obtains to regulate data Seq-1 in advance is relevant.

Then, when writing for the second time the data of acquisition adjusting in advance, the acquisition in advance that will be used for writing is for the first time regulated data Seq-1 and is copied at memory block B2, as seeing at Fig. 9 B.What then, will be used for writing for the second time obtains to regulate the clear area that data Seq-2 writes same memory block B2 in advance.Then, based on comprising that in advance the information data part branch that obtains to regulate data Seq-1 and Seq-2 generates the code data of error correction for the second time ECC 2ND, and with the odd even part of its write memory piece B2.

It may be noted that in this 3rd example, the situation of (2-2) of same and above-mentioned second example is similar, not only,, generate the code data of error correction for the second time ECC 2ND also based on the error-correcting code section data that additionally comprises in the last operation cycle based on the information data part.

According to this 3rd example, with second example class seemingly, even in each regulating cycle, produce and additional error correcting code data, also allow to exchange joint number and write according to adding.

[the adjusting data before factory's shipment and adjusting data afterwards]

More than describe to relate to and regulate data from the acquisition in advance of write non-volatile memory before of factory's shipment TV-set broadcasting receiver.Yet same after factory's shipment, for example the operator can regulate an acquisition at certain and regulate data in user's environment for use, will obtain to regulate additionally write non-volatile memory of data in advance then.

In the present embodiment, also pay close attention to this factory's shipment adjusting data afterwards.Especially, in the present embodiment, nonvolatile memory 51 comprises this a plurality of storage pools (bank) as shown in figure 10, especially in the example of Figure 10, comprises 4 storage pool Bank1, Bank2, Bank3 and Bank4.

Storage pool Bank0 and storage pool Bank2 are as the memory block that obtains to regulate data in advance before factory's shipment.Simultaneously, storage pool Bank1 and storage pool Bank3 are as the memory block that obtains to regulate data in advance after factory's shipment.Then, as seeing, use storage pool Bank0 and storage pool Bank2 in pairs, and use storage pool Bank2 and storage pool Bank3 in pairs at Figure 10.

Like this, before factory loads and transports, the data of acquisition adjusting are in advance write the storage pool Bank0 of the memory block that is used for the factory's shipment adjusting of acquisition in advance data before and the storage pool Bank0 between the Bank2.

Simultaneously, permission will obtain to regulate data in advance and write one of storage pool Bank1 and Bank3, and storage pool Bank1 and Bank3 are configured for the memory block that obtains to regulate data in advance before factory's shipment.If the acquisition in advance after factory's shipment is regulated storage at storage pool Bank1, because being regulated data, the acquisition in advance before factory's shipment writes storage pool Bank0 so, if read the data of acquisition adjusting in advance from being in right storage pool Bank0 and Bank1, can not go wrong.

Yet,, under this state, the acquisition in advance before factory's shipment is not regulated storage at storage pool Bank2 if the acquisition in advance after factory's shipment is regulated storage at storage pool Bank3.Therefore, if the acquisition in advance after factory's shipment is regulated storage at storage pool Bank3, so the acquisition in advance before the shipment of the factory among the storage pool Bank0 is regulated the data copy and is stored in storage pool Bank2.Then, when storage is regulated in the acquisition in advance before the factory shipment at storage pool Bank2, the flag F B_2 that writes of this situation of expression is set at " 0 ", expression storage pool Bank2 is in the state of writing.

In addition, under this state, if the acquisition in advance after the factory shipment is regulated storage at storage pool Bank3, so signal processor 61 inquiry storage pool Bank2 write flag F B_2, to read and obtain to regulate data in advance from being in right storage pool Bank2 and Bank3.

Figure 11 is illustrated in the definite routine of handling of use storage pool of signal processor 61 in the case.

With reference to Figure 11, at step S101, signal processor 61 read from nonvolatile memory 51 in advance obtain to regulate data before, that reads storage pool Bank2 writes flag F B_2.Then, signal processor 61 determines at step S102 whether this writes flag F B_2 is " 0 ".

If determine that at step S102 this writes flag F B_2 is not " 0 ", then signal processor 61 is determined to read the data of acquisition adjusting in advance at step S103 from being in right storage pool Bank0 and Bank1.

On the other hand, if determine that at step S102 this writes flag F B_2 is " 0 ", then signal processor 61 is determined to read the data of acquisition adjusting in advance at step S104 from being in right storage pool Bank2 and Bank3.

By changing before the factory shipment in this way and the memory block of afterwards nonvolatile memory 51, without any troublesomely with before factory's shipment and acquisition in advance afterwards regulate the data write non-volatile memory.It may be noted that equally obtaining in advance after factory's shipment regulated data and be stored in nonvolatile memory 51 with the above-mentioned form that has error-correcting code.

[disconnect up to power supply after the power connection, use the adjusting operation that obtains to regulate data in advance]

When each user changes the channel of selecting on TV-set broadcasting receiver, carry out to use being stored in the adjusting operation that obtaining in advance in the nonvolatile memory 51 regulated data.

In the case, if consider the useful life of current drain and nonvolatile memory 51, change selected channel is not preferred from signal processor 61 visit nonvolatile memories 51 all so at every turn.

In the present embodiment, for address this problem, but TV-set broadcasting receiver is configured so that only ought make the power supply time spent (that is, when energized) just carry out from 51 pairs of visits of reading that obtain to regulate data in advance of nonvolatile memory.

Figure 12 A illustrates the configuration of describing just now to 12C.Especially, shown in the dash area among Figure 12 A, when making that power supply can be used for TV-set broadcasting receiver, signal processor 61 sends at the transmission request that obtains to regulate data in advance to nonvolatile memory 51, obtains to regulate data in advance to read from nonvolatile memory 51.Then, signal processor 61 will obtain the adjusting storage at embedded cache memory 61b wherein in advance from what nonvolatile memory 51 obtained.

In the operating period that the power supply maintenance of TV-set broadcasting receiver is connected, shown in the dash area of Figure 12 B, the control assembly 61a of signal processor 61 uses the acquisition in advance that is stored in cache memory 61b to regulate data and produces actual use adjusting data.Then, the controlled plant part 100 that data offer front-end circuit parts 10 is regulated in the control assembly 61a of the signal processor 61 actual use that will produce.At this moment, the control assembly 61a of signal processor 61 also carries out according to the adjusting data that obtain in advance that are stored in cache memory 61b and handles the processing that produces actual use adjusting data by interpolation.

If cut off the power supply of TV-set broadcasting receiver, so as seeing at Figure 12 C, the adjusting of the acquisition in advance data that are stored among the cache memory 61b of signal processor 61 can disappear.Then, if make that once more power supply can be used for TV-set broadcasting receiver, set up the state of Figure 12 A so once more.Like this, repeat the aforesaid this sequence of operation.

The power supply that Figure 13 is illustrated in signal processor 61 is switched on the processing operating process when it is disconnected afterwards.

At step S201, signal processor 61 monitors that instruction from system controller 4 is to determine whether to have connected the power supply of TV-set broadcasting receiver.Then, if determine to have connected power supply, signal processor 61 sends at the request of reading that obtains to regulate data in advance to nonvolatile memory 51 by the interface unit 52 of front-end circuit IC 1 at step S202 so.

Then, at step S203, signal processor 61 obtains to regulate data from the acquisition in advance that nonvolatile memory 51 is read by interface unit 52, and data execution error correction decoder is regulated in the acquisition in advance that obtains handled.Then, signal processor 61 will be regulated storage at embedded cache memory 61b wherein by the acquisition in advance of error correction error recovery at step S204.

Then, signal processor 61 receives for example information of last channel by system controller 4, will be used to select the information of last channel to send to front-end circuit IC 1 then.As mentioned above, this information comprises that the information of frequency dividing ratio of the frequency dividing circuit 32 that will offer PLL circuit 30 and 36 and the actual use that is used for the adjusting part of front-end circuit parts 10 regulate data.Especially, signal processor 61 produces the actual use adjusting data relevant with last channel according to the adjusting data that obtain in advance that are stored among the cache memory 61b.At step S205, when producing reality use adjusting data, signal processor 61 is carried out interpolation as required and is handled, as the linear interpolation of using the data of acquisition adjusting in advance to carry out.

Then, at step S206,61 pairs of essential adjusting items of signal processor are carried out calibration process.When carrying out calibration process, signal processor 61 generates parts 7 with test signal and is controlled to be mode of operation generating aforesaid test signal, and switching circuit 6 is switched to test signal generates parts 7 sides.After calibration process finished, signal processor 61 generated parts 7 with test signal and is controlled to be non-operating state stopping the generation of test signal, and switching circuit 6 is switched to reception antenna 5 sides.Therefore, TV-set broadcasting receiver enters the accepting state of last channel.

Then, at step S207,61 pairs of information of cutting off the electricity supply from the expression of system controller 4 of signal processor are monitored, and whether carry out the dump operation to determine the user.Then, at step S208, if determine that at step S207 the user does not carry out the dump operation, 61 pairs of information from the expressions change selected channel of system controller 4 of signal processor are monitored so, whether switch selected channel to determine the user.

If determine that at step S208 the user do not switch selected channel, then signal processor 61 turns back to step S207 with processing, with the step process that repeats to begin with step S207.

Then, if determine that at step S208 the user switched selected channel, the channel information after then signal processor 61 switches by system controller 4 receiving channelss, and will be used to select the information of the channel after selected channel switches to send to front-end circuit IC 1.This information comprises that the information of frequency dividing ratio of the frequency dividing circuit 32 that will offer PLL circuit 30 and 36 and the actual use that is used for the adjusting part of front-end circuit parts 10 regulate data.Especially, signal processor 61 produces the actual use relevant with the channel after the selected channel switching according to the adjusting of the acquisition in advance data that are stored in cache memory 61b and regulates data.At step S209, produce actual the use when regulating data like this, signal processor 61 is carried out interpolation as required and is handled, and obtains to regulate the linear interpolation that data are carried out in advance as using.

Then, at step S210,61 pairs of essential adjusting items of signal processor are carried out calibration process.When carrying out calibration process, as mentioned above, signal processor 61 generates parts 7 with test signal and is controlled to be mode of operation with the generation test signal, and switching circuit 6 is switched to test signal generation parts 7 sides.

After calibration process finished, signal processor 61 generated parts 7 with test signal and is controlled to be non-operating state stopping the generation of test signal, and switching circuit 6 is switched to reception antenna 5 sides.Therefore, TV-set broadcasting receiver has been set up the accepting state of selected channel switching channel afterwards.

Then, signal processor 61 turns back to step S207 with processing, with the step process that repeats to begin with step S207.

If determine that at step S207 the user carries out the dump operation, signal processor 61 finishes the processing routine of Figure 13 so.At this moment, at step S211, the adjusting data of cache memory 61b disappear.The processing that it may be noted that step S211 is not the processing of being carried out by signal processor 61, but the affirmation that the memory contents of expression cache memory 61b during to dump is lost.

[interpolation of signal processor 61 is handled example]

In the present embodiment, use is stored in the regulating in advance of cache memory 61b " cut-off frequency of IF BPF is regulated data " shown in Figure 3 in the data, can be ready for the intermediate frequency bandwidth of the band pass filter 24 of intermediate frequency for all broadcast systems.In addition,, use " cut-off frequency of IF BPF is regulated data " shown in Figure 3 to carry out interpolation and handle, can carry out the fine setting setting of cut-off frequency by intermediate frequency bandwidth in response to expectation.

Figure 14 illustration is stored in nonvolatile memory 51 " cut-off frequency of IF BPF is regulated data ".With reference to Figure 14, the low-limit frequency of intermediate frequency bandwidth that is used for the band pass filter 24 of intermediate frequency is fixed, and the acquisition in advance that is not included in nonvolatile memory 51 is regulated in the data.

" cut-off frequency of IF BPF is regulated data " comprises that the bandwidth 6MHz/7MHz/8MHz with 3 frequency acceptance bands distinguishes the adjusting of the acquisition in advance data of corresponding cut-off frequency

IF_BPF_COFF_6M，

IF_BPF_COFF_7M, and

IF_BPF_COFF_8M。

Data are regulated in the acquisition in advance that provides more than signal processor 61 uses, and handle the corresponding optimum cut-off frequency of selected receiving channels definite and band pass filter 24 by interpolation.Figure 15 illustrates the processing operational flowchart of signal processor 61 in the case.

At step S301, signal processor 61 is at first read from cache memory 61b and is obtained to regulate data I F_BPF_COFF_6M, F_BPF_COFF_7M and IF_BPF_COFF_8M in advance.

Then, at step S302, signal processor 61 will compare mutually corresponding to the optimum expectation IF bandwidth IFBW of selected receiving channels and the bandwidth 6MHz/7MHz/8MHz of described 3 frequency acceptance bands, to select two data near expectation IF bandwidth IFBW.

Especially, approaching most in described two data expects that first data of IF bandwidth IFBW are represented by IFBW1, and selects bandwidth IFBW1 from the bandwidth 6MHz/7MHz/8MHz of described 3 frequency acceptance bands.Then, the cut-off frequency of regulating data as obtain in advance relevant with selected bandwidth is regulated data and be expressed as adjusting data I F_BPF_COFF1.

In described two data second are represented by IFBW2 near second data of expectation IF bandwidth IFBW, and select bandwidth IFBW2 from the bandwidth 6MHz/7MHz/8MHz of described 3 frequency acceptance bands.Then, the cut-off frequency of regulating data as obtain in advance relevant with selected bandwidth is regulated data and be expressed as adjusting data I F_BPF_COFF2.

Then, at step S303, the interpolation that the formula A that signal processor 61 uses the data of selecting in above-mentioned this mode to carry out Figure 16 represents is handled mathematical operation, regulates data I F_BPF_COFF to calculate optimum cut-off frequency.

Then, signal processor 61 is regulated data I F_BPF_COFF at step S304 with the cut-off frequency that calculates and is stored in register.When power supply keeps connecting, use the cut-off frequency that is stored in the register to regulate data I F_BPF_COFF the cut-off frequency of band pass filter 24 is finely tuned.

It may be noted that the example of the interpolation processing of the step S205 execution that the above-mentioned interpolation processing that is used for the cut-off frequency of accommodation zone bandpass filter 24 is Figure 13.

Now, the example of the interpolation processing of the step S208 execution of description Figure 13.Some obtain to regulate data in advance and depend on variation with the corresponding RF frequency of selected channel, as shown in figure 17.Therefore, when each selected channel changes, all generate actual use and regulate data.Yet, at this moment, directly may not be stored in the nonvolatile memory 51 corresponding to regulating data with the acquisition in advance of the corresponding RF frequency of selected channel.At Figure 17, illustration nonvolatile memory 51 store the frequency f 1 of interruption, f2, f3 ... acquisition in advance regulate data D1, D2, D3 ...

Directly be stored in this way under the situation of nonvolatile memory 51 corresponding to the adjusting data that obtain in advance with the corresponding RF frequency of selected channel, signal processor 61 is carried out the interpolations processing and is regulated data to produce actual use.

For example, and if the corresponding RF frequency of selected channel be in the frequency f 1 of Figure 17 and the frequency f 12 between the f2, signal processor 61 is carried out this interpolation as described below and is handled.Especially, the frequency f 1 of the both sides of signal processor 61 frequency of utilization f12 and the data D1 of f2 and D2 carry out interpolation and handle, with the practical adjustments data D12 of calculated rate f12.The following this mathematical operation formula that provides is used for interpolation to be handled.

Especially, if frequency f 12 is represented by k1 with the difference of frequency f 1 and frequency f 12 is represented by k2 with the difference of frequency f 2, then determine practical adjustments data D12 by following mathematical operation formula (B):

D12＝{k2/(k1+k2)}D1+{k1/(k1+k2)}D2

(formula B)

[calibration example]

Now, the calibration example of carrying out among the step S206 of the flow chart of Figure 13 or the step S209 is described.Following example is intended to regulate the image disruption removal characteristic of intermediate frequency filter (that is, band pass filter 24).Below image disruption is removed characteristic calibration be called the IMRR calibration.

For the IMRR calibration of this example, demodulator circuit IC 2 comprises testing circuit 62.

＜be used for first example of structure of the testing circuit 62 of IMRR calibration 〉

Figure 18 illustrates first example of the concrete structure of testing circuit 62.With reference to Figure 18, in the example shown, demodulator circuit parts 60 comprise A/D converter 601 and the demodulation process parts 602 that the intermediate frequency signal from front-end circuit IC 1 converted to digital signal.To offer testing circuit 62 from the digital intermediate frequency signal of A/D converter 601.

Testing circuit 62 comprises multiplier 621, oscillator 622, low pass filter 623 and level detector 624.

Oscillator 622 generates the oscillator signal of intermediate frequency.Digital intermediate frequency signal is offered multiplier 621, the oscillator signal of oscillator 622 is also offered multiplier 621.From the frequency corresponding output signal of multiplier 621 acquisitions with the difference of digital intermediate frequency signal and oscillator signal.The output signal of multiplier 621 is offered level detector 624 by low pass filter 623.Level detector 624 detects the output signal level of multiplier 621, and testing result is offered signal processor 61.

Have fixed frequency although be used for the test signal from test signal generation parts 7 of IMRR calibration, signal processor 61 is the image disruption frequency of selected receiving channels with this frequency setting.

Therefore, when under the IMRR calibration mode during from antenna terminal pin T11 input test signal, be in optimum state if the image disruption of band pass filter 24 is removed characteristic, then the detection level of the level detector 624 of testing circuit 62 equals 0 in the ideal case.

Signal processor 61 is removed the adjusting data of characteristic with reference to the detection level of the level detector 624 of testing circuit 62 with the image disruption of accommodation zone bandpass filter 24.Then, signal processor 61 is exchanged joint number according to calibrating, and makes that can obtain optimum image disturbs the removal characteristic.

The operation example of＜signal processor 61 when IMRR calibrates 〉

Processing operational flowchart when Figure 19 is illustrated in the calibration that signal processor 61 carries out image disturb to remove characteristic.

With reference to Figure 19, at step S400, signal processor 61 is when in the end the channel selection of a channel begins or the channel selection after selected channel switches when beginning, the processing routine that beginning IMRR calibrates.

Before the IMRR calibration, at step S401, as mentioned above, signal processor 61 is at first read from cache memory 61b and is obtained to regulate data in advance, offers front-end circuit IC 1 to produce actual use adjusting data and data are regulated in the reality use.The actual use that signal processor 61 is produced is regulated in the data with image disruption and is removed the default value a that the adjusting data of the object that data are defined as the IMRR calibration are regulated in the relevant actual use of characteristic.

At step S402,61 pairs of test signals of signal processor generate parts 7 and control the test signal that is used for selected channel with generation, and switching circuit 6 is switched to test signal generation parts 7 sides so that the IMRR calibration mode comes into force.

Then, at step S403, signal processor 61 is carried out the initialization of the adjusting value of setting that is used for the IMRR calibration.Especially, in the scope of carrying out the IMRR calibration, the initial value that signal processor 61 will be used for the value of the setting x of IMRR calibration is set at minimum value x=a-MRANGE.

Then, at step S404, signal processor 61 is set a higher value MAXVAL to the variable minmag that will compare with the output level of level detector 624 as initial value.In other words, signal processor 61 is set at MAXVAL with variable minmag.

Then, at step S405, signal processor 61 sends to front-end circuit IC 1 with set point x, thereby the image disruption that set point x is set at the band pass filter 24 of front-end circuit parts 10 is removed characteristic adjusting data.

Then, at step S406, signal processor 61 is read the detection level amp of the level detector 624 of testing circuit 62.Then, at step S407, signal processor 61 compares the detection level amp and the variable minmag of level detector 624 mutually, to determine whether to satisfy amp＜minmag.

If determine to satisfy amp＜minmag, then set point x is stored as optimal value x_opt, and variable minmag is defined as detection level amp with the corresponding level detector 624 of set point x at step S408 signal processor 61 at step S407.

On the other hand, if determine not satisfy amp＜minmag at step S407, then signal processor 61 is not carried out the renewal of optimal value x_opt and variable minmag.

Then, signal processor 61 determines at step S409 whether set point x is higher than the maximum a+PRANGE of the scope of carrying out the IMRR calibration.Be not higher than maximum a+PRANGE if determine set point x, then next regulated value set to set point x at step S410 signal processor 61.Signal processor 61 is determined next regulated value in response to the adjusting step-length width of IMRR calibration.After having set next regulated value, signal processor 61 turns back to step S405 with processing, repeats the step process that begins with step S405.

If determine that at step S409 set point x is higher than maximum a+PRANGE, then the current regulated value that keeps as optimal value x_opt is set at image and removes the relevant optimal adjustment value of interference characteristic at step S411 signal processor 61.

Then, at step S412, it is invalid that signal processor 61 is set at the IMRR calibration mode, and this is notified to system controller 4.Then, at step S413, signal processor 61 enters the common mode of operation on the channel that is receiving.

Although it may be noted that in the processing example of the flow chart of above-mentioned Figure 19 and determine the optimal adjustment value, also can use some other searching method, as two fens (binary) searching methods by the searching method of complete or limit.

＜be used for second example of structure of the testing circuit 62 of IMRR calibration 〉

Figure 20 illustrates second example of structure of the testing circuit 62 of demodulator circuit IC 2.

Second topology example utilizes demodulator circuit parts 60 to have the structure of OFDM (OFDM) demodulator circuit and comprises the fact of fast Fourier transform (FFT) parts.

Especially, in demodulator circuit parts 60, the output signal of A/D converter 601 is carried out quadrature demodulation by the mixer that constitutes by multiplier 603 and frequency oscillator 604.Then, FFT parts 605 will become frequency-region signal through the conversion of signals of mixer quadrature demodulation.

In this second topology example, the output signal of the FFT parts 605 of demodulator circuit parts 60 is offered testing circuit 62.Testing circuit 62 is made of peak swing detector 625.Peak swing detector 625 determines to represent the frequency of peak swing according to the mathematical operation result of FFT parts 605, and exports the amplitude of this frequency.The amplitude output of peak swing detector 625 is offered signal processor 61.

In the IMRR calibration, owing to the test signal that the image disruption frequency is provided by antenna terminal pin T11, so peak swing detector 625 offers signal processor 61 with the output of the amplitude in the image disruption frequency.

Therefore, signal processor 61 can be removed the regulated value of characteristic by IMRR alignment settings image disruption, sets the optimal adjustment value that image disruption is removed characteristic, makes that the amplitude output of peak swing detector 625 can be 0.

By use the adjusting of the acquisition in advance data that are stored in advance in the nonvolatile memory 51 to carry out calibration by above-mentioned this mode, the accurate actual adjusting data of using that are suitable for change in long term and environment for use are produced.At this moment, be stored in obtaining in advance in the nonvolatile memory 51 and regulate data and carry out the calibration that data are regulated in actual uses as starting point owing to use, it is very short therefore to calibrate the required time before obtaining optimum actual use adjusting data.

It may be noted that the test signal that is used to calibrate can be generated parts 7 is arranged on front-end circuit IC 1.

[other embodiment and other modifications]

In the foregoing description, the nonvolatile memory 51 that is used to store the adjusting data relevant with the adjusting part of front-end circuit parts 10 is arranged on front-end circuit IC 1.Yet, also nonvolatile memory 51 can be arranged on beyond the front-end circuit IC 1.Figure 21 illustrates the topology example of the TV-set broadcasting receiver with structure of describing just now.

With reference to Figure 21, front-end circuit IC 1 does not comprise nonvolatile memory, and only comprises buffer register 54.Buffer register 54 receives and stores the adjusting data of the adjusting part of front-end circuit parts 10 from the signal processor 61 of demodulator circuit IC 2, and will regulate the adjusting part that data offer front-end circuit parts 10.

In addition, in this example, nonvolatile memory 70 is arranged on outside the front-end circuit IC 1 and via terminal supportor T27 is connected to signal processor 61.Signal processor 61 is visited nonvolatile memory 70 when needed, obtains to regulate data in advance to read from nonvolatile memory 70.Then, similar to the above embodiments, signal processor 61 is regulated data according to the acquisition in advance that receives from nonvolatile memory 70 and is generated actual use adjusting data, then data is regulated in the reality use and offers buffer register 54.

Except nonvolatile memory 70 being arranged on front-end circuit IC 1 outside, the structure of Figure 21 is operated similar to the above embodimentsly, and realizes similarly work effect.

Only remove the relevant adjusting data of characteristic for the image disruption of band pass filter 24 and carry out although it may be noted that the calibration of the foregoing description, calibration is not limited to this.For example, calibration also can be carried out for the tuned frequency adjusting data or the gain-adjusted data of tracking filter.In addition, the cut-off frequency that calibration can also be applied to band pass filter 24 is regulated.Moreover calibration also can disperse to regulate data for the electric current of VCO or the dispersion adjusting data relevant with the constant voltage source of constant voltage circuit 53 are carried out.

In addition, although in to the above description of embodiment with the receiving channels frequency as with the relevant parameter example of variation of regulating data, described parameter is not limited to this.For example, can with according to the adjusting storage of change in long term at nonvolatile memory, and the timer that will be used for Measuring Time incorporates electronic equipment into, thereby handles the optimal adjustment data that produce the current time in response to the elapsed time by interpolation according to regulating data.

And, can also with according to the adjusting storage of variations in temperature at nonvolatile memory, and the device that will be used for measures ambient temperature is incorporated electronic equipment into, thereby measure the temperature of current time by temperature measuring equipment, handle according to the adjusting data that are stored in nonvolatile memory producing the adjusting data that are suitable for this temperature then by interpolation.

In addition, although use the error-correcting code of RS sign indicating number, naturally, not only can use the RS sign indicating number, and can use various other error-correcting codes or error detection correction sign indicating number as the adjusting data in will write non-volatile memory.

Although it may be noted that electronic equipment is a TV-set broadcasting receiver in the above-described embodiments, naturally, the present invention can be applied to the various electronic equipments except that TV-set broadcasting receiver.

Although use particular term that the preferred embodiment of the present invention is described, this description only is for illustrative purposes, should be understood that to change under the situation of the spirit or scope that do not break away from claims and to change.

Claims

1. electronic equipment comprises:

First integrated circuit comprises: can use and regulate the inside building block that data are regulated; Nonvolatile memory wherein stores in advance and to obtain to regulate data, describedly obtains to regulate the result that data are adjustings that described inner building block is carried out in advance in advance; And interface unit, have the data transport functions of the signal processor second integrated circuit that will be sent to from the described adjusting of the acquisition in advance data that described nonvolatile memory is read outside described first integrated circuit and the actual use adjusting data that the signal processor second integrated circuit of storage outside described first integrated circuit sends and the described reality use that will store and regulate the data storage function that data offer described inner building block; With

Second integrated circuit, comprise signal processor as inner building block, the described interface unit of described first integrated circuit is connected to this signal processor, the operation of described signal processor describedly obtains to regulate data in advance to receive from what described nonvolatile memory was read by described interface unit when the power connection, the described acquisition in advance that receives regulated storage in the embedded memory of described signal processor, when keeping connecting, power supply reads the described data that obtain in advance to regulate from described embedded memory, generate the described actual adjusting data of using according to the described adjusting data that obtain in advance of reading from described embedded memory, the described actual use that will generate is then regulated data and is sent to described interface unit.

2. electronic equipment according to claim 1, wherein said first integrated circuit constitutes the front end component that is configured to receiving broadcast signal, and described second integrated circuit formation is configured to the demodulation parts of demodulation from the signal of described front end component.

3. electronic equipment according to claim 1, the wherein said adjusting data that obtain in advance write described nonvolatile memory with the error correction coding form, and carry out error correcting/decoding by the described signal processor of described second integrated circuit.

4. dispersion adjustment method that is used for the IC interior building block of electronic equipment comprises step:

Write in the nonvolatile memory of first integrated circuit regulating data, first integrated circuit comprises: can use and regulate the inside building block that data are regulated; Described nonvolatile memory wherein stores in advance and to obtain to regulate data, describedly obtains to regulate the result that data are adjustings that described inner building block is carried out in advance in advance; And interface unit, having the data transport functions of the signal processor second integrated circuit that will be sent to from the described adjusting of the acquisition in advance data that described nonvolatile memory is read outside described first integrated circuit and the actual use that the signal processor second integrated circuit of storage outside described first integrated circuit sends regulates data and the data storage function that data offer described inner building block is regulated in described reality use;

Signal processor by second integrated circuit, when power connection, receive the described adjusting data that obtain in advance of reading from described nonvolatile memory by described interface unit, and the described embedded memory that obtains the adjusting storage at described signal processor in advance that will receive, described second integrated circuit comprises the described signal processor as inner building block, and the described interface unit of described first integrated circuit is connected to described signal processor; And

By described signal processor, when power supply keeps connecting, read the described data that obtain in advance to regulate from described embedded memory, generate described actual use adjusting data according to the described adjusting data that obtain in advance of reading, use the adjusting data to send to described interface unit the described reality that generates from described embedded memory.

5. integrated circuit comprises:

Signal processor as inner building block, the interface unit of another integrated circuit is connected to this signal processor, described another integrated circuit comprises using regulates the inside building block that data are regulated, nonvolatile memory and interface unit, wherein said nonvolatile memory stores has acquisition in advance to regulate data, describedly to regulate the result that data are adjustings that the inside building block of described another integrated circuit is carried out in advance in advance, described interface unit has regulates the data transport functions that data are sent to described signal processor with the described acquisition in advance of reading from described nonvolatile memory, regulate the data storage function that data offer the inside building block of described another integrated circuit with storage from the actual use adjusting data of described signal processor transmission and described actual use that will store

Described signal processor can be operated to receive from what described nonvolatile memory was read by described interface unit when the power connection and describedly obtain to regulate data in advance, with the described embedded memory that obtains the adjusting storage at described signal processor in advance that receives, when keeping connecting, power supply reads the described data that obtain in advance to regulate from described embedded memory, generate the described actual adjusting data of using according to the described adjusting data that obtain in advance of reading from described embedded memory, the described actual use that will generate is then regulated data and is sent to described interface unit.

6. integrated circuit according to claim 5, wherein said integrated circuit constitutes the demodulation parts, and these demodulation parts are configured to from described another integrated circuit received signal, and described another integrated circuit constitutes the front end component that is configured to receiving broadcast signal.

7. electronic equipment comprises:

First integrated circuit comprises: can use and regulate the inside building block that data are regulated; And data storage part, be configured to that data are regulated in the actual use that the signal processor second integrated circuit outside described first integrated circuit sends and offer described inner building block;

Nonvolatile memory wherein stores in advance and to obtain to regulate data, describedly obtains to regulate the result that data are adjustings that the described inner building block of described first integrated circuit is carried out in advance in advance; And

Second integrated circuit comprises the signal processor as inner building block, and the described data storage part and the described nonvolatile memory of described first integrated circuit are connected to this signal processor,

Described signal processor can be operated to receive when the power connection from what described nonvolatile memory was read and describedly obtain to regulate data in advance, with the described embedded memory that obtains the adjusting storage at described signal processor in advance that receives, when keeping connecting, power supply reads the described data that obtain in advance to regulate from described embedded memory, generate the described actual adjusting data of using according to the described adjusting data that obtain in advance of reading from described embedded memory, the described actual use that will generate is then regulated data and is sent to described data storage part.