CN101552035A - Storage system - Google Patents
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- CN101552035A CN101552035A CNA2008100908092A CN200810090809A CN101552035A CN 101552035 A CN101552035 A CN 101552035A CN A2008100908092 A CNA2008100908092 A CN A2008100908092A CN 200810090809 A CN200810090809 A CN 200810090809A CN 101552035 A CN101552035 A CN 101552035A
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Abstract
The invention relates to a storage system which comprises at least one storage unit and a source electrode power supply driving circuit. Each storage unit is coupled between a source electrode voltage and a ground voltage and stores a digital datum according to a word line signal and a bit line signal. The source electrode power supply driving circuit provides the source electrode voltage for the storage unit, when the storage unit is in a read state, the source electrode voltage is a first power supply voltage, and when the storage unit is in a write state, the source electrode voltage is a second power supply voltage, wherein the second power supply voltage is that the first power supply voltage reduces a given voltage so as to prevent the storage unit from writing error when rewriting the digital datum.
Description
Technical field
The invention relates to a kind of memory cell, particularly receive variable voltage source to avoid the data write error mistake relevant for a kind of memory cell with single bit line.
Background technology
Fig. 1 shows that tradition has five transistorized static RAMs (Static RandomAccess Memory, SRAM) 100.Switch 101 is a nmos pass transistor, nmos pass transistor 101 according to the WL conducting of character line signal or not conducting to transmit bit line signal BL to storage unit 110, storage unit 110 is that a latch circuit is made up of two phase inverter cross-coupled, first phase inverter comprises nmos pass transistor 102 and PMOS transistor 104, second phase inverter comprises nmos pass transistor 103 and PMOS transistor 105, and Node B and C are anti-phase each other with store digital data.
When storer 100 write data 1, the current potential of bit line signal BL can be moved current potential V to
Dd, character line signal WL conducting nmos pass transistor 101, so Node B is a noble potential and node C is an electronegative potential.When storer 100 write data 0, the current potential of bit line BL can be pulled down to current potential GND, character line signal WL conducting nmos pass transistor 101, so Node B is an electronegative potential and node C is a noble potential.
When storage unit 110 storage datas are 1 when being read, can pre-charge bit line to current potential V
Dd, by character line signal WL conducting nmos pass transistor 101, next, system can detect the current potential of bit line again, because Node B is a noble potential, the current potential of bit line can not dragged down, and is 1 so the data that are stored in storage unit 110 are learnt by system.
When storage unit 110 storage datas are 0 when being read, can pre-charge bit line to current potential V
Dd, by character line signal WL conducting nmos pass transistor 101, next, system can detect the current potential of bit line again, because node C is a noble potential, the current potential of bit line BL can be dragged down, and is 0 so the data that are stored in storage unit 110 are learnt by system.
Has only a bit line because storer 100 is limited, when storage unit 110 during storage data 1 (just Node B is a noble potential), just can't be when storage unit 110 writes noble potential again with correct current potential write storage unit 110, classic method is to adjust the beta ratio of transistor 102,103,104 or 105, yet, said method can cause storage unit 110 degree of stability deficiencies, and the present invention will solve the problem that said memory cells 110 writes noble potential again.
Summary of the invention
In view of this, the invention provides a kind of static RAM system.The static RAM system comprises at least one storage unit and one source pole power driving circuit.Storage unit is coupled between an one source pole voltage and the ground voltage and by a character line signal and a bit line signal access one numerical data.The source electrode power driving circuit provides source voltage to storage unit, when storage unit is a reading state, source voltage is first supply voltage, when storage unit is a write state, source voltage is a second source voltage, and wherein second source voltage is that write error takes place when reducing by a specific voltage and writing numerical data once more to avoid storage unit first supply voltage.
Description of drawings
Fig. 1 shows to have five transistorized static RAMs;
Fig. 2 shows source electrode power driving circuit according to an embodiment of the invention;
Fig. 3 shows the layout of accumulator system according to an embodiment of the invention;
Fig. 4 shows source electrode power driving circuit according to another embodiment of the present invention; And
Fig. 5 shows the layout of accumulator system according to another embodiment of the present invention.
Drawing reference numeral
The static RAM of 100～5T cells
101,102,103,201,202,401,402～nmos pass transistor
104,105,203,403～PMOS transistor
110～storage unit
200,200-1,200-2,400～source electrode power driving circuit
210,410～control circuit
220,420～CMOS phase inverter
300, the layout of 500～accumulator system
310,320,510,520～character line drive circuit
331,332～phase inverter
A, B, C～node
BL～bit line signal
COLB, COLB1, COLB2～bit alignment control signal
GND, Vdd～voltage
WL, WLB1, WLB2～character line signal
WEB～write-enable signal
SL～source voltage
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Because storer 100 is limited to have only a bit line, when storage unit 110 during storage data 1 (just Node B is a noble potential), when storage unit 110 writes noble potential again write error can take place.And the potential difference (PD) of nmos pass transistor source electrode and drain electrode is V
TN, when storage unit 110 write noble potential again, the current potential of bit line was V
Dd, the current potential of Node B is V
Dd-V
TN, so nmos pass transistor 103 conducting fully, and nmos pass transistor 102 is closed deficiency, so storer 100 can't be stored in correct current potential Node B and C, when causing storage unit 110 to write noble potential again, write error again takes place easily.
Fig. 2 shows source electrode power driving circuit 200 according to an embodiment of the invention.Source electrode power driving circuit 200 can provide different source voltage SL to storage unit 110, please also refer to Fig. 1, and when storage unit 110 during at write state, source electrode power driving circuit 200 can provide voltage V
Dd-V
TN, so the transistor 103 of storage unit 110 can the conducting deficiency not cause write error, when storage unit 110 during at reading state, source electrode power driving circuit 200 can provide voltage V
Dd, storage unit 110 normally is read by nmos pass transistor 101 and bit line.
Source electrode power driving circuit 200 is according to the current potential of the current potential of write-enable signal WEB, character line signal WLB1 and WLB2 decision node A and source voltage SL, and when storage unit during at write state, node A current potential is a noble potential, and source voltage SL is V
Dd-V
TN, when storage unit during at reading state, node A current potential is an electronegative potential, and source voltage SL is V
DdAs shown in the following Table 1:
Table 1
| WLB1 | WLB2 | WEB | A | SL | ||
| Read | | X | 1 | GND | V dd | |
| Write | 1 | 0 | 0 | V dd | V dd-V TN | |
| Write | 0 | 1 | 0 | V dd | V dd-V TN |
Source electrode power driving circuit 200 comprises control circuit 210, CMOS phase inverter 220 and nmos pass transistor 201, control circuit 210 can determine the current potential of node A and the current potential of source voltage SL according to the current potential of write-enable signal WEB, character line signal WLB1 and WLB2, makes storage unit 110 write fashionable receiving than low supply voltage to avoid write error.Wherein the current potential of write-enable signal WEB, character line signal WLB1 or WLB2 is 0 o'clock, the corresponding stored unit is a write state, when the current potential of write-enable signal WEB, character line signal WLB1 or WLB2 is 1, the corresponding stored unit is a reading state, character line signal WLB1 and the corresponding different storage unit column or row of WLB2 difference.
Fig. 3 shows the layout of accumulator system 300 according to an embodiment of the invention, 300 of accumulator systems show six storage unit, yet, accumulator system 300 is not limited to and is only had six storage unit, character line drive circuit 310 and 320 transmits character line signal WL1 and WL2 respectively to the corresponding stored cell columns, as shown in Figure 3, character line signal WL1 and WL2 produce character line signal WLB1 via phase inverter 331 and 332 respectively and WLB2 is sent to source electrode power driving circuit 200, so source electrode power driving circuit 200 can provide the source voltage SL of two different column of memory cells.
Fig. 4 shows source electrode power driving circuit 400 according to another embodiment of the present invention.Source electrode power driving circuit 400 can provide different source voltage SL to storage unit 110, and when storage unit 110 during at write state, source electrode power driving circuit 400 can provide voltage V
Dd-V
TN, so the transistor 103 of storage unit 110 can the conducting deficiency not cause write error, when storage unit 110 during at reading state, source electrode power driving circuit 400 can provide voltage V
Dd, storage unit 110 normally is read by nmos pass transistor 101 and bit line BL.
Source electrode power driving circuit 400 is according to the current potential of the current potential of write-enable signal WEB and bit alignment control signal COLB decision node A and source voltage SL, and when storage unit during at write state, node A current potential is a noble potential, and source voltage SL is V
Dd-V
TN, when storage unit during at reading state, node A current potential is an electronegative potential, and source voltage SL is V
DdAs shown in the following Table 2:
Table 2
| COLB | WEB | A | SL | |
| Read | |
1 | GND | V dd |
| Write | 0 | 0 | V dd | V dd-V TN |
Source electrode power driving circuit 400 comprises control circuit (anti-phase or logic gate, NOR Gate) 410, CMOS phase inverter 420 and nmos pass transistor 401, control circuit 410 can determine the current potential of node A and the current potential of source voltage SL according to the current potential of write-enable signal WEB and bit alignment control signal COLB, makes storage unit 110 write fashionable receiving than low supply voltage to avoid write error.Wherein the current potential of write-enable signal WEB and bit alignment control signal COLB is 0 o'clock, and the corresponding stored unit is a write state, and when the current potential of write-enable signal WEB was 1, the corresponding stored unit was a reading state.
Fig. 5 shows the layout of accumulator system 500 according to another embodiment of the present invention, 500 of accumulator systems show six storage unit, yet, accumulator system 500 is not limited to and is only had six storage unit, character line drive circuit 510 and 520 transmits character line signal WL1 and WL2 respectively to the corresponding stored cell row, as shown in Figure 5, bit alignment control signal COLB1 and COLB2 are sent to source electrode power driving circuit 200-1 and 200-2 respectively, and source electrode power driving circuit 200-1 and 200-2 provide the source voltage SL of different column of memory cells respectively.
Accumulator system about Fig. 3 and Fig. 5, because accumulator system 300 is shorter in the length of Y direction (vertical direction), accumulator system 300 can be applied on some specified arrangement demands, and accumulator system 500 layout areas are less, and accumulator system 500 can reduce the wafer usable floor area to reduce cost.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; any technician who is familiar with this field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention attached claim person of defining before looking is as the criterion.
Claims (12)
1. an accumulator system is characterized in that, this accumulator system comprises:
At least one storage unit is coupled between an one source pole voltage and the ground voltage, and by a character line signal and a bit line signal access one numerical data; And
The one source pole power driving circuit, provide above-mentioned source voltage to said memory cells, when said memory cells is a reading state, above-mentioned source voltage is one first supply voltage, when said memory cells is a write state, above-mentioned source voltage is a second source voltage, and wherein above-mentioned second source voltage is that write error takes place when reducing by a specific voltage and writing above-mentioned numerical data once more to avoid said memory cells above-mentioned first supply voltage.
2. accumulator system as claimed in claim 1 is characterized in that, above-mentioned source electrode power driving circuit is exported above-mentioned source voltage in the one drive circuit output terminal, and above-mentioned source electrode power driving circuit comprises:
One control circuit, when said memory cells was above-mentioned reading state, above-mentioned control circuit was exported a low-potential signal in an output port, and when said memory cells was above-mentioned write state, above-mentioned control circuit was exported a high potential signal in above-mentioned output port;
One phase inverter, couple the above-mentioned output port of above-mentioned control circuit and be coupled between above-mentioned first supply voltage and the above-mentioned ground voltage, when above-mentioned control circuit was exported above-mentioned low-potential signal, above-mentioned phase inverter was exported above-mentioned first supply voltage to above-mentioned driving circuit output terminal; And
One first nmos pass transistor has one first source electrode and couples above-mentioned first supply voltage, a first grid and couple above-mentioned first supply voltage and above-mentioned first source electrode and one first drain electrode and couple above-mentioned driving circuit output terminal;
Wherein when above-mentioned control circuit was exported above-mentioned high potential signal, above-mentioned first nmos pass transistor was exported above-mentioned second source voltage to above-mentioned driving circuit output terminal.
3. accumulator system as claimed in claim 2 is characterized in that, last control circuit is exported above-mentioned high potential signal or above-mentioned earthing potential signal to above-mentioned driving circuit output terminal according to a write-enable signal and at least one character line signal deciding.
4. accumulator system as claimed in claim 2, it is characterized in that, last control circuit determines above-mentioned high potential signal of output or above-mentioned earthing potential signal to above-mentioned driving circuit output terminal according to a write-enable signal and at least one bit alignment control signal, the corresponding above-mentioned bit line signal of above-mentioned bit alignment control signal.
5. accumulator system as claimed in claim 4, it is characterized in that, last control circuit is an anti-phase or logic gate, above-mentioned anti-phase or logic gate according to the current potential of above-mentioned write-enable signal and above-mentioned bit alignment control signal to export above-mentioned high potential signal or above-mentioned low-potential signal.
6. accumulator system as claimed in claim 2 is characterized in that, above-mentioned specific voltage is a critical voltage of above-mentioned first nmos pass transistor.
7. accumulator system as claimed in claim 2 is characterized in that, above-mentioned phase inverter comprises:
One second nmos pass transistor has that one second source electrode couples above-mentioned driving circuit output terminal, one second drain electrode couples the above-mentioned output port that above-mentioned earthing power supply and a second grid couple above-mentioned control circuit; And
One PMOS transistor has that one the 3rd source electrode couples above-mentioned driving circuit output terminal, one the 3rd drain electrode couples the above-mentioned output port that above-mentioned first supply voltage and one the 3rd grid couple above-mentioned control circuit.
8. accumulator system as claimed in claim 1 is characterized in that, said memory cells is one to have five transistorized static random access memory (sram) cells.
9. accumulator system as claimed in claim 1 is characterized in that said memory cells comprises:
One latch circuit comprises one first phase inverter and one second phase inverter cross-coupled storing above-mentioned numerical data, and by the above-mentioned numerical data of an input end access; And
One switch, according to the above-mentioned bit line of the current potential conducting signal of above-mentioned character line signal to above-mentioned latch circuit with the above-mentioned numerical data of access.
10. accumulator system as claimed in claim 1, it is characterized in that, this accumulator system more comprises a character line drive circuit, wherein above-mentioned character line drive circuit, said memory cells and above-mentioned source electrode power driving circuit along the directions X setting to reduce the length of above-mentioned accumulator system Y direction.
11. an accumulator system is characterized in that, this storer comprises:
At least one storage unit is coupled between an one source pole voltage and the ground voltage, and by a character line signal and a bit line signal access one numerical data; And
The one source pole power driving circuit, provide above-mentioned source voltage to said memory cells, when said memory cells is a reading state, above-mentioned source voltage is one first supply voltage, when said memory cells is a write state, above-mentioned source voltage is a second source voltage, wherein above-mentioned second source voltage is that write error takes place when reducing by a specific voltage and writing above-mentioned numerical data once more to avoid said memory cells above-mentioned first supply voltage, wherein above-mentioned source electrode power driving circuit is exported above-mentioned source voltage in the one drive circuit output terminal, and above-mentioned source electrode power driving circuit comprises:
One control circuit, when said memory cells was above-mentioned reading state, above-mentioned control circuit was exported a low-potential signal in an output port, and when said memory cells was above-mentioned write state, above-mentioned control circuit was exported a high potential signal in above-mentioned output port;
One phase inverter, couple the above-mentioned output port of above-mentioned control circuit and be coupled between above-mentioned first supply voltage and the above-mentioned ground voltage, when above-mentioned control circuit was exported above-mentioned low-potential signal, above-mentioned phase inverter was exported above-mentioned first supply voltage to above-mentioned driving circuit output terminal; And
One first nmos pass transistor, having one first source electrode couples above-mentioned first supply voltage, a first grid and couples above-mentioned first supply voltage and above-mentioned first source electrode and one first drain electrode and couple above-mentioned driving circuit output terminal, when above-mentioned control circuit is exported above-mentioned high potential signal, above-mentioned first nmos pass transistor is exported above-mentioned second source voltage to above-mentioned driving circuit output terminal
Wherein go up control circuit and be according to a write-enable signal and at least one character line signal deciding and export above-mentioned high potential signal or above-mentioned earthing potential signal to above-mentioned driving circuit output terminal.
12. an accumulator system is characterized in that, this accumulator system comprises:
At least one storage unit is coupled between an one source pole voltage and the ground voltage, and by a character line signal and a bit line signal access one numerical data; And
The one source pole power driving circuit, provide above-mentioned source voltage to said memory cells, when said memory cells is a reading state, above-mentioned source voltage is one first supply voltage, when said memory cells is a write state, above-mentioned source voltage is a second source voltage, wherein above-mentioned second source voltage is that write error takes place when reducing by a specific voltage and writing above-mentioned numerical data once more to avoid said memory cells above-mentioned first supply voltage, wherein above-mentioned source electrode power driving circuit is exported above-mentioned source voltage in the one drive circuit output terminal, and above-mentioned source electrode power driving circuit comprises:
One control circuit, when said memory cells was above-mentioned reading state, above-mentioned control circuit was exported a low-potential signal in an output port, and when said memory cells was above-mentioned write state, above-mentioned control circuit was exported a high potential signal in above-mentioned output port;
One phase inverter, couple the above-mentioned output port of above-mentioned control circuit and be coupled between above-mentioned first supply voltage and the above-mentioned ground voltage, when above-mentioned control circuit was exported above-mentioned low-potential signal, above-mentioned phase inverter was exported above-mentioned first supply voltage to above-mentioned driving circuit output terminal; And
One first nmos pass transistor, having one first source electrode couples above-mentioned first supply voltage, a first grid and couples above-mentioned first supply voltage and above-mentioned first source electrode and one first drain electrode and couple above-mentioned driving circuit output terminal, when above-mentioned control circuit is exported above-mentioned high potential signal, above-mentioned first nmos pass transistor is exported above-mentioned second source voltage to above-mentioned driving circuit output terminal
Wherein going up control circuit is to determine above-mentioned high potential signal of output or above-mentioned earthing potential signal to above-mentioned driving circuit output terminal according to a write-enable signal and at least one bit alignment control signal, the corresponding above-mentioned bit line signal of above-mentioned bit alignment control signal.
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| CN2008100908092A CN101552035B (en) | 2008-04-02 | 2008-04-02 | Storage system |
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|---|---|---|---|
| CN2008100908092A CN101552035B (en) | 2008-04-02 | 2008-04-02 | Storage system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456351A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Driver for static random access memory (RAM), and static RAM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE602006017777D1 (en) * | 2005-07-29 | 2010-12-09 | Semiconductor Energy Lab | Semiconductor memory and its operating method |
| JP4865360B2 (en) * | 2006-03-01 | 2012-02-01 | パナソニック株式会社 | Semiconductor memory device |
| CN101071634A (en) * | 2006-05-09 | 2007-11-14 | 松下电器产业株式会社 | Static semiconductor memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456351A (en) * | 2012-06-04 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Driver for static random access memory (RAM), and static RAM |
| CN103456351B (en) * | 2012-06-04 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | For driver and the static RAM of static RAM |
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