CN101540928B - Digital television test signal generator and play method thereof - Google Patents

Abstract

The invention discloses a digital television test signal generator and a play method thereof. The method adopts a DMA data transmission mode to carry out data transmission, reads a corresponding test signal file into a preset data buffer area in a system memory from an external memory through an input interface circuit, and then reads the test signal file into a play buffer area in a signal play buffer from the data buffer area in the system memory so as to save a process which needs to firstly read the test signal file into a preset data buffer area in a CPU and then transmit the test signal file to the data buffer area in the CPU from the data buffer area of the system memory during calling; therefore, the method avoids repeat of the data transmission process, shortens the data transmission time, and improves the running efficiency of the CPU.

Description

Digital TV test signal generator and player method thereof

Technical field

The present invention relates to the DTV technical field of measurement and test, relate in particular to a kind of digital TV test signal generator and player method thereof.

Background technology

Digital TV test signal generator is used to test the test signal of digital television function and performance, and it is mainly DTV research and development, production, detection, demonstration, maintenance and even sales department and uses.The apparatus structure of existing digital TV test signal generator 11, as shown in Figure 1, comprising: input interface circuit 111, CPU 112, user interface 113, Installed System Memory 114, signal play-out buffer 115 and output interface circuit 116.When using; The input interface circuit 111 of digital TV test signal generator is connected with external memory storage; The output interface circuit 116 of digital TV test signal generator is connected with digital television; The user chooses desired test signal file through operation interface 113, and command signal play-out buffer 115 is play this test signal file of choosing, after the user application among the CPU 112 is received user command; The device driver of notice among the CPU 112 opened the test signal file of preserving in the memory externally; The test signal file is read among the CPU 112 preset data buffer zone earlier, again they is transferred to data buffer zone preset in the Installed System Memory 114, afterwards application program again the invocation facility driver again the test signal file is sent to the data buffer zone of CPU 112 from the data buffer zone of Installed System Memory 114; Be sent to them the play buffer of signal play-out buffer at last, after output interface circuit 116 is issued digital television to be measured with them.Therefore, cause that data transmission procedure repeats, the transmission time is long, the CPU operational efficiency is low.

Summary of the invention

The invention provides a kind of digital TV test signal generator and player method thereof, to solve the long and low problem of CPU operational efficiency of data transmission procedure repetition, transmission time that exists in the prior art.

For achieving the above object, one aspect of the present invention provides a kind of player method of digital TV test signal generator, may further comprise the steps:

CPU receives software initialization instruction, hardware initialization instruction and the signal file name from user interface;

Said CPU sets up the data buffer zone according to said software initialization instruction in said Installed System Memory; And the DMA data transfer mode is set; According to said hardware initialization instruction said signal play-out buffer is carried out the parameter setting; Open said signal play-out buffer, generate the DMA request that comprises the signal file name, and said DMA request is sent to dma controller according to said signal file name;

Said dma controller reads corresponding test signal file to said data buffer zone according to said DMA request and through input interface circuit from external memory storage;

Said dma controller adopts the DMA data transfer mode said test signal file to be transferred to the play buffer of said signal play-out buffer from said data buffer zone;

Output interface circuit is sent to digital television to be measured with the test signal file of current storage in the said play buffer.

The method of putting of the present invention saidly reads corresponding test signal file to said data buffer zone according to DMA request and through input interface circuit from external memory storage, may further comprise the steps:

Said dma controller receives said DMA request;

Said dma controller is searched the FAT table according to the signal file name that comprises in the said DMA request and is confirmed the corresponding position of test signal file in said external memory storage;

Said dma controller reads some byte datas to said data buffer zone at every turn from said test signal file;

Said dma controller starts the DMA data transfer mode the some byte datas in the said data buffer zone is sent to said play buffer;

Said dma controller judges whether said DMA transfer of data finishes, if finish, then continues said DMA transfer of data, otherwise, judge whether said signal file reads to finish, if do not finish, then continue reading of said signal file, otherwise finish.

On the other hand, the present invention also provides a kind of digital TV test signal generator, comprises input interface circuit, CPU, user interface, Installed System Memory, signal play-out buffer and output interface circuit, also comprises:

Dma controller; Be used to receive the DMA request that comprises the signal file name that said CPU sends; Read corresponding test signal file preset data buffer area to the said Installed System Memory according to said DMA request and through said input interface circuit from external memory storage, said test signal file is read the play buffer the said signal play-out buffer from the data buffer area of said Installed System Memory.

Digital TV test signal generator of the present invention, said dma controller comprises:

DMA asks receiver module, is used to receive the DMA request that comprises the signal file name that said CPU sends;

First transport module is used for reading corresponding test signal file to the preset data buffer area of said Installed System Memory according to said DMA request and through said input interface circuit from external memory storage;

Second transport module is used for said test signal file is read the preset play buffer of said signal play-out buffer from the data buffer area of said Installed System Memory.

Digital TV test signal generator of the present invention, said first transport module further comprises:

The ff submodule is used for searching the FAT table according to said signal file name and confirms the position of corresponding test signal file at said external memory storage;

First reading submodule is used for reading the data buffer zone of some byte datas to said Installed System Memory from said test signal file at every turn.

Digital TV test signal generator of the present invention, said second transport module further comprises:

Second reading submodule is used for starting the DMA data transfer mode some byte datas of the data buffer zone of said Installed System Memory is sent to the play buffer in the said signal play-out buffer;

Judge submodule, be used to judge whether the DMA transfer of data of said second reading submodule finishes, if do not finish; Then indicate said second reading submodule to continue said DMA transfer of data; Otherwise, judge whether said signal file reads to finish, if do not finish; Then indicate said first reading submodule to continue reading of said signal file, otherwise finish.

Digital TV test signal generator of the present invention, said CPU comprises:

Receiver module is used to receive software initialization instruction, hardware initialization instruction and signal file name from said user interface;

The software initialization module is used for setting up the data buffer zone according to said software initialization instruction at said Installed System Memory, and said DMA data transfer mode is set;

The hardware initialization module is used for according to said hardware initialization instruction said signal play-out buffer being carried out the parameter setting, opens said signal play-out buffer;

The DMA request sending module is used for generating the said DMA request that comprises the signal file name according to said signal file name, and said DMA request is sent to said dma controller.

The present invention adopts DMA data-transmission mode transmission data; Each data buffer zone of from external memory storage, reading the test signal file of needs to Installed System Memory; Start the DMA data transfer mode then the test signal file in the data buffer zone of Installed System Memory is sent to the play buffer in the signal play-out buffer; Thereby saved the process that needs again the test signal file to be sent to from the data buffer zone of Installed System Memory when earlier the test signal file read being got data buffer zone preset among the CPU and calling the data buffer zone the CPU; Therefore, avoided data transmission procedure repetition, shortened data transmission period, improved the operational efficiency of CPU.

Description of drawings

Fig. 1 is the structure drawing of device of existing digital TV test signal generator;

Fig. 2 is the player method flow chart of digital TV test signal generator of the present invention

Fig. 3 is the structure drawing of device of digital TV test signal generator of the present invention;

Fig. 4 is the structure drawing of device of dma controller among Fig. 3;

Fig. 5 is the structure drawing of device of CPU among Fig. 3.

Embodiment

Be described in detail below in conjunction with the accompanying drawing specific embodiments of the invention:

With reference to figure 2, the player method of digital TV test signal generator of the present invention may further comprise the steps:

Step S201, CPU receive software initialization instruction, hardware initialization instruction and the signal file name from user interface.Need explanation, the signal file that the digital TV test signal generator of present embodiment is play is made up of file header and valid data two large divisions, and wherein, valid data adopt the MPEG relevant criterion, and the composition of file header is specifically seen table 1

Table 1: the composition of file header

Sequence number	Purposes	For example	Data type	Length (byte)	Remarks
						1	The signal file name	Defination	char	Maximum 15	Being used for screen shows
2	Dot matrix format	1920X1080	char	Maximum 15	Being used for screen shows
						3	Scan format	013800	unsigned?char	4	Be used for related description to the scanning specification
4	Signal type	11	unsigned?char	1	00-Dan Jing, 01-forbid, how quiet 10-is, 11-lives more
						5	Frame number	1	unsigned?char	1	0-forbids maximum 255
6	Data length	001FA400	Long?int	4
						7	Data structure and reconstruction mode	80	unsigned?char	1	1: 0 monochrome, 1 colour
8	The X point frequently		Long?int	4	XXXX
						9	X frequency division code 1		unsigned?char	1	XXXX
10	X frequency division code 2		Short?int	2	XXXX
						11	X frequency division code 3		unsigned?char	1	XXXX
12	Keep		char	12
						13	Colour moment battle array code		unsigned?char	1
14	Password	0000	Short?int	2	0-does not encrypt

Wherein, reconstruction mode is represented with 7 bits, specifically sees table 2:

Table 2: reconstruction mode

Code (7)	Explanation
		?00	SDRAM has the data of every each pixel of frame, 1 two field picture that the output total data obtains rebuilding
?01	SDRAM has the data of every frame 1 row, repeats to export capable 1 two field picture of rebuilding of N
		?02	SDRAM has the data of every frame 2 row, repeats to export the first capable row of N/2 and repeats to export second capable capable 1 two field picture of then rebuilding of N/2 again
?03	SDRAM has the data of every frame 2 row, repeats to export the first capable row of N/4, repeats to export the second capable row of N/2 again, repeats to export the first capable row of N/4 again, then rebuilds the wide white window signal of 1 two field picture * * *
		?04	SDRAM has the data of 1 each pixel of frame, rebuilds first two field picture identical with depositing image (the 2nd relative the 1st translation 20 pixels), and later every frame moves 40 pixels relative to preceding frame horizontal direction circulation
?05	SDRAM has the data of 1 each pixel of frame, rebuilds first two field picture identical with depositing image (the 2nd relative the 1st translation 15 pixels), and later every frame moves 30 pixels relative to preceding frame horizontal direction circulation
		?06	SDRAM has the data of 1 each pixel of frame, rebuilds first two field picture identical with depositing image (the 2nd relative the 1st translation 10 pixels), and later every frame moves 20 pixels relative to preceding frame horizontal direction circulation
?07	SDRAM has the data of 1 each pixel of frame, rebuilds first two field picture identical with depositing image (the 2nd relative the 1st translation 20 pixels), and 240 to 1680 pixels of the every row of later every frame move 40 pixels relative to the datacycle of the preceding every row of frame
		?08	SDRAM has the data of 1 each pixel of frame, rebuilds first two field picture identical with depositing image (the 2nd relative the 1st translation 15 pixels), and 240 to 1680 pixels of the every row of later every frame move 30 pixels relative to the datacycle of the preceding every row of frame
?09	SDRAM has the data of 1 each pixel of frame, rebuilds first two field picture identical with depositing image (the 2nd relative the 1st translation 10 pixels), and 240 to 1680 pixels of the every row of later every frame move 20 pixels relative to the datacycle of the preceding every row of frame
		?0A	SDRAM has the data of 1 each pixel of frame; Rebuild first two field picture identical with depositing image (the 2nd relative the 1st translation 20 pixels); The 80th row of later every frame is to 1004 row, and 240 to 1680 pixels of each row move 40 pixels relative to the datacycle of the preceding every row of frame
?0B	SDRAM has the data of 1 each pixel of frame; Rebuild first two field picture identical with depositing image (the 2nd relative the 1st translation 15 pixels); The 80th row of later every frame is to 1004 row, and 240 to 1680 pixels of each row move 30 pixels relative to the datacycle of the preceding every row of frame
		0C	SDRAM has the data of 1 each pixel of frame; Rebuild first two field picture identical with depositing image (the 2nd relative the 1st translation 10 pixels); The 80th row of later every frame is to 1004 row, and 240 to 1680 pixels of each row move 20 pixels relative to the datacycle of the preceding every row of frame
0D	SDRAM has the data of 1 each pixel of frame; Rebuild first two field picture identical with depositing image (the 2nd relative the 1st translation 20 pixels); The 80th row of later every frame is gone to 1004 to 590 row and the 670th, and 240 to 1680 pixels of each row move 40 pixels relative to the datacycle of the preceding every row of frame
		0E	SDRAM has the data of 1 each pixel of frame; Rebuild first two field picture identical with depositing image (the 2nd relative the 1st translation 15 pixels); The 80th row of later every frame is gone to 1004 to 590 row and the 670th, and 240 to 1680 pixels of each row move 30 pixels relative to the datacycle of the preceding every row of frame
0F	SDRAM has the data of 1 each pixel of frame; Rebuild first two field picture identical with depositing image (the 2nd relative the 1st translation 10 pixels); The 80th row of later every frame is gone to 1004 to 590 row and the 670th, and 240 to 1680 pixels of each row move 20 pixels relative to the datacycle of the preceding every row of frame
		20	The APL signal reproduction
21	Sdtv multifrequence reappears
		22	12 black 12 white AV tests
23(A3)	PEONY CARDAV test
		24	Every 5 points of dynamic definition
25	Every 4.5 points of dynamic definition
		40-43	The hangover signal reproduction.40poda 41pobr 42nada 43nabr
* *	Wait to expand

Wherein, colour moment battle array code is specifically seen table 3

Table 3: colour moment battle array code

Code	Applicable situation	Remarks
			00	VGA	Matrix, HDMI circuit are not worked
01	High definition	The order matrix circuit is chosen corresponding coefficient
			05	SD	The order matrix circuit is chosen corresponding coefficient
07	SD YCbCr	Do not make matrixing fxt07/11/08
			Other		Wouldn't use

Step S202; CPU instructs according to software initialization and in Installed System Memory, sets up the data buffer zone; And the DMA data transfer mode is set, instruction is carried out the parameter setting to the signal play-out buffer, the start signal play-out buffer according to hardware initialization; Generate the DMA request that comprises the signal file name according to the signal file name, and the DMA request is sent to dma controller.For from external memory storage (like USB flash disk, CF card, SD card etc.) read test signal file with to signal play-out buffer dateout; CPU instructs according to software initialization and in Installed System Memory, sets up data buffer zone (n*8*512 byte); And its address changed into physical address, the zero clearing of the busy sign of dma controller.Then, DCSRC0 among the CPU and the zero clearing of DCDST0 register; In the DISRC0 register of the source start address that the DMA transfer of data is set in the CPU; In the DIDST0 register of the purpose start address that the DMA transfer of data is set in the CPU; Bus location and variation pattern that DMA transfer of data source address is set are in the DISRCC0 register; The moment, bus location and variation pattern take place in the DIDSTC0 register in the interruption that DMA transfer of data destination address is set; DMA control register DCON0 is set, comprises the DMA transmission quantity.Set up interrupt routine for the DMA transfer of data at last; Comprise: select interrupt mode, open interruption, call request_irq () function installation interrupt handling routine, the descriptor that is about to above-mentioned interrupt handling routine and relevant this interruption that is arranged in the overall array of irq_desc [] couples together.Then, CPU carries out the parameter setting according to hardware initialization instruction to the signal play-out buffer, and these parameter settings comprise the FPGA related register is provided with parameter; The scanning timing parameters is set: horizontal pulse width, row crop, row effectively, the row sum, the field pulse width, a crop, effectively, a sum; The signalization location register: signal original position base address, signal original position side-play amount, base address, signal terminating position, the signal terminating position offset loads the base address; LOGO related register: LOGO storage original position base address is set, storage original position side-play amount, storage final position base address, storage final position side-play amount is presented at which row of which row, motion mode, line width and col width.Then, send the FPGA starting command, the start signal play-out buffer.

Step S203, CPU is to data buffer zone output LOGO data content.Promptly export the brand mark of DTV to be measured, like tree peony sign image data.

Step S204, dma controller receive the DMA request, search the FAT table according to the signal file name and confirm the externally position in the memory of corresponding test signal file.In addition, n the data buffering area that dma controller will be gone back Installed System Memory is mounted to idle queues, data buffer zone full scale will counter O reset, the zero clearing of the busy sign of dma controller.

Step S205, dma controller read the data buffer zone of some byte datas to Installed System Memory at every turn from the test signal file.For example from the test signal file, read in the data buffer zone of data to a 8*512 byte-sized of 6*512 byte at every turn, after Data Format Transform, it is suspended in the busy formation, data buffer zone full scale will counter adds one.

Step S206, dma controller start the DMA data transfer mode the some byte datas in the data buffer zone are sent to the play buffer in the signal play-out buffer.If dma controller is busy be masked as 0 and data buffer zone full scale will counter be not 0, then be changed to 1 to the busy sign of dma controller; DCSRC0 and the zero clearing of DCDST0 register; The source start address register DISRC0 of DMA transfer of data is set; The purpose start address register DIDST0 of DMA transfer of data is set; Shielding DMA interrupts; Play buffer in data to the signal play-out buffer of a 8*512 byte of transmission; Data buffer zone full scale will counter subtracts one, the data buffer zone of having sent is suspended in the idle queues zero clearing of the busy sign of dma controller; Open DMA and interrupt, remove the shielding that DMA is interrupted.Wherein, The operation principle of DMA transfer of data and interrupt handling routine and process are: dma controller is waited for the DMA request; If CPU produces a DMA data transfer request, after promptly dma controller detected the DMA request, dma controller was just examined content among the register DCON [19:0] among the CPU among the CURR_TC (in the DSTAT register); Examine content among the register DISRC0 among the DCSRC0, examine DCDST0 to content among the register DIDST0.Dma controller reads in data from the source address that the DCSRC0 register is represented; And it is write in the destination address that the DCDST0 register representes, every transmission primaries CURR_TC subtracts one, and DCSRC0 and DCDST0 subtract corresponding value; Repeat said process, be kept to zero until CURR_TC.When CURR_TC was kept to zero, dma controller sent interrupt requests.When dma controller took place to interrupt, the program counter of CPU was changed to 0x18, and carried out the code at 0x18 place.Because a statement that jumps to vector_irq () function is deposited at the 0x18 place,, carries out CPU so jumping to this function place.For example vector_irq () function is accomplished following task: judge this DMA interrupt source interruption has taken place, and the interrupt number that calculates it is 17; In the overall array of irq_desc [], find the element irq_desc [17] that describes this interruption according to interrupt number 17, from the action pointer member of this element chained list pointed, find this Interrupt Process function, carry out above-mentioned interrupt handling routine.

Step S207, dma controller judge whether the DMA transfer of data finishes, if finish, and execution in step S206 then, otherwise, execution in step S208.

Step S208, dma controller judge whether signal file reads and finish, do not finish if read, and execution in step S205 then, otherwise, execution in step S209.

Step S209, output interface circuit is sent to digital television to be measured with the test signal file of current storage in the play buffer.

With reference to figure 3; The device 21 of digital TV test signal generator of the present invention; Comprise input interface circuit 211, CPU 212, user interface 213, Installed System Memory 214, signal play-out buffer 215, output interface circuit 216 and DMA (DirectMemory Access, direct memory access) controller 217.Wherein, Dma controller 217; Be used to receive the DMA request that comprises the signal file name that CPU 212 sends; Read corresponding test signal file preset data buffer area to the Installed System Memory 214 according to DMA request and through input interface circuit 211 from external memory storage, the test signal file is read the play buffer the signal play-out buffer 215 from the data buffer area of Installed System Memory 214.

With reference to figure 4, dma controller 217 of the present invention comprises: DMA asks receiver module 2171, is used to receive the DMA request that comprises the signal file name that CPU212 sends.First transport module 2172 is used for reading the data buffer area that corresponding test signal file is preset to Installed System Memory 214 according to the DMA request and through input interface circuit 211 from external memory storage.Second transport module 2173 is used for the test signal file is read the preset play buffer of signal play-out buffer 215 from the data buffer area of Installed System Memory 214.Wherein: first transport module 2172 further comprises: ff submodule 2174 is used for searching the FAT table according to the signal file name and confirms the externally position of memory of corresponding test signal file; First reading submodule 2175 is used for reading the data buffer zone of some byte datas to Installed System Memory 214 from the test signal file at every turn.Second transport module 2173 further comprises: second reading submodule 2176 is used for starting the DMA data transfer mode some byte datas of the data buffer zone of Installed System Memory 214 is sent to the play buffer in the signal play-out buffer 215; Judge submodule 2177, be used to judge whether the DMA transfer of data of second reading submodule 2173 finishes, if do not finish; Then indicate second reading submodule 2176 to continue the DMA transfer of data; Otherwise, judge whether signal file reads to finish, if do not finish; Then indicate first reading submodule 2175 to continue reading of signal file, otherwise finish.

With reference to figure 5, the model of CPU 212 of the present invention is ARM9CPU, comprising: receiver module 2121 is used to receive software initialization instruction, hardware initialization instruction and signal file name from user interface 213.Software initialization module 2122 is used for setting up the data buffer zone according to software initialization instruction at Installed System Memory 214, and the DMA data transfer mode is set.Hardware initialization module 2123 is used for signal play-out buffer 215 being carried out the parameter setting, start signal play-out buffer 215 according to hardware initialization instruction.DMA request sending module 2124 is used for generating the DMA request that comprises the signal file name according to the signal file name, and the DMA request is sent to dma controller 217.

The present invention adopts DMA data-transmission mode transmission data; Each data buffer zone of from external memory storage, reading the test signal file of needs to Installed System Memory; Start the DMA data transfer mode then the test signal file in the data buffer zone of Installed System Memory is sent to the play buffer in the signal play-out buffer; Thereby saved the process that needs again the test signal file to be sent to from the data buffer zone of Installed System Memory when earlier the test signal file read being got data buffer zone preset among the CPU and calling the data buffer zone the CPU; Therefore, avoided data transmission procedure repetition, shortened data transmission period, improved the operational efficiency of CPU.

It will be appreciated by those skilled in the art that: accompanying drawing is the sketch map of a preferred embodiment, and module in the accompanying drawing or flow process might not be that embodiment of the present invention is necessary.The scheme of the content record of claim also is the protection range of the embodiment of the invention.Module in the device among the embodiment can be described according to embodiment and be distributed in the device of embodiment, also can carry out respective change and be arranged in the one or more devices that are different from present embodiment.The module of the foregoing description can be merged into a module, also can further split into a plurality of submodules.

Above embodiment describes preferred implementation of the present invention; Be not that scope of the present invention is limited; Design under the prerequisite of spirit not breaking away from the present invention; Various distortion and improvement that the common engineers and technicians in this area make technical scheme of the present invention all should fall in the definite protection range of claims of the present invention.

Claims (7)

1. the player method of a digital TV test signal generator is characterized in that, may further comprise the steps:

CPU receives software initialization instruction, hardware initialization instruction and the test signal filename from user interface;

Said CPU sets up the data buffer zone according to said software initialization instruction in Installed System Memory; And the DMA data transfer mode is set; According to said hardware initialization instruction the signal play-out buffer is carried out the parameter setting; Open said signal play-out buffer, generate the DMA request that comprises the test signal filename, and said DMA request is sent to dma controller according to said test signal filename;

Said dma controller reads corresponding test signal file to said data buffer zone according to said DMA request and through input interface circuit from external memory storage;

Said dma controller adopts the DMA data transfer mode said test signal file to be transferred to the play buffer of said signal play-out buffer from said data buffer zone;

Output interface circuit is sent to digital television to be measured with the test signal file of current storage in the said play buffer.

2. player method according to claim 1 is characterized in that, saidly reads corresponding test signal file to said data buffer zone according to DMA request and through input interface circuit from external memory storage, may further comprise the steps:

Said dma controller receives said DMA request;

Said dma controller is searched the FAT table according to the test signal filename that comprises in the said DMA request and is confirmed the corresponding position of test signal file in said external memory storage;

Said dma controller reads some byte datas to said data buffer zone at every turn from said test signal file;

Said dma controller starts the DMA data transfer mode the some byte datas in the said data buffer zone is sent to said play buffer;

Said dma controller judges whether said DMA transfer of data finishes, if do not finish, then continues said DMA transfer of data; Otherwise, judge whether said test signal file reads to finish, if do not finish; Then continue reading of said test signal file, otherwise finish.

3. an enforcement of rights requires the digital TV test signal generator of 1 or 2 said player methods; Comprise the input interface circuit, CPU, user interface, Installed System Memory, signal play-out buffer and the output interface circuit that connect successively; It is characterized in that, also comprise:

Dma controller; Be used to receive the DMA request that comprises the test signal filename that said CPU sends; Read corresponding test signal file preset data buffer area to the said Installed System Memory according to said DMA request and through said input interface circuit from external memory storage, said test signal file is read the play buffer the said signal play-out buffer from the data buffer area of said Installed System Memory.

4. digital TV test signal generator according to claim 3 is characterized in that, said dma controller comprises:

DMA asks receiver module, is used to receive the DMA request that comprises the test signal filename that said CPU sends;

First transport module is used for reading corresponding test signal file to the preset data buffer area of said Installed System Memory according to said DMA request and through said input interface circuit from external memory storage;

Second transport module is used for said test signal file is read the preset play buffer of said signal play-out buffer from the data buffer area of said Installed System Memory.

5. digital TV test signal generator according to claim 4 is characterized in that, said first transport module further comprises:

The ff submodule is used for searching the FAT table according to said test signal filename and confirms the position of corresponding test signal file at said external memory storage;

First reading submodule is used for reading the data buffer zone of some byte datas to said Installed System Memory from said test signal file at every turn.

6. digital TV test signal generator according to claim 5 is characterized in that, said second transport module further comprises:

Second reading submodule is used for starting the DMA data transfer mode some byte datas of the data buffer zone of said Installed System Memory is sent to the play buffer in the said signal play-out buffer;

Judge submodule, be used to judge whether the DMA transfer of data of said second reading submodule finishes, if do not finish; Then indicate said second reading submodule to continue said DMA transfer of data; Otherwise, judge whether said test signal file reads to finish, if do not finish; Then indicate said first reading submodule to continue reading of said test signal file, otherwise finish.

7. digital TV test signal generator according to claim 6 is characterized in that, said CPU comprises:

Receiver module is used to receive software initialization instruction, hardware initialization instruction and test signal filename from said user interface;

The software initialization module is used for setting up the data buffer zone according to said software initialization instruction at said Installed System Memory, and establishes the said DMA data transfer mode of arm;

The hardware initialization module is used for according to said hardware initialization instruction said signal play-out buffer being carried out the parameter setting, opens said signal play-out buffer;

The DMA request sending module is used for generating the said DMA request that comprises the test signal filename according to said test signal filename, and said DMA request is sent to said dma controller.

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