CN101533826B - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN101533826B CN101533826B CN200810081784XA CN200810081784A CN101533826B CN 101533826 B CN101533826 B CN 101533826B CN 200810081784X A CN200810081784X A CN 200810081784XA CN 200810081784 A CN200810081784 A CN 200810081784A CN 101533826 B CN101533826 B CN 101533826B
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Abstract
The invention provides a semiconductor device and a production method thereof, and the semiconductor device comprises a substrate, a buried layer which is formed inside the substrate and comprises an insulating area; a deep trench contact structure formed in the substrate and composed of a conductive material and a laying which is formed on a side wall of the conductive material, the conductive material beingelectrically connected to the substrate; and a doping area formed between the deep trench contact structure and the substrate, wherein the conductive material of the deep trench contact structure extends to the doping area, the laying extends to the insulation area, the laying is connected to the insulation area and covers the side wall of the conductive material so as to form an insulation structure. The semiconductor device and the production method thereof can significantly increase the quantity of elements which can be configured inside a single wafer and raise the element density, and when doped polysilicon is selected as the conducting material inside the deep trench contact structure, the stress between an oxide-containing pad layer and an epitaxial layer which is caused by crystal lattice difference can be buffered, thereby raising the stability and the efficacy of the elements.
Description
Technical field
The invention relates to a kind of semiconductor device and manufacturing approach thereof, particularly relevant for deep trenches contact structures and manufacturing approach thereof.
Background technology
In semiconductor technology now; In order to reach the operation of single-chip system (single-chip system); Be that controller, memory, low voltage operated circuit and the power component height of operation with high pressure are integrated on the single wafer; Wherein the research and development kind of power component includes several kinds of rectilinear double diffusion metal-oxide semiconductor transistor (VDMOS), insulated gate electrode two-carrier transistor (IGBT), transverse type power transistors (LDMOS) etc., and its research and development purpose is to improve the loss that power supply conversion efficiency reduces the energy.Owing on single wafer, high-pressure crystal tube elements and low voltage CMOS circuit element need be provided simultaneously, therefore on manufacturing process, need to make isolation structure in order to isolated adjacent element.
See also Fig. 1, it shows the profile of existing semiconductor element.Generally can use by the formed deep trenches insulation system 20 of dielectric material and isolate contiguous element, therefore can the individual power parameter of else controlling the element of isolating.But deep trenches insulation system 20 is easy to generate parasitic capacitance.In addition, between element active region and substrate 10, bury oxide layer 30, also can produce parasitic capacitance.When element is finished drilling when doing at a voltage environment, can cause coupling effect because above-mentioned parasitic capacitance produces to charge, this effect is especially obvious in high voltage device.Capacitance coupling effect not only makes the characteristic performance of neighbouring element be affected, even can have influence on the high-low pressure element that other are electrical connected by the base material degree varies.
Continuous progress along with semiconductor fabrication process; The size of integrated circuit is more and more little, circuit is more and more close, and work clock is more and more fast simultaneously, and the parasitic resistance effect in the wafer in the circuit, parasitic capacitance effect are also just more and more serious; And then frequency can't be promoted again; This is called, and capacitance-resistance postpones, capacitance-resistance sluggish (RCDelay), and RC Delay not only hinders clock and grows up, and also can increase the meaningless power consumption of circuit simultaneously.These effects produce influence in various degree to the running of circuit, also cause the doubt to circuit stability, and especially in epoch of circuit high-speed cruising now, circuit is also more and more lower to the tolerance of these interference, more deepens the seriousness of this problem.
Therefore having to provide a kind of semiconductor device and forming method thereof, to overcome the deficiency of prior art.
Summary of the invention
, other and the object of the invention above-mentioned for reaching, the present invention provides a kind of semiconductor device, comprising:
One substrate; One buried regions is formed in the described substrate, and wherein said buried regions comprises an insulation layer; One deep trenches contact structures; Be formed in the described substrate; Wherein said deep trenches contact structures comprise an electric conducting material and a laying, and wherein said laying is formed on the sidewall of described electric conducting material, and described electric conducting material and described substrate electric connection; An and doped region; Be formed between said deep trenches contact structures and the said substrate; The electric conducting material of wherein said deep trenches contact structures extends to said doped region; Said laying extends to the insulation layer of said buried regions, and said laying links to each other with the insulation layer of said buried regions and covers the sidewall of said electric conducting material, to be formed for the isolation structure of quarantine component.
The present invention also provides a kind of manufacturing approach of semiconductor device, comprises the following steps: to provide a substrate, and it has a buried regions and is positioned at wherein, and wherein said buried regions comprises an insulation layer; In described substrate, form deep trenches contact structures; Wherein said deep trenches contact structures comprise an electric conducting material and a laying; Wherein said laying is formed on the sidewall of described electric conducting material, and described electric conducting material and described substrate electric connection; And form a doped region between said deep trenches contact structures and said substrate; The electric conducting material of wherein said deep trenches contact structures extends to said doped region; Said laying extends to the insulation layer of said buried regions; Said laying links to each other with the insulation layer of said buried regions and covers the sidewall of said electric conducting material, to be formed for the isolation structure of quarantine component.
Description of drawings
Fig. 1 shows the profile of existing semiconductor element.
Fig. 2 to Fig. 9 shows the profile according to the formation deep trenches contact structures of the embodiment of the invention.
Drawing reference numeral
10～substrate; 20～deep trenches insulation system;
30～bury oxide layer; 100～substrate;
120～conductor buried regions; 140～insulating buried layer;
160～epitaxial layer; 180～cover curtain layer;
200～the first deep trenches; 210～laying;
220～the second deep trenches; 230～doped region;
260～deep trenches contact structures; 300～interlayer dielectric layer;
310～barrier layer; 320～contact plunger;
330～metal level.
Embodiment
Embodiments of the invention provide a kind of semiconductor device and manufacturing approach thereof.About the manufacture of each embodiment with occupation mode is following details, and follow diagram explanation.Wherein, the components identical numbering of using in graphic and the specification is the identical or similar elements of expression.And in graphic, for the purpose of clear and convenient explanation, shape and the thickness of relevant embodiment or the situation that is not inconsistent reality is arranged.And following the description explained to various elements or its integration of device of the present invention especially; Yet, it should be noted that said elements be not particularly limited in show or description person; But can have the knack of the various forms that the personage learnt of this skill; In addition, when the layer of material layer is when being positioned on another material layer or the substrate, it can be to be located immediately at its surface to go up or be inserted with in addition other intermediary layers.
Fig. 2 to Fig. 9 is the profile that shows according to a kind of semiconductor device of making of the embodiment of the invention.Please refer to Fig. 2, a substrate 100 is provided, can have conductor buried regions 120, insulating buried layer 140 on it, and epitaxial layer 160.Substrate 100 can comprise the base material of silicon or other suitable semi-conducting material.Insulating buried layer 140 can comprise the oxide like silicon dioxide etc.After forming a cover curtain layer 180 in epitaxial layer 160 tops, can above-mentioned cover curtain layer 180 be carried out patterning, to expose the surface of epitaxial layer to be removed 160.The resistance of conductor buried regions 120 can be less than the resistance of substrate 100.In other embodiments, when enough hour of the resistance of substrate 100, can there be (not being shown among the figure) in conductor buried regions 120.
Please refer to Fig. 3; At the cover curtain layer 180 that forms patterning after above the epitaxial layer 160; Can carry out an etching manufacturing process epitaxial layer 160 that cover curtain layer 180 is exposed is removed, to form one first deep trenches 200, wherein formed first deep trenches 200 exposes the upper surface of insulating buried layer 140.In other embodiments; Can carry out the epitaxial layer 160 that the etching manufacturing process is exposed cover curtain layer 180; And the insulating buried layer 140 that is positioned at the part of epitaxial layer 160 belows is removed; To form first deep trenches 200, wherein formed first deep trenches 200 exposes the part (not being shown among the figure) of the upper surface below of insulating buried layer 140.Then cover curtain layer 180 is removed.
Please refer to Fig. 4, after first deep trenches 200 forms, can on the sidewall of first deep trenches 200 and basal surface, form laying 210.Laying 210 also may extend on the upper surface of epitaxial layer 160.Laying 210 can comprise for example tetraethoxysilane (tetraethoxy silane, oxide TEOS).Then can carry out an etching manufacturing process; The laying that is positioned at insulating buried layer 140 tops 210 so that first deep trenches 200 is exposed is removed; And can be after laying 210 is removed, the insulating buried layer 140 that continues first deep trenches 200 is exposed is removed, and forms second deep trenches 220 with the below in first deep trenches 200; As shown in Figure 5, and keep the laying 210 on the sidewall that is positioned at first deep trenches 200.Please refer to Fig. 5, the upper surface that second deep trenches 220 can expose conductor buried regions 120 that forms.In another embodiment; The etching manufacturing process of being carried out can be after insulating buried layer 140 be removed; The conductor buried regions 120 of the part that more first deep trenches 200 is exposed is removed, and formed second deep trenches 220 exposes the part (not being shown among the figure) of the upper surface below of conductor buried regions 120.In other embodiments, when conductor buried regions 120 did not exist, formed second deep trenches 220 can expose the surface of the substrate 100 that is positioned at insulating buried layer 140 belows or the part of lower face.
Please refer to Fig. 6, then can carry out a doping manufacturing process, to form a doped region 230 in the conductor buried regions 120 that is exposed in second deep trenches 220.After the doping manufacturing process, can carry out an annealing manufacturing process again, make doped region 230 toward laterally reaching direction diffusion longitudinally; For example; In the conductor buried regions 120 of horizontal proliferation to insulating buried layer 140 belows, and in the darker zone of longitudinal diffusion to conductor buried regions 120, as shown in Figure 6.Doped region 230 can have the conductivity type identical with conductor buried regions 120.In an embodiment, doped region 230 and conductor buried regions 120 are all N type conductivity type.The doping content of doped region 230 generally can be greater than the doping content of conductor buried regions 120.The formation of doped region 230 can provide preferable implant uniformity (uniformity), forming the resistance at preferable interface, and more stable (ohmic contact) conductive member.In other embodiments, when enough hour of the resistance of substrate 100, conductor buried regions 120 can not exist, so doped region 230 can be formed in the substrate 100 that second deep trenches 220 exposed (not being shown among the figure).In another embodiment, can not form doped region 230 (not being shown among the figure).
Please refer to Fig. 7, after doped region 230 forms, then can form an electric conducting material 240 filling first deep trenches 200 and second deep trenches 220, and electric conducting material 240 may extend on the surface of laying 210.Electric conducting material 240 can comprise the conductive materials of the polysilicon that for example mixes.In a preferred embodiment, electric conducting material 240 is under the environment of the gas with impurity, with the polysilicon of the formed doping of (in-situ) chemical vapour deposition technique synchronously.Electric conducting material 240, doped region 230 and conductor buried regions 120 can be identical conductivity type.In an embodiment, electric conducting material 240, doped region 230 and conductor buried regions 120 are all N type conductivity type.In a preferred embodiment, electric conducting material 240 is the polysilicon with N type doping impurity.In other embodiment, electric conducting material 240 can comprise the for example metal of tungsten or aluminium etc.
Because it is big with epitaxial layer 160 crystal lattice difference degree each other generally to comprise the laying 210 of oxide; Therefore be easy to generate stress at its joint interface place; The high temperature manufacturing process of especially in subsequent fabrication steps, being carried out more possibly increase the otherness of lattice and causes structural defective.The polysilicon of selecting to mix can cushion the stress problem between the above-mentioned material as electric conducting material 240, and then the stability of lift elements and effect thereof.
Please refer to Fig. 8, then can carry out an etch-back (etching back) manufacturing process, remove and form deep trenches contact structures 260 with the electric conducting material 240 that will be formed at laying 210 tops.
Because in the deep trenches contact structures 260; The electric conducting material 240 that comprises the polysilicon of doping can be under the environment of the gas with impurity; Form with synchronous chemical vapour deposition (CVD) mode, and need not carry out extra doping manufacturing process, to avoid mixing the issuable pollution problem of manufacturing process; Or the problem that reduces of the element efficiency that causes of diffusion of impurities, so deep trenches contact structures 260 can be designed in the position near main element.And because the sidewall of deep trenches contact structures 260 has the for example laying with insulating effect 210 of oxide; Therefore deep trenches contact structures 260 also can be used as the isolation structure of isolated element; In an embodiment, can the deep trenches contact structures active area of 260 definition elements.Among another embodiment, can deep trenches contact structures 260 and the active area of insulating buried layer 140 definition elements.
Please refer to Fig. 9; After forming deep trenches contact structures 260, can above deep trenches contact structures 260 and laying 210, continue to form interlayer dielectric layer 300 contact plunger 320 that passes interlayer dielectric layer 300 and electrically connect with deep trenches contact structures 260; Tungsten plug for example; In an embodiment, the sidewall of contact plunger 320 and bottom can have the barrier layer 310 of titanium for example or titanium nitride, and form the metal level 330 that is positioned at contact plunger 320 tops.Conductor buried regions 120, doped region 230 and deep trenches contact structures 260 can electrically connect with outside by contact plunger 320 and metal level 330.
Because the electric conducting material 240 in the deep trenches contact structures 260; Itself and conductor buried regions 120 (or substrate 100) and doped region 230 can electrically connect with outside by contact plunger 320 and metal level 330; Therefore when because executive component and in insulating buried layer 140 and laying 210 during the spurious charge of formation; Can be with the external power source ground connection that electrically connects with electric conducting material 240, conductor buried regions 120 (or substrate 100) and doped region 230; Make the spurious charge can be by conducting to the outside with the conductor buried regions 120 (or substrate 100) of insulating buried layer 140 and laying 210 adjacency with electric conducting material 240 respectively, to avoid because the noise problem that parasitic capacitance was produced.The voltage of conductor buried regions 120 (or substrate 100) also can be controlled by the outside via deep trenches contact structures 260.
In semiconductor device that embodiments of the invention disclosed and forming process thereof; Be to be beneficial to have insulating buried layer and conductor buried regions in substrate wherein; Form the deep trenches contact structures, wherein the deep trenches contact structures comprise electric conducting material and are positioned at the laying on the sidewall of electric conducting material.
The electric conducting material of deep trenches contact structures can be to have under the gaseous environment of impurity; Form with synchronous vapour deposition mode; And need not carry out extra doping manufacturing process; With the problem of avoiding issuable pollution or element efficiency to reduce, so the deep trenches contact structures can be designed in than the position near main element.The laying of deep trenches contact structures is the oxide layer with insulation characterisitic, so the deep trenches contact structures can be as the isolation structure of isolated component, more can be in order to the active area of definition element, and can reduce the area of the needed active area of single element.For the above reasons, according to the formed deep trenches contact structures of embodiments of the invention, it can significantly promote the parts number that can dispose in the single wafer and improve component density.When the polysilicon that select to mix during as the electric conducting material in the deep trenches contact structures, its can the oxidiferous laying of buffers packet and epitaxial layer between because the stress that crystal lattice difference caused, with the stability and the effect thereof of lift elements.
Electric conducting material in the deep trenches contact structures, itself and conductor buried regions (or substrate) and doped region can be by contact plunger and metal level and outside the electric connections.Therefore since executive component and in insulating buried layer or laying formed spurious charge, it can conduct to the outside via electric conducting material, conductor buried regions (or substrate) and doped region, to avoid because noise problem that parasitic capacitance was produced.The voltage of conductor buried regions (or substrate) also can be controlled by the outside via the deep trenches contact structures.The formation of doped region can provide preferable implant uniformity (uniformity), and between the electric conducting material of conductor buried regions (or substrate) and deep trenches contact structures, and the resistance at preferable interface is provided, and more stable (ohmic contact) conductive member.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting the present invention, anyly is familiar with this operator, do not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, thus protection scope of the present invention when with claims were defined is as the criterion.
Claims (9)
1. a semiconductor device is characterized in that, described semiconductor device comprises:
One substrate;
One buried regions is formed in the described substrate, and wherein said buried regions comprises an insulation layer;
One deep trenches contact structures; Be formed in the described substrate; Wherein said deep trenches contact structures comprise an electric conducting material and a laying, and wherein said laying is formed on the sidewall of described electric conducting material, and described electric conducting material and described substrate electric connection; And
One doped region; Be formed between said deep trenches contact structures and the said substrate; The electric conducting material of wherein said deep trenches contact structures extends to said doped region; Said laying extends to the insulation layer of said buried regions, and said laying links to each other with the insulation layer of said buried regions and covers the sidewall of said electric conducting material, to be formed for the isolation structure of quarantine component.
2. semiconductor device as claimed in claim 1 is characterized in that described electric conducting material comprises the polysilicon of doping.
3. semiconductor device as claimed in claim 1 is characterized in that described buried regions more comprises a conductor region.
4. the manufacturing approach of a semiconductor device comprises the following steps:
One substrate is provided, and it has a buried regions and is positioned at wherein, and wherein said buried regions comprises an insulation layer;
In described substrate, form deep trenches contact structures; Wherein said deep trenches contact structures comprise an electric conducting material and a laying; Wherein said laying is formed on the sidewall of described electric conducting material, and described electric conducting material and described substrate electric connection; And
Form a doped region between said deep trenches contact structures and said substrate; The electric conducting material of wherein said deep trenches contact structures extends to said doped region; Said laying extends to the insulation layer of said buried regions; Said laying links to each other with the insulation layer of said buried regions and covers the sidewall of said electric conducting material, to be formed for the isolation structure of quarantine component.
5. the manufacturing approach of semiconductor device as claimed in claim 4 is characterized in that, the manufacturing approach of described semiconductor device more is included in and forms described doped region between described deep trenches contact structures and the described substrate.
6. the manufacturing approach of semiconductor device as claimed in claim 4 is characterized in that, described buried regions more comprises a conductor region.
7. the manufacturing approach of semiconductor device as claimed in claim 4 is characterized in that, the manufacturing approach of described deep trenches contact structures comprises the following steps:
In described substrate, form one first deep trenches to expose described buried regions;
On the sidewall of described first deep trenches, form described laying;
In described buried regions, form one second deep trenches, wherein said second deep trenches is positioned at the below of described first deep trenches, and described second deep trenches is communicated with described first deep trenches; And
Form described electric conducting material, to fill described first deep trenches and described second deep trenches.
8. the manufacturing approach of semiconductor device as claimed in claim 7 is characterized in that, described first deep trenches exposes described insulation layer.
9. the manufacturing approach of semiconductor device as claimed in claim 7 is characterized in that, described buried regions more comprises a conductor region.
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| CN200810081784XA CN101533826B (en) | 2008-03-13 | 2008-03-13 | Semiconductor device and production method thereof |
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| CN200810081784XA CN101533826B (en) | 2008-03-13 | 2008-03-13 | Semiconductor device and production method thereof |
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| CN101533826B true CN101533826B (en) | 2012-07-04 |
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| CN102142392B (en) * | 2010-01-28 | 2014-03-12 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacture method thereof |
| CN102646621B (en) * | 2011-02-16 | 2015-01-21 | 世界先进积体电路股份有限公司 | Preparation method of deep trench insulation structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1783480A (en) * | 2004-11-30 | 2006-06-07 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| CN1797762A (en) * | 2004-11-24 | 2006-07-05 | 中国台湾积体电路制造股份有限公司 | Semiconductor structure of wafer and method for forming same |
| CN1934696A (en) * | 2004-01-23 | 2007-03-21 | Atmel德国有限公司 | Integrated circuit comprising laterally dielectrically isolated active regions above an electrically contacted buried material, and method for producing the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1934696A (en) * | 2004-01-23 | 2007-03-21 | Atmel德国有限公司 | Integrated circuit comprising laterally dielectrically isolated active regions above an electrically contacted buried material, and method for producing the same |
| CN1797762A (en) * | 2004-11-24 | 2006-07-05 | 中国台湾积体电路制造股份有限公司 | Semiconductor structure of wafer and method for forming same |
| CN1783480A (en) * | 2004-11-30 | 2006-06-07 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
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| Title |
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| US2008/0026556A1A1 2008.01.31 |
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