CN101527164B - Data reading circuit and method - Google Patents
Data reading circuit and method Download PDFInfo
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- CN101527164B CN101527164B CN2008100831476A CN200810083147A CN101527164B CN 101527164 B CN101527164 B CN 101527164B CN 2008100831476 A CN2008100831476 A CN 2008100831476A CN 200810083147 A CN200810083147 A CN 200810083147A CN 101527164 B CN101527164 B CN 101527164B
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Abstract
The present invention provides a data reading circuit and a data reading method. The data reading circuit comprises a first buffer, a second buffer, a first selector, a second selector and a third buffer, wherein the first buffer is used for receiving a first data signal and sampling the first data signal according to a first edge of a first prearranged signal to generate a second data signal; the second buffer is used for sampling the second data signal according to a second edge of a second prearranged signal to generate a third data signal; the first selector is used for selecting and outputting the second data signal or the third data signal according to the phase difference between the first prearranged signal and the second prearranged signal so as to generate a fourth data signal; the second selector is used for selecting and outputting the fourth data signal or a fifth data signal according to a selecting signal to generate a sixth data signal; and the third buffer is used for sampling the sixth data signal according to the first edge of the second prearranged signal so as to generate the fifth data signal.
Description
Technical field
The present invention is relevant for a kind of data reading circuit, more specifically, and relevant for the data reading circuit of revising in real time according to the delay situation of the data read frequency signal of storer.
Background technology
In electronic installation now, storer often is used storing various data, and this type of electronic installation can use a data read frequency signal to read the data in the storer usually.Yet along with the progress of science and technology, the circuit in the electronic installation and the configuration of every assembly are gradually complicated, the situation that the data read frequency signal may occur postponing because of these distributions and assembly.For example, the delay that the data read frequency signal causes because of joint sheet (pad), and make data read mistake occur.If this storer uses at the customized chip of volume production (Application-Specific Integrated Circuit; ASIC) on, then this kind phenomenon can cause sizable puzzlement, because the characteristic of the customized chip of each volume production all is not quite similar, as improving the problem that the data read frequency signal postpones, may causes the unstable of system and can cause puzzlement in the design.
Therefore there are many inventions to be developed with head it off.Fig. 1 illustrates the data reading circuit of prior art, and it is exposed in the U.S. Pat 6529424.As shown in Figure 1, storer 101 is in order to storage data, and the customized chip 103 of volume production provide a data read frequency signal to storer 101 with foundation as data read.In addition, the customized chip 103 of volume production has more a test port 105 to send test signal TS to storer 101, and one feedback port one 07 with from storer 101 acceptance test signal TS, the situation that postpones when the customized chip 103 of volume production is passed to storer 101 of simulating signal by this, and make system make suitable adjustment.Yet the shortcoming of this type of circuit is that it needs extra test port 105, feedback port one 07 and relevant distribution, causes the increase of cost, and has increased the step of analogue delay.Also make the burden of system increase.And, need carry out synchronization action at the input data.
Therefore, need a kind of invention of novelty to address the above problem.
Summary of the invention
Therefore, one of purpose of the present invention is for providing a kind of data reading circuit, and the data that it utilizes a plurality of signals with specific corresponding relation to be read with real-time correction are to reduce the error because of the data read that signal delay was caused.
One of purpose of the present invention is for providing a kind of data reading circuit that is used on the storer, it utilizes the data read frequency signal of reading memory data to reach the signal specific relevant with the data read frequency signal with real-time correction, to reduce the error because of the data read that signal delay was caused.
The present invention's preferred embodiment has disclosed a kind of data reading circuit, and it comprises one first buffer, one second buffer, a first selector, a second selector and one the 3rd buffer.First buffer is in order to receive one first data-signal and according to first edge of first prearranged signals first data-signal to be sampled to produce one second data-signal.Second buffer is coupled to first buffer, in order to second edge according to one second prearranged signals second data-signal is sampled to produce one the 3rd data-signal.First selector is coupled to second buffer, is used for selecting second data-signal and one of them output of the 3rd data-signal to form one the 4th data-signal according to the phase place of first, second prearranged signals.Second selector is coupled to first selector, is used for selecting signal to select the 4th data-signal and one of them output of the 5th data-signal to form one the 6th data-signal according to one.The 3rd buffer is coupled to second selector, in order to first edge according to second prearranged signals the 6th data-signal is sampled to form the 5th data-signal.
If this data reading circuit is used on the storer, then second prearranged signals is the data read frequency signal that reads the data of storer.
The present invention's preferred embodiment has also disclosed a kind of method for reading data, comprises: receive one first data-signal; Use first edge of one first prearranged signals that this first data-signal is sampled to form one second data-signal; Use second edge of one second prearranged signals that this second data-signal is sampled to form one the 3rd data-signal; Whether the phase differential of judging this first prearranged signals and this second prearranged signals greater than a predetermined value, if then with this second data-signal as the 4th data-signal, if not then with the 3rd data-signal as the 4th data-signal; And the 4th data-signal is sampled to obtain the correct data signal with first edge of this second prearranged signals.
By foregoing circuit and method, no matter be which kind of frequency data read signal is or what kind of has postpone, all can suitably be revised by the present invention, this visible this case is arranged not less than being novel invention.
Description of drawings
Fig. 1 illustrates the data reading circuit of prior art.
Fig. 2 illustrates the data reading circuit according to preferred embodiment of the present invention.
Fig. 3 illustrates the delay frequency signal that is used in data reading circuit shown in Figure 2 and produces circuit.
Fig. 4 illustrates the enable signal generator that is used in data reading circuit shown in Figure 2.
Fig. 5 illustrates the action synoptic diagram of data reading circuit shown in Figure 2.
Fig. 6 illustrates the action synoptic diagram of data reading circuit shown in Figure 2.
Fig. 7 illustrates the operating concept of the system that utilizes data reading circuit provided by the present invention.
Fig. 8 illustrates the process flow diagram according to the method for reading data of preferred embodiment of the present invention.
[primary clustering symbol description]
101 storeies
The customized chip of 103 volume productions
201 first buffers
203 second buffers
205 first selectors
207 second selectors
209 the 3rd buffers
301,303,401,403,405,407 buffers
305 selector switchs
400 enable signal generators
Embodiment
In the middle of instructions and appending claims, used some vocabulary to refer to specific assembly.The person with usual knowledge in their respective areas should understand, and hardware manufacturer may be called same assembly with different nouns.This instructions and appending claims are not used as distinguishing the mode of assembly with the difference of title, but the criterion that is used as distinguishing with the difference of assembly on function.Be an open term mentioned " comprising " in the middle of instructions and the appending claims in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to one second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly through other device or connection means if describe one first device in the literary composition.
Fig. 2 illustrates the data reading circuit 200 according to preferred embodiment of the present invention.As shown in Figure 2, data reading circuit 200 has: one first buffer 201, one second buffer 203, a first selector 205, a second selector 207 and one the 3rd buffer 209.First buffer 201 is in order to receive one first data-signal DS1 and according to first edge of one first prearranged signals PS1 this first data-signal DS1 to be sampled to produce one second data-signal DS2.Second buffer 203 is coupled to first buffer 201, in order to second edge according to one second prearranged signals PS2 the second data-signal DS2 is sampled to produce one the 3rd data-signal DS3.First selector 205 is coupled to second buffer 203, in order to selecting signal SS to select the second data-signal DS2 and one of them output of the 3rd data-signal DS3 forming one the 4th data-signal DS4 according to one, and this selects signal SS to elect according to the phase place of first, second prearranged signals PS1 and PS2.Second selector 207 is coupled to first selector 205, in order to select one of them output of the 4th data-signal DS4 and one the 5th data-signal DS5 to form one the 6th data-signal DS6 according to an enable signal ES.The 3rd buffer 209 is coupled to second selector 207, in order to first edge according to the second prearranged signals PS2 the 6th data-signal DS6 is sampled to form the 5th data-signal DS5.
Data reading circuit 200 can be applicable on the data that read storer, can also use reading in other data.When data reading circuit 200 used on storer, the second prearranged signals PS2 was that the data read frequency signal of reading memory data (generally speaking, can be system frequency, systemclock).This data reading circuit 200 can use at the customized chip of volume production (Application-SpecificIntegrated Circuit; ASIC).In this embodiment, first edge of the first prearranged signals PS1 is positive edge, and first edge of the second prearranged signals PS2 is that positive edge, second edge are for bearing edge.Use different edges to sample but also visual demand is different.
And, can utilize as shown in Figure 3 delay frequency signal to produce circuit 300 postpones a particular phases with two frequency multiplication signal PS2x2 with second prearranged signals and produces the first prearranged signals PS1, two frequencys multiplication herein are only in order to give an example, be not in order to limiting the present invention, produce the first prearranged signals PS1 with the second prearranged signals PS2 of different frequencys multiplication when the viewable design demand.As shown in Figure 3, this postpones frequency signal generation circuit 300 and comprises buffer 301,303 and selector switch 305.Its two frequency multiplication signal PS2x2 according to second prearranged signals produce delay frequency signal PS1a, PS1b, PS1c and the PS1d with different phase retardations, and selector switch 305 selects one as the first prearranged signals PS1 from postpone frequency signal PS1a, PS1b, PS1c and PS1d then.When data reading circuit 200 uses on storer, the second prearranged signals PS2 is the data read frequency signal of reading memory data, therefore the situation of the first prearranged signals PS1 after in order to simulated data reading frequency signal delay can utilize other known method earlier all candidate delay frequency signals to be analyzed once and selected candidate delay frequency signal near the true delays situation to carry out follow-up action.The foregoing description is an example to produce four phase places, and can be according to need in practice, utilize the various distortion that postpone frequency signal generation circuit 300 to extend to more phase place, in addition, postpone frequency signal generation circuit and also can use the phase-locked or lock-in circuit of simulation to realize.Though owing to realize that with numeral or simulation the mode that postpones frequency signal generation circuit is known by knowing this skill person, so do not repeat them here.
Enable signal ES can utilize enable signal generator 400 shown in Figure 4 to produce.As shown in Figure 4, enable signal generator 400 has a plurality of buffers 401,403,405 and 407, and each buffer is sampled according to the second prearranged signals PS2 and used as a delay-level.Easy speech, enable signal generator 400 postpone one with reference to selection signal RFS producing a plurality of candidate's enable signal ES1, ES2, ES3 and ES4, and export one of a plurality of candidate's enable signals and be used as enable signal ES.Same, when data reading circuit 200 uses on storer, the second prearranged signals PS2 is the data read frequency signal of reading memory data, and the detailed structure of enable signal generator 400 and mode of operation are known by knowing this skill person, so do not repeat them here.
In sum, when data-signal enters data reading circuit 200, data reading circuit 200 uses the first prearranged signals PS1 to decide should to use which phase place of data read frequency signal to come reading of data, and use enable signal ES to decide should since which frequency reading of data of the first prearranged signals PS1.Easily it can draw correct data read time point by this circuit, and compensates aforesaid signal delay problem and obtain correct data.And the viewdata signal is with the relation of the first prearranged signals PS1, and the negative edge that utilizes the second prearranged signals PS2 to sampling input data to promote the correctness of data, this partly will elaborate below.
Fig. 5 and Fig. 6 illustrate the action of data reading circuit shown in Figure 2 200, please in conjunction with referring to Fig. 2 more to understand the present invention.Figure 5 shows that when the second prearranged signals PS2 that data-signal DS1 is delayed 90 ° of phase places samples the manner of execution of data reading circuit 200.In this figure, the first prearranged signals PS1 postpones 90 ° of phase places than the second tentation data PS2.As shown in Figure 5, data-signal DS1 is formed the second data-signal DS2 by sampling backs such as the positive edge of the first prearranged signals PS1, and in this example, utilize enable signal ES to select the second data-signal DS2 as the 4th data-signal DS4, and with the 4th data-signal DS4 as the 6th signal data DS6.As mentioned above, enable signal ES is in order to which the frequency reading of data of decision since the first prearranged signals PS1, in this example, since the 5th frequency T5 reading of data.Utilize the second prearranged signals PS2 that the 6th data-signal DS6 is sampled to form the 5th data-signal DS5 then, then output.
When data are correct, when not needing to change the time point of reading of data, enable signal ES just selects the 5th data-signal DS5 as the 6th data-signal DS6, makes it form a circulation and constantly output.And when the data that read wrong, during time point that must the change reading of data, enable signal ES just select the 4th data-signal DS4 as the 6th data-signal DS6 with output.Generally speaking, when data-signal DS1 is delayed 180 ° of second prearranged signals PS2 with interior phase place and is read, all can adopt this manner of execution.But viewable design or system requirements, and the second prearranged signals PS2 that makes data-signal DS1 be delayed a predetermined value all can adopt this manner of execution when reading.
Figure 6 shows that when the second prearranged signals PS2 that data-signal DS1 is delayed 270 ° of phase places reads the manner of execution of data reading circuit 200.In this figure, the first prearranged signals PS1 postpones 270 ° of phase places than the second tentation data PS2.As shown in Figure 6, data-signal DS1 is formed the second data-signal DS2 by first prearranged signals PS1 sampling back, and then utilizes the negative edge of the second prearranged signals PS2 to sample and form the 3rd data-signal DS3.And in this example, utilize and select signal SS to select the 3rd data-signal DS3 as the 4th data-signal DS4.Adopt the reason of this action to be, because data-signal has been delayed 270 °, therefore the distance of the current data section that postponed and next data segments is too short, if directly use the sampled targets of the second data-signal DS2 as the second prearranged signals PS2 of the 3rd data buffer 209, then sample wrong data segments easily, therefore must so can avoid this type of problem with the negative edge of second prearranged signals PS2 once sampling again.
In addition, as mentioned above, enable signal ES is in order to which the frequency reading of data of decision since the second prearranged signals PS2, in this example, since the 5th frequency T5 reading of data.Utilize the second prearranged signals PS2 that the 6th data-signal DS6 is sampled to form the 5th data-signal DS5 then, then output.When data are correct, when not needing to change the time point of reading of data, enable signal ES just selects the 5th data-signal DS5 as the 6th data-signal DS6, makes it form a circulation and constantly output.And wrong when the data that read, in the time of must changing the time point of reading of data, enable signal ES just selects the 4th data-signal DS4 as the 6th data-signal DS6, and forms the 6th data-signal DS6 with output.Generally speaking, when data-signal DS1 is delayed that the second prearranged signals PS2 of phase place reads more than 180 °, all can adopt this manner of execution.
It is noted that, though sample with the positive edge of the first prearranged signals PS1 in the foregoing description, and revise with the negative edge of the second prearranged signals PS2, do not represent to limit the present invention.For example, negative edge that can the first prearranged signals PS1 is sampled, and revises with the positive edge of the second prearranged signals PS2, and it also within the scope of the present invention.
Fig. 7 illustrates the operating concept of the system that utilizes data reading circuit provided by the present invention.As shown in Figure 7, be introduced into step 701, set time for reading.Step 703 is from memory read data.Step 705, comparing data.Step 707, whether judgment data is correct, is spendable if then enter this time for reading of step 709 record, then enters step 711 if not and adjusts time for reading.
Fig. 8 illustrates the process flow diagram according to the method for reading data of preferred embodiment of the present invention.As shown in Figure 8, the method comprises: step 801, and use one first prearranged signals that one first data-signal is sampled to form one second data-signal.Step 803 uses the negative edge of one second prearranged signals that second data-signal is sampled to form the 3rd data-signal.Step 805, whether the phase differential of judging this first prearranged signals and this second prearranged signals is greater than a predetermined value, if then enter step 807 with the 3rd data-signal as the 4th data-signal, then enter if not step 809 with the 3rd data-signal as the 4th data-signal.Step 811 uses second prearranged signals that the 4th data-signal is sampled to obtain the correct data signal.
Know this skill person when other minutia that can learn the method by the description of foregoing circuit, so do not repeat them here.
According to above-mentioned circuit, can omit synchronizing circuit, and under the situation of any delay or operating frequency, read correct data, if use on FPGA (Field-Programmable Gate Array field programmable gate array) or ASIC, can use and same set ofly read circuit and increase the integrality of circuit, this shows that this case is not less than being a kind of invention of novelty.
The above only is preferred embodiment of the present invention, and all equivalences of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. data reading circuit comprises:
One first buffer is in order to receive one first data-signal and according to first edge of one first prearranged signals this first data-signal to be sampled to produce one second data-signal;
One second buffer is coupled to this first buffer, in order to second edge according to one second prearranged signals this second data-signal is sampled to produce one the 3rd data-signal;
One first selector is coupled to this second buffer, in order to select one of them output of this second data-signal and the 3rd data-signal to form one the 4th data-signal according to the phase place of this first, second prearranged signals;
One second selector is coupled to this first selector, in order to select one of them output of the 4th data-signal and one the 5th data-signal to form one the 6th data-signal according to an enable signal; And
One the 3rd buffer is coupled to this second selector, in order to first edge according to this second prearranged signals the 6th data-signal is sampled to form the 5th data-signal.
2. data reading circuit as claimed in claim 1, it includes in addition:
One postpones frequency signal produces circuit, is used for N frequency-doubled signal with this second prearranged signals to postpone a particular phases and produce this first prearranged signals, and wherein N is more than or equal to 2.
3. data reading circuit as claimed in claim 2, it is used in a storer, and this second prearranged signals is the data read frequency signal that reads the data of this storer.
4. data reading circuit as claimed in claim 1, it includes in addition:
One enable signal generator is used for postponing one with reference to selecting signal producing a plurality of candidate's enable signals, and one of these a plurality of candidate's enable signals of output are used as this enable signal.
5. data reading circuit as claimed in claim 4, it is used in a storer, and this second prearranged signals is the data read frequency signal that reads the data of this storer.
6. data reading circuit as claimed in claim 1, wherein first edge is that the positive edge and second edge are negative edge.
7. data reading circuit as claimed in claim 6, the phase place of this second prearranged signals of the phase lag of this first prearranged signals wherein, when the phase differential of this first, second prearranged signals during less than a predetermined value, this selection signal selects this second data-signal to be used as the 4th data-signal, and when the phase differential of this first, second prearranged signals was not less than this predetermined value, this selection signal selected the 3rd data-signal to be used as the 4th data-signal.
8. a method for reading data comprises
Receive one first data-signal;
Use first edge of one first prearranged signals that this first data-signal is sampled to form one second data-signal;
Use second edge of one second prearranged signals that this second data-signal is sampled to form one the 3rd data-signal;
Whether the phase differential of judging this first prearranged signals and this second prearranged signals greater than a predetermined value, if then with this second data-signal as one the 4th data-signal, if not then with the 3rd data-signal as the 4th data-signal; And
Sample to obtain the correct data signal to the 4th data-signal in first edge with this second prearranged signals.
9. method for reading data as claimed in claim 8, wherein first edge is that the positive edge and second edge are negative edge.
10. method for reading data as claimed in claim 9, the phase place of this second prearranged signals of the phase lag of this first prearranged signals wherein, when the phase differential of this first, second prearranged signals during less than a predetermined value, this selection signal selects this second data-signal to be used as the 4th data-signal, and when the phase differential of this first, second prearranged signals was not less than this predetermined value, this selection signal selected the 3rd data-signal to be used as the 4th data-signal.
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| US5467464A (en) * | 1993-03-09 | 1995-11-14 | Apple Computer, Inc. | Adaptive clock skew and duty cycle compensation for a serial data bus |
| US5864706A (en) * | 1995-08-15 | 1999-01-26 | Sony Corporation | Digital signal processing apparatus and information processing system |
| CN1635578A (en) * | 2003-12-30 | 2005-07-06 | 瑞昱半导体股份有限公司 | Storage device reading phase automatic correction method and correlated mechanism |
| CN1858856A (en) * | 2005-05-02 | 2006-11-08 | 联发科技股份有限公司 | Signal processing circuits and methods, and memory systems |
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2008
- 2008-03-07 CN CN2008100831476A patent/CN101527164B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5467464A (en) * | 1993-03-09 | 1995-11-14 | Apple Computer, Inc. | Adaptive clock skew and duty cycle compensation for a serial data bus |
| US5864706A (en) * | 1995-08-15 | 1999-01-26 | Sony Corporation | Digital signal processing apparatus and information processing system |
| CN1635578A (en) * | 2003-12-30 | 2005-07-06 | 瑞昱半导体股份有限公司 | Storage device reading phase automatic correction method and correlated mechanism |
| CN1858856A (en) * | 2005-05-02 | 2006-11-08 | 联发科技股份有限公司 | Signal processing circuits and methods, and memory systems |
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