CN101521224B - Double trigger silicon controlled rectifier - Google Patents
Double trigger silicon controlled rectifier Download PDFInfo
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- CN101521224B CN101521224B CN2008100827146A CN200810082714A CN101521224B CN 101521224 B CN101521224 B CN 101521224B CN 2008100827146 A CN2008100827146 A CN 2008100827146A CN 200810082714 A CN200810082714 A CN 200810082714A CN 101521224 B CN101521224 B CN 101521224B
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Abstract
The invention provides a double trigger silicon controlled rectifier which comprises a semiconductor substrate, a N well, a P well, a first N+ diffusion zone, a first P+ diffusion zone, a second N+ diffusion zone, a second P+ diffusion zone, a third P+ diffusion zone which is arranged on one side of the double trigger silicon controlled rectifier across the N well and the P well, a third N+ diffusion zone which is arranged on the other side of the double trigger silicon controlled rectifier across the N well and the P well, a first grid which is arranged above the surface of the N well betweenthe second P+ diffusion zone and the third P+ diffusion zone, and used as a P-type trigger point for receiving a first triggered current or a first triggered voltage, and a second grid which is arran ged above the surface of the P well between the first N+ diffusion zone and the third N+ diffusion zone, and used as a N-type trigger point for receiving a second triggered current or a second triggered voltage. The double trigger silicon controlled rectifier can bear high voltage level, and switch more quickly to conduct circuit or not.
Description
Technical field
The present invention relates to a kind of double trigger silicon controlled rectifier (dual triggered siliconcontrolled rectifier, DTSCR), especially a kind of double trigger silicon controlled rectifier that can be applied in the electric fuse trimming circuit (trim-fuse circuit).
Background technology
With reference to Fig. 1, shown in Figure 1 is that tradition is used the electric fuse trimming circuit 100 of large scale metal-oxide semiconductor (MOS) (MOS) transistor as switch element, as shown in Figure 1, electric fuse trimming circuit 100 comprises mos transistor switch element 110 and electric fuse 120, wherein, whether mos transistor switch element 110 is to be used to receive control signal Sc control to allow and adjust electric current by mos transistor switch element 110.Yet, if electric fuse trimming circuit 100 is used in the low-voltage technology, then can suffer from the problem that to bear the accurate position of high voltage, this is because electric fuse trimming circuit 100 needs the voltage of the accurate position of high voltage that enough big adjustment electric current is provided usually, but the low voltage devices element can't bear the cause of the accurate position of high voltage again.
Summary of the invention
Thus, one of purpose of the present invention is to provide a kind of double trigger silicon controlled rectifier that can be applied in the electric fuse trimming circuit, to solve the above problems.
According to scope of the present invention, it has disclosed a kind of double trigger silicon controlled rectifier, and it comprises: Semiconductor substrate; The wellblock is arranged in this Semiconductor substrate; The one a N+ diffusion zone and a P+ diffusion zone are arranged in this Semiconductor substrate, are used for first electrode as the horizontal silicon controlled rectifier of this pair flip-over type; The 2nd N+ diffusion zone and the 2nd P+ diffusion zone are arranged in this wellblock, are used for second electrode as the horizontal silicon controlled rectifier of this pair flip-over type; The 3rd P+ diffusion zone, be arranged on the horizontal silicon controlled rectifier of this pair flip-over type a side and across the part this wellblock and this Semiconductor substrate between; The 3rd N+ diffusion zone, be arranged on the horizontal silicon controlled rectifier of this pair flip-over type opposite side and across the part this wellblock and this Semiconductor substrate between; First grid, be arranged on the surface of this wellblock between the 2nd P+ diffusion zone and the 3rd P+ diffusion zone, be used for P type trigger point (trigger node), to receive first trigger current or first trigger voltage as the horizontal silicon controlled rectifier of this pair flip-over type; And second grid, be arranged on the surface of this Semiconductor substrate between a N+ diffusion zone and the 3rd N+ diffusion zone, be used for N type trigger point, to receive second trigger current or second trigger voltage as the horizontal silicon controlled rectifier of this pair flip-over type.
According to scope of the present invention, it has disclosed a kind of double trigger silicon controlled rectifier again, and it comprises: Semiconductor substrate; The wellblock is arranged in this Semiconductor substrate; The one a N+ diffusion zone and a P+ diffusion zone are arranged in this Semiconductor substrate, are used for first electrode as the horizontal silicon controlled rectifier of this pair flip-over type; The 2nd N+ diffusion zone and the 2nd P+ diffusion zone are arranged in this wellblock, are used for second electrode as the horizontal silicon controlled rectifier of this pair flip-over type; The 3rd P+ diffusion zone, be arranged on the horizontal silicon controlled rectifier of this pair flip-over type a side and across the part this wellblock and this Semiconductor substrate between; The 3rd N+ diffusion zone, be arranged on the horizontal silicon controlled rectifier of this pair flip-over type opposite side and across the part this wellblock and this Semiconductor substrate between; First grid, be arranged on the surface of this Semiconductor substrate between a P+ diffusion zone and the 3rd P+ diffusion zone, be used for P type trigger point (trigger node), to receive first trigger current or first trigger voltage as the horizontal silicon controlled rectifier of this pair flip-over type; And second grid, be arranged on the surface of this wellblock between the 2nd N+ diffusion zone and the 3rd N+ diffusion zone, be used for N type trigger point, to receive second trigger current or second trigger voltage as the horizontal silicon controlled rectifier of this pair flip-over type.
According to scope of the present invention, it has also disclosed a kind of double trigger silicon controlled rectifier, and it comprises: Semiconductor substrate; N well (N-well) is arranged in this Semiconductor substrate; P well (P-well) is arranged in this Semiconductor substrate and adjacent to this N well; The one a N+ diffusion zone and a P+ diffusion zone are arranged in this P well, are used for the negative electrode as the horizontal silicon controlled rectifier of this pair flip-over type; The 2nd N+ diffusion zone and the 2nd P+ diffusion zone are arranged in this N well, are used for the anode as the horizontal silicon controlled rectifier of this pair flip-over type; The 3rd P+ diffusion zone, be arranged on the horizontal silicon controlled rectifier of this pair flip-over type a side and across the part this N well and this P well between; The 3rd N+ diffusion zone, be arranged on the horizontal silicon controlled rectifier of this pair flip-over type opposite side and across the part this N well and this P well between; First grid is arranged on the surface of this N well between the 2nd P+ diffusion zone and the 3rd P+ diffusion zone, is used for the P type trigger point as the horizontal silicon controlled rectifier of this pair flip-over type, to receive first trigger current or first trigger voltage; And second grid, be arranged on the surface of this P well between a N+ diffusion zone and the 3rd N+ diffusion zone, be used for N type trigger point, to receive second trigger current or second trigger voltage as the horizontal silicon controlled rectifier of this pair flip-over type.
Description of drawings
Illustrated in fig. 1 is that tradition is used the electric fuse trimming circuit of large scale metal-oxide semiconductor (MOS) (MOS) transistor as switch element.
Illustrated in fig. 2 is 3 D stereo schematic diagram according to the double trigger silicon controlled rectifier of the first embodiment of the present invention.
Illustrated in fig. 3 is the 3 D stereo schematic diagram of double trigger silicon controlled rectifier according to a second embodiment of the present invention.
Illustrated in fig. 4 is the 3 D stereo schematic diagram of the double trigger silicon controlled rectifier of a third embodiment in accordance with the invention.
Illustrated in fig. 5 is the 3 D stereo schematic diagram of the double trigger silicon controlled rectifier of a fourth embodiment in accordance with the invention.
Illustrated in fig. 6 is the 3 D stereo schematic diagram of double trigger silicon controlled rectifier according to a fifth embodiment of the invention.
Illustrated in fig. 7 is the 3 D stereo schematic diagram of double trigger silicon controlled rectifier according to a sixth embodiment of the invention.
The electric fuse trimming circuit that is to use the disclosed double trigger silicon controlled rectifier of the present invention as switch element illustrated in fig. 8.
Embodiment
In this specification and follow-up claim scope, used some vocabulary to censure specific element, and one skilled in the art are to be understood that, hardware manufacturer may be called same element with different nouns, this specification and follow-up claim scope are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function, mentioned in specification and the follow-up claim item in the whole text " comprise ' ' be open term; so should be construed to " including but not limited to "; in addition; " coupling " speech comprises any direct and indirect means that are electrically connected at this; therefore; be coupled to second device if describe first device in the literary composition, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other device or connection means.
The present invention relates to a kind of double trigger silicon controlled rectifier, and this specification will illustrate about using the embodiment of double trigger silicon controlled rectifier of the present invention in electric fuse trimming circuit, but the correlative technology field those of ordinary skill should be able to recognize the present invention and can be applied in other various types of circuit structures, and the specific embodiment that is not limited in the following description to be provided.
With reference to Fig. 2, illustrated in fig. 2 is 3 D stereo schematic diagram according to the double trigger silicon controlled rectifier 200 of the first embodiment of the present invention.As shown in Figure 2, double trigger silicon controlled rectifier 200 comprises: P type semiconductor substrate 202; N well (N-well) 204 is arranged in the P type semiconductor substrate 202; The one a N+ diffusion zone 206 and a P+ diffusion zone 208 are arranged in the P type semiconductor substrate 202, are used for the negative electrode as double trigger silicon controlled rectifier 200; The 2nd N+ diffusion zone 210 and the 2nd P+ diffusion zone 212 are arranged in the N well 204, are used for the anode as double trigger silicon controlled rectifier 200; The 3rd P+ diffusion zone 214, be arranged on double trigger silicon controlled rectifier 200 a side and across the part N well 204 and P type semiconductor substrate 202 between; The 3rd N+ diffusion zone 216, be arranged on double trigger silicon controlled rectifier 200 opposite side and across the part N well 204 and P type semiconductor substrate 202 between; First grid 218 is arranged on the surface of the N well 204 between the 2nd P+ diffusion zone and the 3rd P+ diffusion zone, is used for the P type trigger point as double trigger silicon controlled rectifier 200, to receive first trigger current or first trigger voltage; And second grid 220, be arranged on the surface of the P type semiconductor substrate 202 between a N+ diffusion zone and the 3rd N+ diffusion zone, be used for N type trigger point, to receive second trigger current or second trigger voltage as double trigger silicon controlled rectifier 200.
With reference to Fig. 3, illustrated in fig. 3 is the 3 D stereo schematic diagram of double trigger silicon controlled rectifier 300 according to a second embodiment of the present invention.As shown in Figure 3, double trigger silicon controlled rectifier 300 comprises: P type semiconductor substrate 302; N well 304 is arranged in the P type semiconductor substrate 302; The one N+ diffusion zone 306, a P+ diffusion zone 308 and the 4th N+ diffusion zone 322 are arranged in the P type semiconductor substrate 302, are used for the negative electrode as double trigger silicon controlled rectifier 300; The 2nd N+ diffusion zone 310, the 2nd P+ diffusion zone 312 and the 4th P+ diffusion zone 324 are arranged in the N well 304, are used for the anode as double trigger silicon controlled rectifier 300; The 3rd P+ diffusion zone 314, be arranged on double trigger silicon controlled rectifier 300 a side and across the part N well 304 and P type semiconductor substrate 302 between; The 3rd N+ diffusion zone 316, be arranged on double trigger silicon controlled rectifier 300 opposite side and across the part N well 304 and P type semiconductor substrate 302 between; First grid 318 is arranged on the surface of the N well 304 between the 2nd P+ diffusion zone 312 and the 3rd P+ diffusion zone 314, is used for the P type trigger point as double trigger silicon controlled rectifier 300, to receive first trigger current or first trigger voltage; And second grid 320, be arranged on the surface of the P type semiconductor substrate 302 between a N+ diffusion zone 306 and the 3rd N+ diffusion zone 316, be used for N type trigger point, to receive second trigger current or second trigger voltage as double trigger silicon controlled rectifier 300.
With reference to Fig. 4, illustrated in fig. 4 is the 3 D stereo schematic diagram of the double trigger silicon controlled rectifier 400 of a third embodiment in accordance with the invention.As shown in Figure 4, double trigger silicon controlled rectifier 400 comprises: N type semiconductor substrate 402; P well 404 is arranged in the N type semiconductor substrate 402; The one a N+ diffusion zone 406 and a P+ diffusion zone 408 are arranged in the N type semiconductor substrate 402, are used for the anode as double trigger silicon controlled rectifier 400; The 2nd N+ diffusion zone 410 and the 2nd P+ diffusion zone 412 are arranged in the P well 404, are used for the negative electrode as double trigger silicon controlled rectifier 400; The 3rd P+ diffusion zone 414, be arranged on double trigger silicon controlled rectifier 400 a side and across the part P well 404 and N type semiconductor substrate 402 between; The 3rd N+ diffusion zone 416, be arranged on double trigger silicon controlled rectifier 400 opposite side and across the part P well 404 and N type semiconductor substrate 402 between; First grid 418, be arranged on the surface of the N type semiconductor substrate 402 between a P+ diffusion zone 408 and the 3rd P+ diffusion zone 414, be used for P type trigger point, to receive first trigger current or first trigger voltage as double trigger silicon controlled rectifier 400; And second grid 420, be arranged on the surface of the P well 404 between the 2nd N+ diffusion zone 410 and the 3rd N+ diffusion zone 416, be used for N type trigger point, to receive second trigger current or second trigger voltage as double trigger silicon controlled rectifier 400.
With reference to Fig. 5, illustrated in fig. 5 is the 3 D stereo schematic diagram of the double trigger silicon controlled rectifier 500 of a fourth embodiment in accordance with the invention.As shown in Figure 5, double trigger silicon controlled rectifier 500 comprises: N type semiconductor substrate 502; P well 504 is arranged in the N type semiconductor substrate 502; The one N+ diffusion zone 506, a P+ diffusion zone 508 and the 4th P+ diffusion zone 522 are arranged in the N type semiconductor substrate 502, are used for the anode as double trigger silicon controlled rectifier 500; The 2nd N+ diffusion zone 510, the 2nd P+ diffusion zone 512 and the 4th N+ diffusion zone 524 are arranged in the P well 504, are used for the negative electrode as double trigger silicon controlled rectifier 500; The 3rd P+ diffusion zone 514, be arranged on double trigger silicon controlled rectifier 500 a side and across the part P well 504 and N type semiconductor substrate 502 between; The 3rd N+ diffusion zone 516, be arranged on double trigger silicon controlled rectifier 500 opposite side and across the part P well 504 and N type semiconductor substrate 502 between; First grid 518, be arranged on the surface of the N type semiconductor substrate 502 between a P+ diffusion zone 508 and the 3rd P+ diffusion zone 514, be used for P type trigger point, to receive first trigger current or first trigger voltage as double trigger silicon controlled rectifier 500; And second grid 520, be arranged on the surface of the P well 504 between the 2nd N+ diffusion zone 510 and the 3rd N+ diffusion zone 516, be used for N type trigger point, to receive second trigger current or second trigger voltage as double trigger silicon controlled rectifier 500.
With reference to Fig. 6, illustrated in fig. 6 is the 3 D stereo schematic diagram of double trigger silicon controlled rectifier 600 according to a fifth embodiment of the invention.As shown in Figure 6, double trigger silicon controlled rectifier 600 comprises: P type semiconductor substrate 602; N well 604 is arranged in the P type semiconductor substrate 602; P well 605 is arranged in the P type semiconductor substrate 602 and adjacent to N well 604; The one a N+ diffusion zone 606 and a P+ diffusion zone 608 are arranged in the P well 605, are used for the negative electrode as double trigger silicon controlled rectifier 600; The 2nd N+ diffusion zone 610 and the 2nd P+ diffusion zone 612 are arranged in the N well 604, are used for the anode as double trigger silicon controlled rectifier 600; The 3rd P+ diffusion zone 614, be arranged on double trigger silicon controlled rectifier 600 a side and across the part N well 604 and P well 605 between; The 3rd N+ diffusion zone 616, be arranged on double trigger silicon controlled rectifier 600 opposite side and across the part N well 604 and P well 605 between; First grid 618 is arranged on the surface of the N well 604 between the 2nd P+ diffusion zone 612 and the 3rd P+ diffusion zone 614, is used for the P type trigger point as double trigger silicon controlled rectifier 600, to receive first trigger current or first trigger voltage; And second grid 620, be arranged on the surface of the P well 605 between a N+ diffusion zone 606 and the 3rd N+ diffusion zone 616, be used for N type trigger point, to receive second trigger current or second trigger voltage as double trigger silicon controlled rectifier 600.In addition, in this attention, the above embodiments only illustrate as of the present invention, rather than restrictive condition of the present invention, and for instance, P type semiconductor substrate 602 also can be replaced into the N type semiconductor substrate.
With reference to Fig. 7, illustrated in fig. 7 is the 3 D stereo schematic diagram of double trigger silicon controlled rectifier 700 according to a sixth embodiment of the invention.As shown in Figure 7, double trigger silicon controlled rectifier 700 comprises: P type semiconductor substrate 702; N well 704 is arranged in the P type semiconductor substrate 702; P well 705 is arranged in the P type semiconductor substrate 702 and adjacent to N well 704; The one N+ diffusion zone 706, a P+ diffusion zone 708 and the 4th N+ diffusion zone 722 are arranged in the P well 705, are used for the negative electrode as double trigger silicon controlled rectifier 700; The 2nd N+ diffusion zone 710, the 2nd P+ diffusion zone 712 and the 4th P+ diffusion zone 724 are arranged in the N well 704, are used for the anode as double trigger silicon controlled rectifier 700; The 3rd P+ diffusion zone 714, be arranged on double trigger silicon controlled rectifier 700 a side and across the part N well 704 and P well 705 between; The 3rd N+ diffusion zone 716, be arranged on double trigger silicon controlled rectifier 700 opposite side and across the part N well 704 and P well 705 between; First grid 718 is arranged on the surface of the N well 704 between the 2nd P+ diffusion zone 712 and the 3rd P+ diffusion zone 714, is used for the P type trigger point as double trigger silicon controlled rectifier 700, to receive first trigger current or first trigger voltage; And second grid 720, be arranged on the surface of the P well 705 between a N+ diffusion zone 706 and the 3rd N+ diffusion zone 716, be used for N type trigger point, to receive second trigger current or second trigger voltage as double trigger silicon controlled rectifier 700.In addition, in this attention, the above embodiments only illustrate as of the present invention, rather than restrictive condition of the present invention, and for instance, P type semiconductor substrate 702 also can be replaced into the N type semiconductor substrate.
With reference to Fig. 8, the electric fuse trimming circuit 800 that is to use the disclosed double trigger silicon controlled rectifier of the present invention as switch element illustrated in fig. 8, as shown in Figure 1, electric fuse trimming circuit 800 comprises double trigger silicon controlled rectifier 810 and electric fuse 820, wherein, be formed with PMOS transistor 812 and nmos pass transistor 814 in the double trigger silicon controlled rectifier 810, and PMOS transistor 812 and nmos pass transistor 814 are respectively applied for and receive the first control signal Ctrlb (for example first trigger current or first trigger voltage) and the second control signal Ctrl (for example second trigger current or second trigger voltage) and control double trigger silicon controlled rectifier 810 whether conducting allows and adjust electric current by double trigger silicon controlled rectifier 810, in addition, notice that at this first control signal Ctrlb and the second control signal Ctrl are the accurate position of low-voltage.Because the disclosed double trigger silicon controlled rectifier of all embodiment can bear the accurate position of high voltage in the present invention, so can solve the problems of the prior art, in addition, and the disclosed double trigger silicon controlled rectifier of all embodiment all has splendid current-voltage curve (I-Vcurve) characteristic in the present invention, therefore under the condition that identical triggering electric current or trigger voltage are provided, can carry out the handover operation of whether conducting more quickly.
The above only is the preferred embodiments of the present invention, as long as the claim scope is done according to the present invention equivalent variations and modification all should belong to covering scope of the present invention.
The primary clustering symbol description
100: electric fuse trimming circuit 110:MOS transistor switch element
120: electric fuse 200: double trigger silicon controlled rectifier
202:P type Semiconductor substrate 204:N well
208: the P+ diffusion zones of 206: the N+ diffusion zones
212: the two P+ diffusion zones of 210: the two N+ diffusion zones
216: the three N+ diffusion zones of 214: the three P+ diffusion zones
218: first grid 220: second grid
300: double trigger silicon controlled rectifier 302:P type Semiconductor substrate
306: the one N+ diffusion zones of 304:N well
310: the two N+ diffusion zones of 308: the one P+ diffusion zones
314: the three P+ diffusion zones of 312: the two P+ diffusion zones
316: the three N+ diffusion zones 318: first grid
320: 322: the four N+ diffusion zones of second grid
324: the four P+ diffusion zones 400: double trigger silicon controlled rectifier
402:N N-type semiconductor N substrate 404:P well
408: the one P+ diffusion zones of 406: the one N+ diffusion zones
412: the two P+ diffusion zones of 410: the two N+ diffusion zones
416: the three N+ diffusion zones of 414: the three P+ diffusion zones
418: first grid 420: second grid
500: double trigger silicon controlled rectifier 502:N N-type semiconductor N substrate
506: the one N+ diffusion zones of 504:P well
510: the two N+ diffusion zones of 508: the one P+ diffusion zones
514: the three P+ diffusion zones of 512: the two P+ diffusion zones
516: the three N+ diffusion zones 518: first grid
520: 522: the four P+ diffusion zones of second grid
524: the four N+ diffusion zones 600: double trigger silicon controlled rectifier
602:P N-type semiconductor N substrate 604:N well
606: the one N+ diffusion zones of 605:P well
610: the two N+ diffusion zones of 608: the one P+ diffusion zones
614: the three P+ diffusion zones of 612: the two P+ diffusion zones
616: the three N+ diffusion zones 618: first grid
620: second grid 700: double trigger silicon controlled rectifier
702:P N-type semiconductor N substrate 704:N well
706: the one N+ diffusion zones of 705:P well
710: the two N+ diffusion zones of 708: the one P+ diffusion zones
714: the three P+ diffusion zones of 712: the two P+ diffusion zones
716: the three N+ diffusion zones 718: first grid
720: 722: the four N+ diffusion zones of second grid
724: the four P+ diffusion zones 800: electric fuse trimming circuit
810: double trigger silicon controlled rectifier 812:PMOS transistor
814:NMOS transistor 820: electric fuse
Claims (12)
1. double trigger silicon controlled rectifier comprises:
Semiconductor substrate;
The wellblock is arranged in the described Semiconductor substrate;
The one a N+ diffusion zone and a P+ diffusion zone are arranged in the described Semiconductor substrate, are used for first electrode as described double trigger silicon controlled rectifier;
The 2nd N+ diffusion zone and the 2nd P+ diffusion zone are arranged in the described wellblock, are used for second electrode as described double trigger silicon controlled rectifier;
The 3rd P+ diffusion zone, be arranged on described double trigger silicon controlled rectifier the 2nd P+ diffusion zone a side and across the part described wellblock and described Semiconductor substrate between;
The 3rd N+ diffusion zone, be arranged on described double trigger silicon controlled rectifier a N+ diffusion zone a side and across the part described wellblock and described Semiconductor substrate between;
First grid is arranged on the surface of the described wellblock between described the 2nd P+ diffusion zone and described the 3rd P+ diffusion zone, is used for the P type trigger point as described double trigger silicon controlled rectifier, to receive first trigger current or first trigger voltage; And
Second grid, be arranged on the surface of the described Semiconductor substrate between a described N+ diffusion zone and described the 3rd N+ diffusion zone, be used for N type trigger point, to receive second trigger current or second trigger voltage as described double trigger silicon controlled rectifier.
2. double trigger silicon controlled rectifier according to claim 1, wherein, described Semiconductor substrate is the P type semiconductor substrate, and described wellblock is the N well, and described first electrode is negative electrode, and described second electrode is an anode.
3. double trigger silicon controlled rectifier according to claim 2 also comprises:
The 4th N+ diffusion zone is arranged in the described P type semiconductor substrate, is used for the described negative electrode as described double trigger silicon controlled rectifier; And
The 4th P+ diffusion zone is arranged in the described N well, is used for the described anode as described double trigger silicon controlled rectifier.
4. double trigger silicon controlled rectifier according to claim 1, it is applied in the electric fuse trimming circuit.
5. double trigger silicon controlled rectifier comprises:
Semiconductor substrate;
The wellblock is arranged in the described Semiconductor substrate;
The one a N+ diffusion zone and a P+ diffusion zone are arranged in the described Semiconductor substrate, are used for first electrode as described double trigger silicon controlled rectifier;
The 2nd N+ diffusion zone and the 2nd P+ diffusion zone are arranged in the described wellblock, are used for second electrode as described double trigger silicon controlled rectifier;
The 3rd P+ diffusion zone, be arranged on described double trigger silicon controlled rectifier the 2nd P+ diffusion zone a side and across the part described wellblock and described Semiconductor substrate between;
The 3rd N+ diffusion zone, be arranged on described double trigger silicon controlled rectifier a N+ diffusion zone a side and across the part described wellblock and
Between the described Semiconductor substrate;
First grid, be arranged on the surface of the described Semiconductor substrate between a described P+ diffusion zone and described the 3rd P+ diffusion zone, be used for P type trigger point, to receive first trigger current or first trigger voltage as described double trigger silicon controlled rectifier; And
Second grid is arranged on the surface of the described wellblock between described the 2nd N+ diffusion zone and described the 3rd N+ diffusion zone, is used for the N type trigger point as described double trigger silicon controlled rectifier, to receive second trigger current or second trigger voltage.
6. double trigger silicon controlled rectifier according to claim 5, wherein, described Semiconductor substrate is the N type semiconductor substrate, and described wellblock is the P well, and described first electrode is anode, and described second electrode is a negative electrode.
7. double trigger silicon controlled rectifier according to claim 6 also comprises:
The 4th P+ diffusion zone is arranged in the described N type semiconductor substrate, is used for the described anode as described double trigger silicon controlled rectifier; And
The 4th N+ diffusion zone is arranged in the described P well, is used for the described negative electrode as described double trigger silicon controlled rectifier.
8. double trigger silicon controlled rectifier according to claim 5, it is applied in the electric fuse trimming circuit.
9. double trigger silicon controlled rectifier comprises:
Semiconductor substrate;
The N well is arranged in the described Semiconductor substrate;
The P well is arranged in the described Semiconductor substrate and adjacent to described N well;
The one a N+ diffusion zone and a P+ diffusion zone are arranged in the described P well, are used for the negative electrode as described double trigger silicon controlled rectifier;
The 2nd N+ diffusion zone and the 2nd P+ diffusion zone are arranged in the described N well, are used for the anode as described double trigger silicon controlled rectifier;
The 3rd P+ diffusion zone, be arranged on described double trigger silicon controlled rectifier a side and across the part described N well and described P well between;
The 3rd N+ diffusion zone, be arranged on described double trigger silicon controlled rectifier opposite side and across the part described N well and described P well between;
First grid is arranged on the surface of the described N well between described the 2nd P+ diffusion zone and described the 3rd P+ diffusion zone, is used for the P type trigger point as described double trigger silicon controlled rectifier, to receive first trigger current or first trigger voltage; And
Second grid is arranged on the surface of the described P well between a described N+ diffusion zone and described the 3rd N+ diffusion zone, is used for the N type trigger point as described double trigger silicon controlled rectifier, to receive second trigger current or second trigger voltage.
10. double trigger silicon controlled rectifier according to claim 9 also comprises:
The 4th N+ diffusion zone is arranged in the described P well, is used for the described negative electrode as described double trigger silicon controlled rectifier; And
The 4th P+ diffusion zone is arranged in the described N well, is used for the described anode as described double trigger silicon controlled rectifier.
11. double trigger silicon controlled rectifier according to claim 9, wherein, described Semiconductor substrate is P type semiconductor substrate or N type semiconductor substrate.
12. double trigger silicon controlled rectifier according to claim 9, it is applied in the electric fuse trimming circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100827146A CN101521224B (en) | 2008-02-27 | 2008-02-27 | Double trigger silicon controlled rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100827146A CN101521224B (en) | 2008-02-27 | 2008-02-27 | Double trigger silicon controlled rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101521224A CN101521224A (en) | 2009-09-02 |
| CN101521224B true CN101521224B (en) | 2010-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100827146A Expired - Fee Related CN101521224B (en) | 2008-02-27 | 2008-02-27 | Double trigger silicon controlled rectifier |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5910664A (en) * | 1996-11-05 | 1999-06-08 | International Rectifier Corporation | Emitter-switched transistor structures |
| US6215135B1 (en) * | 1998-08-04 | 2001-04-10 | U.S. Philips Corporation | Integrated circuit provided with ESD protection means |
| US6246079B1 (en) * | 1998-05-13 | 2001-06-12 | Winbond Electronics Corp. | SCR circuit with a high trigger current |
| US7141831B1 (en) * | 2004-07-28 | 2006-11-28 | National Semiconductor Corporation | Snapback clamp having low triggering voltage for ESD protection |
-
2008
- 2008-02-27 CN CN2008100827146A patent/CN101521224B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5910664A (en) * | 1996-11-05 | 1999-06-08 | International Rectifier Corporation | Emitter-switched transistor structures |
| US6246079B1 (en) * | 1998-05-13 | 2001-06-12 | Winbond Electronics Corp. | SCR circuit with a high trigger current |
| US6215135B1 (en) * | 1998-08-04 | 2001-04-10 | U.S. Philips Corporation | Integrated circuit provided with ESD protection means |
| US7141831B1 (en) * | 2004-07-28 | 2006-11-28 | National Semiconductor Corporation | Snapback clamp having low triggering voltage for ESD protection |
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| Publication number | Publication date |
|---|---|
| CN101521224A (en) | 2009-09-02 |
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