JP2007088550A

JP2007088550A - Semiconductor relay unit

Info

Publication number: JP2007088550A
Application number: JP2005271559A
Authority: JP
Inventors: Kazuhiko Kusuda; 和彦楠田; Masaru Matsuda; 大松田; Takeshi Nobe; 武野辺; Hiroshi Okada; 洋岡田; Yoshihiro Fujiwara; 嘉宏藤原
Original assignee: Matsushita Electric Works Ltd
Current assignee: Panasonic Electric Works Co Ltd
Priority date: 2005-09-20
Filing date: 2005-09-20
Publication date: 2007-04-05

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor relay unit comprising MOSFETs that has characteristics of a low capacitance and a high withstanding voltage and attains two-way connection to a load. <P>SOLUTION: Two sets of output sections 4a, 4b each comprising a high withstanding voltage output MOSFET and a low withstanding voltage output MOSFET in pairs are configured symmetrically with respect to source terminals of the low withstanding voltage output MOSFETs 42, 43 so as to use drains of the high withstanding voltage output MOSFETs 41, 44 for external terminals 45a, 45b. Thus, a high voltage can be applied to the external terminals 45a, 45b in two-ways so as to enhance the security and the convenience, and the series connection of the plural low capacitance low withstanding voltage output MOSFETs 42, 43 can reduce the capacitance between the external terminals to be lower and improve the high frequency characteristics. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、入力信号に応答して出力される光信号に基づいて、出力部のＦＥＴをスイッチング動作させる半導体リレー装置に関するものである。 The present invention relates to a semiconductor relay device that switches a FET of an output unit based on an optical signal output in response to an input signal.

従来この種の半導体リレー装置としては、例えば、特許文献１に示されるように、２つのＦＥＴが直列に接続され、各ＦＥＴの開放端を入力端子又は出力端子とし、各ＦＥＴをオン、オフするものがある。図８に、このリレー装置の構成を示す。このリレー装置においては、入力信号により発光するＬＥＤ１０１からの光信号を受光素子のフォトダイオードアレイ１０２で受光して所定電圧を発生し、この所定電圧が、放電回路１０３を介してＭＯＳＦＥＴ１０４、１０５のゲート端子とソース端子間に接続されている。この半導体リレー装置では、入力信号により出力用ＭＯＳＦＥＴ１０４、１０５がスイッチング駆動されて、出力部に接続された負荷電流を開閉している。 Conventionally, as this type of semiconductor relay device, for example, as shown in Patent Document 1, two FETs are connected in series, and the open end of each FET is used as an input terminal or output terminal, and each FET is turned on and off. There is something. FIG. 8 shows the configuration of this relay device. In this relay device, an optical signal from the LED 101 that emits light in response to an input signal is received by the photodiode array 102 of the light receiving element to generate a predetermined voltage, and this predetermined voltage is supplied to the gates of the MOSFETs 104 and 105 via the discharge circuit 103. Connected between terminal and source terminal. In this semiconductor relay device, the output MOSFETs 104 and 105 are switched by an input signal to open and close the load current connected to the output unit.

ところで、出力用ＭＯＳＦＥＴは、通電されない状態のオフ容量が大きい。また、一般に耐圧が大きくなると、ＭＯＳＦＥＴのオフ容量Ｃとオン抵抗Ｒの積（Ｃ×Ｒ）が大きくなる傾向があり、そのため単体のＭＯＳＦＥＴで高耐圧、低容量、低オン抵抗の性能を同時に満たすＭＯＳＦＥＴを得ることは極めて難しい。一方、半導体リレー装置は、高周波負荷及び高電圧負荷に適用するために、低容量性及び高耐圧性が求められる。 By the way, the output MOSFET has a large off-capacitance when it is not energized. In general, when the withstand voltage increases, the product (C × R) of the off-capacitance C and the on-resistance R of the MOSFET tends to increase. Therefore, a single MOSFET simultaneously satisfies the performance of high withstand voltage, low capacity, and low on-resistance. Obtaining a MOSFET is extremely difficult. On the other hand, the semiconductor relay device is required to have low capacity and high withstand voltage in order to be applied to a high frequency load and a high voltage load.

このために、上記特許文献１に示された半導体リレー装置では、低容量、低耐圧のＭＯＳＦＥＴ１０４と高容量、高耐圧のＭＯＳＦＥＴ１０５を直列に接続することにより、合成容量を低減させ、低容量、高耐圧の半導体リレー装置を実現している。 For this reason, in the semiconductor relay device disclosed in Patent Document 1, a low-capacitance, low-voltage MOSFET 104 and a high-capacity, high-voltage MOSFET 105 are connected in series to reduce the combined capacitance, thereby reducing the A breakdown voltage semiconductor relay device is realized.

しかしながら、上記半導体リレー装置においては、低容量、高耐圧の実現は可能であるが、低耐圧のＭＯＳＦＥＴ１０４の外部端子１０６及び高耐圧のＭＯＳＦＥＴ１０５の外部端子１０７と外部負荷とを接続する際に、外部端子１０６が負荷の高電位側に接続されると、高電圧が低耐圧のＭＯＳＦＥＴ１０４に印加され、低耐圧のＭＯＳＦＥＴ１０４が耐圧破壊される虞があった。この低耐圧のＭＯＳＦＥＴ１０４の耐圧破壊を避けるため、高耐圧のＭＯＳＦＥＴ１０５の外部端子１０７を負荷の高電位側に接続し、低耐圧のＭＯＳＦＥＴ１０４の外部端子１０６を負荷の低電位側に接続する必要があった。 However, in the above-described semiconductor relay device, it is possible to realize a low capacity and a high breakdown voltage. However, when the external terminal 106 of the low breakdown voltage MOSFET 104 and the external terminal 107 of the high breakdown voltage MOSFET 105 are connected to an external load, an external load is provided. When the terminal 106 is connected to the high potential side of the load, a high voltage is applied to the low breakdown voltage MOSFET 104, and the low breakdown voltage MOSFET 104 may be broken down. In order to avoid breakdown of the low breakdown voltage MOSFET 104, it is necessary to connect the external terminal 107 of the high breakdown voltage MOSFET 105 to the high potential side of the load and connect the external terminal 106 of the low breakdown voltage MOSFET 104 to the low potential side of the load. It was.

従って、上記半導体リレー装置においては、低容量の半導体リレー装置を形成することはできるが、外部端子１０６、１０７に双方向より高電圧を印加することができなかった。このため、半導体リレー装置の利用において、安全性及びユーザの利便性を欠くという問題があった。 Accordingly, in the semiconductor relay device, a low-capacity semiconductor relay device can be formed, but a high voltage cannot be applied to the external terminals 106 and 107 in both directions. For this reason, there is a problem that safety and user convenience are lacking in the use of the semiconductor relay device.

また、他の従来例として、特許文献２に示されるように、高耐圧用ＭＯＳＦＥＴと低耐圧用出力ＭＯＳＦＥＴとを直列に接続し、低耐圧用出力ＭＯＳＦＥＴに微小電流バイパス回路を設け、高耐圧化、低容量化を図った半導体リレー装置が提案されている。しかし、この従来例においても、負荷に接続する２つの外部端子が高耐圧用ＭＯＳＦＥＴ側と低耐圧用出力ＭＯＳＦＥＴ側に存在するため、前記と同様に、外部端子の双方向より高電位を印加できないという問題があった。
特開平８−２９８４４６号公報特開２００４−２８９４１０号公報 As another conventional example, as shown in Patent Document 2, a high breakdown voltage MOSFET and a low breakdown voltage output MOSFET are connected in series, and a low current breakdown output MOSFET is provided with a minute current bypass circuit to increase the breakdown voltage. A semiconductor relay device with a reduced capacity has been proposed. However, also in this conventional example, since two external terminals connected to the load exist on the high withstand voltage MOSFET side and the low withstand voltage output MOSFET side, a high potential cannot be applied in both directions of the external terminals as described above. There was a problem.
JP-A-8-298446 JP 2004-289410 A

本発明は、上記の問題を解決するためになされたものであり、高耐圧用出力ＭＯＳＦＥＴと低耐圧用出力ＭＯＳＦＥＴの２組の出力部を、各低耐圧用出力ＭＯＳＦＥＴのソース端子を共通にして直列接続し、各高耐圧用出力ＭＯＳＦＥＴの各ドレインを外部端子とすることにより、外部端子の双方向より高電圧を印加可能とし、しかも、複数の低容量の低耐圧用出力ＭＯＳＦＥＴの直列接続による外部端子間の低容量化を図り高周波特性の向上を図った半導体リレー装置を提供することを目的とする。 The present invention has been made in order to solve the above-described problem, and two sets of output portions of a high-breakdown-voltage output MOSFET and a low-breakdown-voltage output MOSFET are shared by the source terminals of the low-breakdown-voltage output MOSFETs. By connecting in series and each drain of each high breakdown voltage output MOSFET as an external terminal, a high voltage can be applied in both directions of the external terminal, and by connecting multiple low capacity low breakdown voltage output MOSFETs in series. An object of the present invention is to provide a semiconductor relay device in which the capacity between external terminals is reduced and the high frequency characteristics are improved.

上記目的を達成するために請求項１の発明は、入力信号に応答して光信号を出力する発光素子を設けた入力部と、前記光信号を受光して所定電圧を発生する受光部と、この所定電圧により出力用ＭＯＳＦＥＴをスイッチング制御する電圧制御部と、各出力ソースを共通に互いに直列に接続された一対の出力用ＭＯＳＦＥＴを有する出力部とを備え、前記入力信号に応答して前記出力部を開閉する半導体リレー装置において、前記受光部、前記電圧制御部及び前記出力部を少なくともそれぞれ各２組備え、前記電圧制御部は、充放電制御回路で形成され、該充放電制御回路の高電位側と低電位側には、前記各出力用ＭＯＳＦＥＴのゲートとソースがそれぞれ接続されると共に、前記一対の出力用ＭＯＳＦＥＴは、それぞれ高耐圧用出力ＭＯＳＦＥＴと低耐圧用出力ＭＯＳＦＥＴで構成され、前記各低耐圧用出力ＭＯＳＦＥＴのドレイン間を接続することにより前記２組の出力部を直列接続し、前記各高耐圧用出力ＭＯＳＦＥＴのドレイン端子を外部端子としたものである。 In order to achieve the above object, the invention of claim 1 includes an input unit provided with a light emitting element that outputs an optical signal in response to an input signal, a light receiving unit that receives the optical signal and generates a predetermined voltage, A voltage control unit that performs switching control of the output MOSFET with the predetermined voltage; and an output unit that includes a pair of output MOSFETs in which each output source is connected in series to each other, and outputs the output in response to the input signal. In the semiconductor relay device that opens and closes the unit, each of the light receiving unit, the voltage control unit, and the output unit includes at least two sets, and the voltage control unit is formed by a charge / discharge control circuit, The gate and the source of each output MOSFET are connected to the potential side and the low potential side, respectively, and the pair of output MOSFETs are connected to the high breakdown voltage output MOSF, respectively. T and a low breakdown voltage output MOSFET, and the two output units are connected in series by connecting the drains of the low breakdown voltage output MOSFETs. The drain terminals of the high breakdown voltage output MOSFETs are external terminals. It is what.

請求項２の発明は、請求項１に記載の半導体リレー装置において、前記入力信号のオフ時に、前記低耐圧用出力ＭＯＳＦＥＴの動作応答時間を遅く、前記高耐圧用出力ＭＯＳＦＥＴの動作応答時間を速くすることにより、前記低耐圧用出力ＭＯＳＦＥＴの立ち下がり速度を高耐圧用出力ＭＯＳＦＥＴの立ち下がり速度より遅くしたものである。 According to a second aspect of the present invention, in the semiconductor relay device according to the first aspect, when the input signal is turned off, the operation response time of the low withstand voltage output MOSFET is delayed, and the operation response time of the high withstand voltage output MOSFET is increased. Thus, the falling speed of the low withstand voltage output MOSFET is made slower than the falling speed of the high withstand voltage output MOSFET.

請求項３の発明は、請求項１に記載の半導体リレー装置において、前記入力信号のオン時に、前記低耐圧用出力ＭＯＳＦＥＴの動作応答時間を速く、前記高耐圧用出力ＭＯＳＦＥＴの動作応答時間を遅くすることにより、前記低耐圧用出力ＭＯＳＦＥＴの立ち上がり速度を高耐圧用出力ＭＯＳＦＥＴの立ち上がり速度より速くしたものである。 According to a third aspect of the present invention, in the semiconductor relay device according to the first aspect, when the input signal is turned on, the operation response time of the low withstand voltage output MOSFET is shortened, and the operation response time of the high withstand voltage output MOSFET is delayed. Thus, the rising speed of the low withstand voltage output MOSFET is made faster than the rising speed of the high withstand voltage output MOSFET.

請求項４の発明は、請求項１に記載の半導体リレー装置において、前記入力信号のオフ時に、前記低耐圧用出力ＭＯＳＦＥＴの動作応答時間を遅く、前記高耐圧用出力ＭＯＳＦＥＴの動作応答時間を速くすることにより、前記低耐圧用出力ＭＯＳＦＥＴの立ち下がり速度を高耐圧用出力ＭＯＳＦＥＴの立ち下がり速度より遅くすると共に、前記入力信号のオン時に、前記低耐圧用出力ＭＯＳＦＥＴの動作応答時間を速く、前記高耐圧用出力ＭＯＳＦＥＴの動作応答時間を遅くすることにより、前記低耐圧用出力ＭＯＳＦＥＴの立ち上がり速度を高耐圧用出力ＭＯＳＦＥＴの立ち上がり速度より速くしたものである。 According to a fourth aspect of the present invention, in the semiconductor relay device according to the first aspect, when the input signal is turned off, the operation response time of the low withstand voltage output MOSFET is delayed and the operation response time of the high withstand voltage output MOSFET is increased. By making the falling speed of the low breakdown voltage output MOSFET slower than the falling speed of the high breakdown voltage output MOSFET, the operation response time of the low breakdown voltage output MOSFET is increased when the input signal is turned on, By delaying the operation response time of the high breakdown voltage output MOSFET, the rising speed of the low breakdown voltage output MOSFET is made faster than the rising speed of the high breakdown voltage output MOSFET.

請求項５の発明は、請求項２に記載の半導体リレー装置において、前記各高耐圧用出力ＭＯＳＦＥＴのゲートと前記各充放電制御回路の高電圧側との間にダイオードと抵抗がそれぞれ並列に接続され、該ダイオードのアノードは前記各高耐圧用出力ＭＯＳＦＥＴのゲートに接続されているものである。 According to a fifth aspect of the present invention, in the semiconductor relay device according to the second aspect, a diode and a resistor are connected in parallel between the gate of each high withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit. The anode of the diode is connected to the gate of each high withstand voltage output MOSFET.

請求項６の発明は、請求項３に記載の半導体リレー装置において、前記各低耐圧用出力ＭＯＳＦＥＴのゲートと前記各充放電制御回路の高電圧側との間にダイオードと抵抗がそれぞれ並列に接続され、前記ダイオードのカソードは前記各低耐圧用出力ＭＯＳＦＥＴのゲートに接続されているものである。 According to a sixth aspect of the present invention, in the semiconductor relay device according to the third aspect, a diode and a resistor are connected in parallel between the gate of each low withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit. The cathode of the diode is connected to the gate of each low withstand voltage output MOSFET.

請求項７の発明は、請求項４に記載の半導体リレー装置において、前記各高耐圧用出力ＭＯＳＦＥＴのゲートと前記各充放電制御回路の高電圧側との間にダイオードと抵抗がそれぞれ並列に接続され、該ダイオードのアノードは前記各高耐圧用出力ＭＯＳＦＥＴのゲートに接続されると共に、前記各低耐圧用ＭＯＳＦＥＴのゲートと前記各充放電制御回路の高電圧側との間にダイオードと抵抗がそれぞれ並列に接続され、前記ダイオードのカソードは前記各低耐圧用出力ＭＯＳＦＥＴのゲートに接続されているものである。 According to a seventh aspect of the present invention, in the semiconductor relay device according to the fourth aspect, a diode and a resistor are connected in parallel between the gate of each high withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit. The anode of the diode is connected to the gate of each high withstand voltage output MOSFET, and a diode and a resistor are respectively connected between the gate of each low withstand voltage MOSFET and the high voltage side of each charge / discharge control circuit. Connected in parallel, the cathode of the diode is connected to the gate of each low withstand voltage output MOSFET.

請求項８の発明は、請求項１乃至請求項７に記載の半導体リレー装置において、前記外部端子に接続される負荷電圧が、所定の電圧Ｖ１以上において高周波変動し、この高周波変動の最低電位を前記所定の電圧Ｖ１とし、その最高電位を前記電圧Ｖ１に該電圧Ｖ１より小さいある電圧Ｖ２を加えた電圧（Ｖ１＋Ｖ２）である場合、前記出力部の低耐圧用出力ＭＯＳＦＥＴが前記電圧Ｖ２以上の耐圧を持つものである。 According to an eighth aspect of the present invention, in the semiconductor relay device according to any one of the first to seventh aspects, the load voltage connected to the external terminal fluctuates at a high frequency at a predetermined voltage V1 or higher, and a minimum potential of the high frequency fluctuation is reduced. When the predetermined voltage V1 is set and the highest potential is a voltage (V1 + V2) obtained by adding a voltage V2 smaller than the voltage V1 to the voltage V1, the output MOSFET for low withstand voltage of the output unit has a withstand voltage higher than the voltage V2. It has something.

請求項９の発明は、請求項８に記載の半導体リレー装置において、前記低耐圧用出力ＭＯＳＦＥＴのドレイン−ソース間に、該低耐圧用ＭＯＳＦＥＴの耐圧以下の耐圧を持つツェナーダイオードを逆並列に備えているものである。 According to a ninth aspect of the present invention, in the semiconductor relay device according to the eighth aspect, a Zener diode having a breakdown voltage equal to or lower than the breakdown voltage of the low breakdown voltage MOSFET is provided in reverse parallel between the drain and source of the low breakdown voltage output MOSFET. It is what.

請求項１０の発明は、請求項９に記載の半導体リレー装置において、前記ツェナーダイオードは前記低耐圧用出力ＭＯＳＦＥＴと同一チップに形成され、かつ該低耐圧用出力ＭＯＳＦＥＴのゲート電極材料と同じポリシリコンで形成されているものである。 According to a tenth aspect of the present invention, in the semiconductor relay device according to the ninth aspect, the Zener diode is formed on the same chip as the low breakdown voltage output MOSFET, and the same polysilicon as the gate electrode material of the low breakdown voltage output MOSFET It is formed by.

請求項１の発明によれば、高耐圧用出力ＭＯＳＦＥＴと低耐圧用出力ＭＯＳＦＥＴの２組の出力部を、各低耐圧用出力ＭＯＳＦＥＴの共通のソース端子に関して互いに対称に構成しているので、各高耐圧用出力ＭＯＳＦＥＴの各ドレインを外部端子とすることができ、外部端子の双方向より高電圧を印加可能となり、安全性、利便性が向上すると共に、複数の低容量の低耐圧用出力ＭＯＳＦＥＴの直列接続による外部端子間の低容量化により高周波特性が向上する。 According to the first aspect of the present invention, the two output portions of the high breakdown voltage output MOSFET and the low breakdown voltage output MOSFET are configured symmetrically with respect to the common source terminal of each low breakdown voltage output MOSFET. Each drain of the high withstand voltage output MOSFET can be used as an external terminal, so that a high voltage can be applied in both directions of the external terminal, improving safety and convenience, and a plurality of low capacity low withstand voltage output MOSFETs The high frequency characteristics are improved by reducing the capacitance between the external terminals by connecting in series.

請求項２の発明によれば、入力信号によるリレーのオフ時において、低耐圧用出力ＭＯＳＦＥＴを過電圧による破壊から保護することができる。 According to the invention of claim 2, when the relay is turned off by the input signal, the low withstand voltage output MOSFET can be protected from destruction due to overvoltage.

請求項３の発明によれば、入力信号のオン時において、低耐圧用出力ＭＯＳＦＥＴを過電圧による破壊から保護することができる。 According to the invention of claim 3, when the input signal is on, the low withstand voltage output MOSFET can be protected from destruction due to overvoltage.

請求項４の発明によれば、入力信号のオフ時及びオン時のいずれにおいても、低耐圧用出力ＭＯＳＦＥＴを過電圧による破壊から保護することができる。 According to the fourth aspect of the present invention, the low withstand voltage output MOSFET can be protected from destruction due to overvoltage both when the input signal is off and when it is on.

請求項５の発明によれば、入力信号のオフ時において、高耐圧用出力ＭＯＳＦＥＴの動作応答時間の速度を低耐圧用出力ＭＯＳＦＥＴの動作応答時間の速度より遅くすることができるので、低耐圧用出力ＭＯＳＦＥＴを過電圧による破壊から保護することができる。 According to the fifth aspect of the present invention, when the input signal is off, the speed of the operation response time of the high withstand voltage output MOSFET can be made slower than the speed of the operation response time of the low withstand voltage output MOSFET. The output MOSFET can be protected from destruction due to overvoltage.

請求項６の発明によれば、入力信号のオン時において、低耐圧用出力ＭＯＳＦＥＴの動作応答時間の速度を高耐圧用出力ＭＯＳＦＥＴの動作応答時間の速度より遅くすることができるので、低耐圧用出力ＭＯＳＦＥＴを過電圧による破壊から保護することができる。 According to the invention of claim 6, when the input signal is turned on, the speed of the operation response time of the low withstand voltage output MOSFET can be made slower than the speed of the operation response time of the high withstand voltage output MOSFET. The output MOSFET can be protected from destruction due to overvoltage.

請求項７の発明によれば、入力信号のオフ及びオン時に対応して、それぞれ低耐圧用出力ＭＯＳＦＥＴ及び高耐圧用出力ＭＯＳＦＥＴの動作応答時間の速度を遅くすることができるので、入力信号によるリレーのオン、オフ時のいずれにおいても低耐圧用出力ＭＯＳＦＥＴを過電圧による破壊から保護することができる。 According to the seventh aspect of the present invention, the operation response time of the low withstand voltage output MOSFET and the high withstand voltage output MOSFET can be reduced in response to the input signal being turned off and on, respectively. The output MOSFET for low withstand voltage can be protected from destruction due to overvoltage in both cases of ON and OFF.

請求項８の発明によれば、低耐圧用出力ＭＯＳＦＥＴの耐圧を負荷の高周波振幅電圧を超える範囲でかつ必要最小限の耐圧のＭＯＳＦＥＴを選択できるので、オフ容量の小さいＭＯＳＦＥＴを使用でき、高周波特性に優れたリレーを実現することが容易となる。 According to the eighth aspect of the present invention, a MOSFET having a minimum withstand voltage within a range where the withstand voltage of the low withstand voltage output MOSFET exceeds the high frequency amplitude voltage of the load can be selected. It becomes easy to realize an excellent relay.

請求項９の発明によれば、低耐圧用出力ＭＯＳＦＥＴに過電圧が加わった場合に、低耐圧用出力ＭＯＳＦＥＴを破壊する前にツェナーダイオードがブレークダウンするために、過電圧よる低耐圧用出力ＭＯＳＦＥＴの破壊を防ぐことができる。 According to the ninth aspect of the present invention, when an overvoltage is applied to the low withstand voltage output MOSFET, the Zener diode breaks down before the low withstand voltage output MOSFET is destroyed. Can be prevented.

請求項１０の発明によれば、ツェナーダイオードを作製する工程数を削減することができる。また、ポリシリコンを材料に使用することにより、単結晶シリコンよりも加工プロセス上、高精度なツェナー電圧を得られるので、複数個のツェナーダイオードを形成して、低耐圧用出力ＭＯＳＦＥＴの耐圧以下で必要なツェナー電圧を精度良く得られる。 According to the invention of claim 10, the number of steps for producing a Zener diode can be reduced. In addition, by using polysilicon as a material, it is possible to obtain a Zener voltage with higher accuracy in the processing process than single crystal silicon. Therefore, by forming a plurality of Zener diodes, the breakdown voltage of the output MOSFET for low withstand voltage can be reduced. Necessary Zener voltage can be obtained with high accuracy.

以下、本発明の一実施形態に係る半導体リレー装置について図１及び図２（ａ）、（ｂ）を参照して説明する。本実施形態における半導体リレー装置は、入力信号に応答して光信号を出力する発光素子を設けた入力部１と、光信号を受光して所定電圧を発生する第１及び第２の受光部２ａ、２ｂと、この所定電圧により出力用ＭＯＳＦＥＴをスイッチング制御する第１及び第２の充放電制御回路３ａ、３ｂ（電圧制御回路）と、各出力ソースを共通に互いに直列に接続された一対の出力用ＭＯＳＦＥＴを有する第１及び第２の出力部４ａ、４ｂとを備える。これら一対の出力用ＭＯＳＦＥＴは、それぞれ高耐圧、低オン抵抗、高容量の高耐圧用出力ＭＯＳＦＥＴ４１、４４（以下、高耐圧ＦＥＴという）と、低耐圧、低オン抵抗、低容量の低耐圧用出力ＭＯＳＦＥＴ４２、４３（以下、低耐圧ＦＥＴという）で構成される。また、各低耐圧ＦＥＴ４２、４３のドレイン間を接続することにより、２組の出力部４ａ、４ｂは直列接続され、全体出力部４を構成する。各高耐圧ＦＥＴ４１、４４のドレイン端子は、全体出力部４の外部端子４５ａ、４５ｂとなる。なお、出力用ＭＯＳＦＥＴは、大きな電流を流せるパワーＭＯＳＦＥＴを用い、それらの各パワーＭＯＳＦＥＴのドレイン−ソース間には、逆方向電流を流す逆方向ダイオードが内蔵されている。 Hereinafter, a semiconductor relay device according to an embodiment of the present invention will be described with reference to FIG. 1 and FIGS. 2 (a) and 2 (b). The semiconductor relay device in this embodiment includes an input unit 1 provided with a light emitting element that outputs an optical signal in response to an input signal, and first and second light receiving units 2a that receive the optical signal and generate a predetermined voltage. 2b, the first and second charge / discharge control circuits 3a and 3b (voltage control circuit) for controlling the switching of the output MOSFET with the predetermined voltage, and a pair of outputs in which each output source is connected in series with each other in common. And first and second output units 4a and 4b each having a power MOSFET. The pair of output MOSFETs are a high withstand voltage, low on-resistance, high capacity high withstand voltage output MOSFETs 41 and 44 (hereinafter referred to as high withstand voltage FET), and a low withstand voltage, low on resistance, low capacity output for low withstand voltage. It is composed of MOSFETs 42 and 43 (hereinafter referred to as low breakdown voltage FETs). Further, by connecting the drains of the low breakdown voltage FETs 42 and 43, the two sets of output units 4 a and 4 b are connected in series to constitute the entire output unit 4. The drain terminals of the high breakdown voltage FETs 41 and 44 become the external terminals 45 a and 45 b of the overall output unit 4. The output MOSFET uses a power MOSFET that can flow a large current, and a reverse diode that flows a reverse current is built in between the drain and source of each power MOSFET.

入力部１は、発光素子して発光ダイオード１１を有し、入力端子１２からの入力信号により、発光ダイオード１１より光信号を発光する。受光部２ａ、２ｂは、受光素子として太陽電池２１（又はフォトダイオード）を有し、ＬＥＤ１１（発光ダイオード）より光信号を受光して、光起電力を誘起し、所定電圧を発生する。 The input unit 1 has a light emitting diode 11 as a light emitting element, and emits an optical signal from the light emitting diode 11 in response to an input signal from the input terminal 12. The light receiving units 2a and 2b have a solar cell 21 (or a photodiode) as a light receiving element, receive an optical signal from the LED 11 (light emitting diode), induce a photovoltaic force, and generate a predetermined voltage.

充放電制御回路３ａ、３ｂは、電圧制御用のデプレッション型（ノーマリオフ）のＭＯＳＦＥＴ３１及びエンハンスメント型（ノーマリオン）のＭＯＳＦＥＴ３２と、抵抗３３とを備え、ＭＯＳＦＥＴ３１のドレインとゲートは、受光部２ａ、２ｂの高電位側と低電位側にそれぞれ接続される。ＭＯＳＦＥＴ３２のドレインとソースは、ＭＯＳＦＥＴ３１のソースとゲートにそれぞれ接続されると共に、抵抗Ｒ３３で短絡され、そのドレインとゲートは、短絡接続される。 The charge / discharge control circuits 3a and 3b include a depletion type (normally off) MOSFET 31 for voltage control, an enhancement type (normally on) MOSFET 32, and a resistor 33. The drain and gate of the MOSFET 31 are connected to the light receiving units 2a and 2b. Connected to the high potential side and the low potential side, respectively. The drain and source of the MOSFET 32 are connected to the source and gate of the MOSFET 31, respectively, and are short-circuited by a resistor R33, and the drain and gate are short-circuited.

充放電制御回路３ａ、３ｂにおいて、受光部２ａ、２ｂからの所定電圧が、ＭＯＳＦＥＴ３１のドレインとゲートに加えられると、ＭＯＳＦＥＴ３２がオフからオンになり、ＭＯＳＦＥＴ３１がオンからオフになる。この時、第１の出力部４ａ及び第２の出力部４ｂの各高耐圧ＦＥＴ４１、４４及び低耐圧ＦＥＴ４２、４３のゲート、ソース間に電位差が発生し、ゲートが充電され、上記各ＦＥＴ４１〜４４が駆動する。次に、ＬＥＤ１１からの光信号が遮断されると、上記と同様にして、ＭＯＳＦＥＴ３２がオンからオフとなり、ＭＯＳＦＥＴ３１がオフからオンとなる。これにより、各ＦＥＴ４１〜４４のゲート、ソース間に電位差が消失し、ゲートが放電され、各ＦＥＴ４１〜４４がオフ状態となる。この充放電制御回路３ａ、３ｂを設けたことにより、各ＦＥＴ４１〜４４の充放電の切替をスムーズに行うことができる。 In the charge / discharge control circuits 3a and 3b, when a predetermined voltage from the light receiving portions 2a and 2b is applied to the drain and gate of the MOSFET 31, the MOSFET 32 is turned on and the MOSFET 31 is turned off. At this time, a potential difference is generated between the gates and sources of the high breakdown voltage FETs 41 and 44 and the low breakdown voltage FETs 42 and 43 of the first output unit 4a and the second output unit 4b, the gates are charged, and the FETs 41 to 44 are charged. Drive. Next, when the optical signal from the LED 11 is cut off, the MOSFET 32 is turned off and the MOSFET 31 is turned on from off in the same manner as described above. As a result, the potential difference between the gates and sources of the FETs 41 to 44 disappears, the gates are discharged, and the FETs 41 to 44 are turned off. By providing the charge / discharge control circuits 3a, 3b, the charge / discharge switching of the FETs 41 to 44 can be performed smoothly.

第１及び第２の出力部４ａ、４ｂにおいて、出力用ＭＯＳＦＥＴは、パワーＭＯＳＦＥＴより成り、それらの各パワーＭＯＳＦＥＴのドレイン−ソース間には、逆過電圧からＦＥＴを保護する逆方向ダイオードが内蔵されている。一般にパワーＭＯＳＦＥＴは、入力信号がオンにより発生した所定電圧に基づき、充放電制御回路からの制御電圧が各ＦＥＴ４１〜４４のゲートとソース間に加えられると、各ＦＥＴ４１〜４４は導通状態となり、外部端子４５ａと４５ｂ間は導通され、リレーが閉じられる。入力信号がオフになると、充放電制御回路からの制御電圧が無くなり、各ＦＥＴ４１〜４４は非導通状態となり、外部端子４５ａと４５ｂ間は遮断され、リレーが開放される。 In the first and second output units 4a and 4b, the output MOSFET is a power MOSFET, and a reverse diode that protects the FET from reverse overvoltage is incorporated between the drain and source of each power MOSFET. Yes. In general, in a power MOSFET, when a control voltage from a charge / discharge control circuit is applied between the gates and sources of the FETs 41 to 44 based on a predetermined voltage generated when an input signal is turned on, the FETs 41 to 44 become conductive, and external The terminals 45a and 45b are electrically connected and the relay is closed. When the input signal is turned off, the control voltage from the charge / discharge control circuit is lost, the FETs 41 to 44 are turned off, the external terminals 45a and 45b are cut off, and the relay is opened.

上記全体出力部４において、高耐圧ＦＥＴ４１、４４のオフ耐圧をＶ１、オフ容量をＣ１、オン抵抗をＲ１とし、低耐圧ＦＥＴ４２、４３のオフ耐圧をＶ２、オフ容量をＣ２、オン抵抗をＲ２とし、Ｖ１≫Ｖ２、Ｃ１≫Ｃ２、Ｒ１≒Ｒ２であるとする。図１に示される全体出力部４では、出力用ＭＯＳＦＥＴとして、ドレイン、ソース間に逆方向ダイオードを内臓するパワーＭＯＳＦＥＴを用いている。端子間耐圧ＶｔはＶ１≫Ｖ２より、
Ｖｔ＝Ｖ１＋Ｖ２≒Ｖ１
端子間容量Ｃｔは、Ｃ１≫Ｃ２より、
Ｃｔ＝（Ｃ１・Ｃ２）／（２・Ｃ１＋２・Ｃ２）≒０．５・Ｃ２、
端子間オン抵抗Ｒｔは、
Ｒｔ＝２（Ｒ１＋Ｒ２）、
となる。このように、端子間容量Ｃｔは、高い方の耐圧Ｖ１でほぼ決まるので、高耐圧を維持でき、端子間容量Ｃｔは、低容量の低耐圧ＦＥＴが２個直列に挿入されているため従来の半分の低容量となり、Ｃ×Ｒの値を小さくすることが可能となる。これにより、高耐圧、低容量、低オン抵抗の半導体リレー装置を得ることができる。 In the overall output section 4, the high breakdown voltage FETs 41 and 44 have an off breakdown voltage V1, an off capacitance C1, an on resistance R1, a low breakdown voltage FETs 42 and 43 an off breakdown voltage V2, an off capacitance C2, and an on resistance R2. , V1 >> V2, C1 >> C2, and R1≈R2. In the overall output unit 4 shown in FIG. 1, a power MOSFET incorporating a reverse diode between a drain and a source is used as an output MOSFET. The inter-terminal breakdown voltage Vt is V1 >> V2,
Vt = V1 + V2≈V1
The inter-terminal capacitance Ct is C1 >> C2.
Ct = (C1 · C2) / (2 · C1 + 2 · C2) ≈0.5 · C2,
The on-resistance Rt between terminals is
Rt = 2 (R1 + R2),
It becomes. Thus, since the inter-terminal capacitance Ct is substantially determined by the higher breakdown voltage V1, the high breakdown voltage can be maintained, and the inter-terminal capacitance Ct is the conventional one because two low-capacitance low-voltage FETs are inserted in series. The capacity is reduced by half, and the value of C × R can be reduced. Thereby, a semiconductor relay device having a high breakdown voltage, a low capacity, and a low on-resistance can be obtained.

また、全体出力部４においては、一対の高耐圧ＦＥＴと低耐圧ＦＥＴを持つ第１の出力部４ａと第２の出力部４ｂが逆直列に接続され、外部端子４５ａと４５ｂは共に、高耐圧ＦＥＴ４１、４４のドレイン端子となるように構成されている。これにより、半導体リレー装置の両端子は共に高耐圧ＦＥＴ４２、４４に接続される。そして、第１、第２の出力部４ａ、４ｂは低耐圧ＦＥＴ４２、４３の接続点に対して対称となっているので、半導体リレー装置の外部端子４５ａと４５ｂと負荷との接続に際して、接続の方向性がなくなり、負荷電圧の高電圧側、低電圧側のいずれに接続しても、低耐圧ＦＥＴ４２、４３を耐圧破壊を防御することができる。 Further, in the overall output unit 4, the first output unit 4a and the second output unit 4b having a pair of high breakdown voltage FET and low breakdown voltage FET are connected in reverse series, and both the external terminals 45a and 45b have a high breakdown voltage. The drain terminals of the FETs 41 and 44 are configured. Thereby, both terminals of the semiconductor relay device are connected to the high voltage FETs 42 and 44. Since the first and second output portions 4a and 4b are symmetrical with respect to the connection point of the low breakdown voltage FETs 42 and 43, the connection of the external terminals 45a and 45b of the semiconductor relay device and the load The directivity is lost, and the low breakdown voltage FETs 42 and 43 can be protected from breakdown voltage regardless of whether the load voltage is connected to either the high voltage side or the low voltage side.

上記のように、本実施形態によれば、高耐圧、低容量、低オン抵抗の全体出力部４を形成することが可能となり、高周波特性に優れた高耐圧の半導体リレー装置を実現することができると共に、負荷接続の双方向性を可能とし、半導体リレー装置の安全性と、ユーザの利便性を向上することができる。 As described above, according to the present embodiment, it is possible to form the entire output unit 4 having a high withstand voltage, a low capacity, and a low on-resistance, thereby realizing a high withstand voltage semiconductor relay device having excellent high frequency characteristics. In addition, the load connection can be made bidirectional, and the safety of the semiconductor relay device and the convenience of the user can be improved.

また、本回路構成において、低耐圧ＦＥＴは、高集積性を持つＳＯＩ（Ｓｉｌｉｃｏｎｏｎｉｎｓｕｌａｔｏｒ）ウエハを用いて作製することによって、従来品と比較して、さらにＣ×Ｒを小さく形成することができる。さらに、低耐圧ＦＥＴを同一チップにて形成することにより低コスト化が可能となる。また、二つの受光部２ａ、２ｂ、充放電制御回路３ａ、３ｂとを同一チップに形成し、かつ、これらの回路と低耐圧ＦＥＴとを同一チップにより形成することによって、さらに低コスト化が可能である。 Further, in this circuit configuration, the low breakdown voltage FET can be formed smaller by using a SOI (silicon on insulator) wafer having high integration than the conventional product, by making it using a highly integrated SOI (silicon on insulator) wafer. . Further, the cost can be reduced by forming the low breakdown voltage FET on the same chip. Further, it is possible to further reduce the cost by forming the two light receiving portions 2a and 2b and the charge / discharge control circuits 3a and 3b on the same chip, and forming these circuits and the low breakdown voltage FET on the same chip. It is.

次に、本発明の第２の実施形態に係る半導体リレー装置について図２、図（３）を参照して説明する。本実施形態は、上記第１の実施形態の構成において、各低耐圧ＦＥＴ４２、４３のゲート端子と各充放電制御回路３ａ、３ｂの高電圧側との間にダイオード４６ａと抵抗４７ａをそれぞれ並列に接続し、ダイオード４６ａのカソード端子を各低耐圧ＦＥＴ４２、４３のゲート端子に接続したものである。図２に示した本実施形態において、上記第１の実施形態の部材と同等部材には同一符号を付し、重複説明は省く（以下、同様）。 Next, a semiconductor relay device according to a second embodiment of the present invention will be described with reference to FIGS. 2 and 3. In the present embodiment, in the configuration of the first embodiment, a diode 46a and a resistor 47a are connected in parallel between the gate terminals of the low breakdown voltage FETs 42 and 43 and the high voltage side of the charge / discharge control circuits 3a and 3b, respectively. The cathode terminal of the diode 46a is connected to the gate terminal of each low breakdown voltage FET 42, 43. In the present embodiment shown in FIG. 2, the same members as those of the first embodiment are denoted by the same reference numerals, and redundant description is omitted (the same applies hereinafter).

本実施形態の回路構成において、充放電制御回路３ａ、３ｂの高電圧側と低耐圧ＦＥＴ４２、４３のゲート端子との間に、ダイオード４６ａ、抵抗４７ａの並列回路及びダイオード４６ｂ、抵抗４７ｂの並列回路がそれぞれ挿入されている。この回路構成では、入力信号のオン時に、受光部３ａ、３ｂからの所定電圧がダイオード４６ａ、４６ｂと抵抗４７ａ、４７ｂの各並列回路を介して高耐圧ＭＯＳＦＥＴ４１、４４に印加される。この時、各ダイオード４６ａ、４６ｂが順方向接続となるため導通し、その電圧は各ゲート端子に直接印加される。一方、入力信号のオフ時は、各ダイオード４６ａ、４６ｂが逆方向接続となるため、非導通となり、所定電圧が抵抗４７ａ、４７ｂを介して各ゲート端子に接続される。そして、これら抵抗４７ａ、４７ｂと高耐圧ＭＯＳＦＥＴ４１、４４の入力容量により、高耐圧ＦＥＴ４１、４４のゲート電圧が遅延される。このため、低耐圧ＦＥＴ４２、４３の立ち下がりの速さが高耐圧ＦＥＴ４１、４４より遅くなる。 In the circuit configuration of this embodiment, a parallel circuit of a diode 46a and a resistor 47a and a parallel circuit of a diode 46b and a resistor 47b are provided between the high voltage side of the charge / discharge control circuits 3a and 3b and the gate terminals of the low breakdown voltage FETs 42 and 43. Are inserted. In this circuit configuration, when the input signal is turned on, a predetermined voltage from the light receiving portions 3a and 3b is applied to the high voltage MOSFETs 41 and 44 via the parallel circuits of the diodes 46a and 46b and the resistors 47a and 47b. At this time, the diodes 46a and 46b are connected in the forward direction so that they are turned on, and the voltage is directly applied to the gate terminals. On the other hand, when the input signal is turned off, the diodes 46a and 46b are connected in the reverse direction, so that they are non-conductive, and a predetermined voltage is connected to the gate terminals via the resistors 47a and 47b. The gate voltages of the high breakdown voltage FETs 41 and 44 are delayed by the input capacitances of the resistors 47a and 47b and the high breakdown voltage MOSFETs 41 and 44. For this reason, the falling speed of the low breakdown voltage FETs 42 and 43 is slower than that of the high breakdown voltage FETs 41 and 44.

図３（ａ）、（ｂ）を参照して、高耐圧ＦＥＴ４１及び低耐圧ＦＥＴ４２の立ち上がり、立ち下がりの動作応答時間の様子を説明する。高耐圧ＦＥＴ４４及び低耐圧ＦＥＴ４３についても同様であるので、高耐圧ＦＥＴ４１及び低耐圧ＦＥＴ４２についてのみ説明する。図３（ａ）は、ダイオード４６ａと抵抗４７ａの並列回路が無い場合の立ち上がり、立ち下がりの動作応答時間の状態を示し、（ｂ）は、同並列回路が有る場合の同様の状態を示す。図３（ａ）において、入力信号は立ち上がりの時間ｔ１でオンし、立ち下がりの時間ｔ７でオフするとする。これに対応して、低耐圧ＦＥＴ４２は、入力容量のため時間ｔ１より少し遅れて時間ｔ２でオンし、入力信号の立ち下がりの時間ｔ７とほぼ同時にオフする。また、高耐圧ＦＥＴ４１は、入力容量がさらに大きいため、そのオン時間ｔ３及びオフ時間ｔ６は共に、それぞれ低耐圧ＦＥＴ４２のオン時間ｔ２及びオフ時間ｔ５より遅くなる。 With reference to FIGS. 3A and 3B, the state of the operation response time of the rise and fall of the high breakdown voltage FET 41 and the low breakdown voltage FET 42 will be described. Since the same applies to the high voltage FET 44 and the low voltage FET 43, only the high voltage FET 41 and the low voltage FET 42 will be described. FIG. 3A shows the state of the rising and falling operation response times when there is no parallel circuit of the diode 46a and the resistor 47a, and FIG. 3B shows the same state when there is the parallel circuit. In FIG. 3A, the input signal is turned on at the rise time t1 and turned off at the fall time t7. Corresponding to this, the low breakdown voltage FET 42 is turned on at time t2 with a slight delay from the time t1 due to the input capacitance, and is turned off almost simultaneously with the falling time t7 of the input signal. Further, since the high withstand voltage FET 41 has a larger input capacitance, both the on time t3 and the off time t6 are later than the on time t2 and the off time t5 of the low withstand voltage FET 42, respectively.

上記回路構成の高耐圧ＦＥＴ４１と低耐圧ＦＥＴ４２において、各ＦＥＴとも非導通時にオフ耐圧が掛かる。特に、低耐圧ＦＥＴ４２の非導通時に、直列接続されている高耐圧ＦＥＴ４１が導通状態であると、外部端子の負荷電圧がほぼ全て低耐圧ＦＥＴ４２に印加されるので、低耐圧ＦＥＴ４２は過電圧が掛かり耐圧破壊される虞がある。このため、低耐圧ＦＥＴ４２は、高耐圧ＦＥＴ４１より速くオンし、かつ遅くオフすることが必要である。すなわち、高耐圧ＦＥＴ４１のオン状態では、それ以前に低耐圧ＦＥＴ４２がオン状態であることが必要である。しかしながら、図３（ａ）の点線で囲んだＡ部に示されるように、通常、低耐圧ＦＥＴは、高耐圧ＦＥＴより低容量なので、オフの動作応答時間が高耐圧ＦＥＴより速くなる。このため、入力信号の立ち下がりにおいて、低耐圧ＦＥＴは高耐圧ＦＥＴのオン状態において速くオフするので耐圧過剰となり破壊される虞があった。 In the high breakdown voltage FET 41 and the low breakdown voltage FET 42 having the above-described circuit configuration, each FET is turned off when it is not conducting. In particular, if the high-voltage FET 41 connected in series is in a conductive state when the low-voltage FET 42 is non-conductive, almost all of the load voltage at the external terminal is applied to the low-voltage FET 42. There is a risk of being destroyed. For this reason, the low breakdown voltage FET 42 needs to be turned on faster than the high breakdown voltage FET 41 and turned off later. That is, when the high breakdown voltage FET 41 is on, the low breakdown voltage FET 42 needs to be on before that time. However, as indicated by the part A surrounded by the dotted line in FIG. 3A, the low breakdown voltage FET normally has a lower capacity than the high breakdown voltage FET, and therefore, the off operation response time is faster than the high breakdown voltage FET. For this reason, at the falling edge of the input signal, the low breakdown voltage FET is quickly turned off in the on state of the high breakdown voltage FET, so that the breakdown voltage is excessive and may be destroyed.

これに対し、図３（ｂ）の点線で囲んだＡ１部に示されるように、ダイオード４６ａと抵抗４７ａをゲート端子側に接続したことにより、低耐圧ＦＥＴ４２は、高耐圧ＦＥＴ４１より、オフ時間を遅くすることができる。これにより、入力信号の立ち下がり時には、低耐圧ＦＥＴ４２は、高耐圧ＦＥＴより遅くオフするようにできるので耐圧過剰による破壊を防ぐことができる。 On the other hand, as indicated by the A1 portion surrounded by the dotted line in FIG. 3B, the low breakdown voltage FET 42 has a longer off time than the high breakdown voltage FET 41 by connecting the diode 46a and the resistor 47a to the gate terminal side. Can be late. As a result, when the input signal falls, the low breakdown voltage FET 42 can be turned off later than the high breakdown voltage FET, thereby preventing damage due to excessive breakdown voltage.

上記のように本実施形態では、ダイオード４６ａ、４６ｂと抵抗４７ａ、４７ｂによる簡単な並列回路の導入により、入力信号の立ち上がり時に、低耐圧ＦＥＴ４２、４３の動作応答時間を遅く、高耐圧ＦＥＴ４１、４４の動作応答時間を速くすることにより、低耐圧ＦＥＴ４２、４３のオフの速度を高耐圧ＦＥＴ４１、４４のオフの速度より遅くし、低耐圧ＦＥＴ４２、４３を過電圧の耐圧破壊から保護することができる。 As described above, in the present embodiment, by introducing a simple parallel circuit using the diodes 46a and 46b and the resistors 47a and 47b, the operation response time of the low breakdown voltage FETs 42 and 43 is delayed when the input signal rises, and the high breakdown voltage FETs 41 and 44 are provided. By making the operation response time faster, the OFF speed of the low breakdown voltage FETs 42, 43 can be made slower than the OFF speed of the high breakdown voltage FETs 41, 44, and the low breakdown voltage FETs 42, 43 can be protected from overvoltage breakdown.

次に、本発明の第３の実施形態に係る半導体リレー装置について図４（ａ）、（ｂ）を参照して説明する。本実施形態は、上記第１の実施形態の構成において、各高耐圧ＦＥＴ４１、４４のゲート端子と各充放電制御回路３ａ、３ｂの高電圧側との間にダイオード４８ａと抵抗４９ａ）をそれぞれ並列に接続し、ダイオード４８ａ、４８ｂのアノード端子を各高耐圧ＦＥＴ４１、４４のゲート端子に接続したものである。 Next, a semiconductor relay device according to a third embodiment of the present invention will be described with reference to FIGS. 4 (a) and 4 (b). In this embodiment, in the configuration of the first embodiment, a diode 48a and a resistor 49a) are connected in parallel between the gate terminals of the high breakdown voltage FETs 41 and 44 and the high voltage side of the charge / discharge control circuits 3a and 3b. And the anode terminals of the diodes 48a and 48b are connected to the gate terminals of the high-voltage FETs 41 and 44, respectively.

本実施形態において、図４（ａ）に示すように、ダイオード４８ａと抵抗４９ａの並列回路、及びダイオード４８ｂと抵抗４９ｂの並列回路がそれぞれ各高耐圧ＦＥＴ４１、４４のゲート端子に接続されている。この回路構成において、入力信号のオン時に、所定電圧は、ダイオード４８ａ、４８ｂと抵抗４９ａ、４９ｂの各並列回路を介して高耐圧ＦＥＴ４１、４４に印加されるが、各ダイオード４８ａ、４８ｂが逆方向接続となるため非導通となり、所定電圧は、抵抗４７ａ、４７ｂを介して高耐圧ＦＥＴ４１、４４の各ゲート端子に印加される。各ゲート端子のゲート電圧は、抵抗４７ａ、４７ｂと高耐圧ＦＥＴ４１、４４の入力容量により遅延される。このため、高耐圧ＦＥＴ４１、４２のオンの速さが低耐圧ＦＥＴ４２、４３より遅くなる。 In the present embodiment, as shown in FIG. 4A, a parallel circuit of a diode 48a and a resistor 49a, and a parallel circuit of a diode 48b and a resistor 49b are connected to the gate terminals of the high voltage FETs 41 and 44, respectively. In this circuit configuration, when the input signal is turned on, a predetermined voltage is applied to the high breakdown voltage FETs 41 and 44 through the parallel circuits of the diodes 48a and 48b and the resistors 49a and 49b, but the diodes 48a and 48b are reversed. Since it is connected, it becomes non-conductive, and a predetermined voltage is applied to the gate terminals of the high voltage FETs 41 and 44 via the resistors 47a and 47b. The gate voltage of each gate terminal is delayed by the input capacitances of the resistors 47a and 47b and the high breakdown voltage FETs 41 and 44. For this reason, the turn-on speed of the high breakdown voltage FETs 41 and 42 is slower than that of the low breakdown voltage FETs 42 and 43.

ここで、本実施形態の低耐圧ＦＥＴと高耐圧ＦＥＴの動作応答時間の様子を図４（ｂ）に示す。図４（ｂ）の点線で囲まれたＢ１部に示されるように、入力信号が入力されると、まず、低耐圧ＦＥＴ４２が時間ｔ２でオン状態になり、その後、高耐圧ＦＥＴ４１が、時間ｔ３よりさらに遅い時間ｔ４でオンされる。 Here, FIG. 4B shows the operation response time of the low breakdown voltage FET and the high breakdown voltage FET of the present embodiment. 4B, when an input signal is input, first, the low breakdown voltage FET 42 is turned on at time t2, and then the high breakdown voltage FET 41 is switched to time t3. It is turned on at a later time t4.

ところで、上記ダイオード４８ａと抵抗４９ａの並列回路が存在しない場合は、前記図３（ａ）の点線で囲まれたＢ部に示されたように、低耐圧ＦＥＴ４２は、高耐圧ＦＥＴ４１より先にオン状態にあり、オフ状態である高耐圧ＦＥＴ４１によって負荷側の電流がせき止められているので、一般には過電圧が印加されて破壊される可能性は低いと考えられる。 By the way, when there is no parallel circuit of the diode 48a and the resistor 49a, the low breakdown voltage FET 42 is turned on before the high breakdown voltage FET 41, as shown in the part B surrounded by the dotted line in FIG. Since the load-side current is blocked by the high-voltage FET 41 that is in the off-state, it is generally considered that there is a low possibility that the overvoltage is applied and destroyed.

しかしながら、温度特性、ならびに半導体素子の特性のばらつきを考慮した場合、低耐圧ＦＥＴ４２が高耐圧ＦＥＴ４１に比べ、動作時間が遅くなってしまう可能性は否定できない。これに対し、ダイオードと抵抗の並列回路を導入することにより、高耐圧ＦＥＴ４１のオン時間を時間ｔ３から時間ｔ４へさらに遅延時間を延ばすことができるので、高耐圧ＦＥＴ４１の動作時間を、低耐圧ＦＥＴ４２に比べて確実に遅くすることができる。すなわち、各ＦＥＴのゲートを充電する信号入力時にはダイオード４８ａに並列の抵抗４９ａが動作を遅延させ、遮断時にはダイオード４８ａによって素早く放電されるため、高耐圧ＦＥＴ４１の立ち上がり動作応答時間のみを遅くすることができる。これにより、従来に比べて、オン時に低耐圧ＦＥＴ４２が破壊される危険性をさらに低減することができる。 However, when temperature characteristics and variations in characteristics of semiconductor elements are taken into consideration, the possibility that the operation time of the low breakdown voltage FET 42 is delayed compared to the high breakdown voltage FET 41 cannot be denied. On the other hand, by introducing a parallel circuit of a diode and a resistor, the on-time of the high breakdown voltage FET 41 can be further extended from time t3 to time t4, so that the operation time of the high breakdown voltage FET 41 is reduced to the low breakdown voltage FET 42. Compared to, it can be surely slow. That is, when a signal for charging the gate of each FET is input, the resistor 49a in parallel with the diode 48a delays the operation, and when it is cut off, the diode 48a discharges quickly, so that only the rise operation response time of the high voltage FET 41 can be delayed. it can. Thereby, compared with the past, the danger that the low voltage | pressure-resistant FET42 will be destroyed at the time of ON can further be reduced.

次に、本発明の第４の実施形態に係る半導体リレー装置について図５（ａ）、（ｂ）を参照して説明する。本実施形態は、上記第１の実施形態の構成において、高耐圧ＦＥＴ４１、４４及び低耐圧ＦＥＴ４２、４３のゲート端子と各充放電制御回路３ａ、３ｂの高電圧側との間にダイオードと抵抗の並列回路を挿入し、高耐圧ＦＥＴ４１、４４のゲート端子には、ダイオードのアノード側を接続し、低耐圧ＦＥＴ４２、４３のゲート端子には、ダイオードのカソード側を接続したものである。 Next, a semiconductor relay device according to a fourth embodiment of the present invention will be described with reference to FIGS. In this embodiment, in the configuration of the first embodiment, a diode and a resistor are connected between the gate terminals of the high breakdown voltage FETs 41 and 44 and the low breakdown voltage FETs 42 and 43 and the high voltage side of the charge / discharge control circuits 3a and 3b. A parallel circuit is inserted, and the anode terminal of the diode is connected to the gate terminals of the high breakdown voltage FETs 41 and 44, and the cathode side of the diode is connected to the gate terminals of the low breakdown voltage FETs 42 and 43.

図５（ａ）において、ダイオード４６ａ、４６ｂと抵抗４７ａ、４７ｂによるダイオード・抵抗並列回路が各充放電制御回路３ａ、３ｂの高電圧側と低耐圧ＦＥＴ４２、４３のゲート端子との間にそれぞれ接続され、各ダイオード４６ａ、４６ｂのカソード側が各低耐圧ＦＥＴ４２、４３のゲート端子に接続される。同時に、ダイオード４８ａ、４８ｂと抵抗４９ａ、４９ｂによるダイオード・抵抗の並列回路が各高耐圧ＦＥＴ４１、４４のゲート端子と各充放電制御回路３ａ、３ｂの高電圧側との間にそれぞれ接続され、ダイオード４８ａ、４８ｂのアノード側は各高耐圧ＦＥＴ４１、４４のゲート端子側に接続されている。 In FIG. 5A, a diode / resistor parallel circuit including diodes 46a and 46b and resistors 47a and 47b is connected between the high voltage side of the charge / discharge control circuits 3a and 3b and the gate terminals of the low voltage FETs 42 and 43, respectively. The cathode side of each diode 46a, 46b is connected to the gate terminal of each low breakdown voltage FET 42, 43. At the same time, a diode / resistor parallel circuit including diodes 48a and 48b and resistors 49a and 49b is connected between the gate terminals of the high voltage FETs 41 and 44 and the high voltage side of the charge / discharge control circuits 3a and 3b, respectively. The anode side of 48a, 48b is connected to the gate terminal side of each high breakdown voltage FET 41, 44.

本実施形態の入力信号による高耐圧ＦＥＴ４１、４４と低耐圧ＦＥＴ４２、４３の動作応答時間の関係を図５（ｂ）に示す。ダイオード４６ａ、４６ｂ、４８ａ、４８ｂと抵抗４７ａ、４７ｂ、４９ａ、４９ｂの導入により、入力信号のオン、オフ時に、各高耐圧ＦＥＴのオンと各低耐圧ＦＥＴのオフの各動作応答時間をそれぞれ遅くすることができる。すなわち、図５（ｂ）の点線で囲まれたＢ２部、Ａ２部に示されるように、入力信号がオン時には、高耐圧ＦＥＴ４１、４４のオンの動作応答時間が時間ｔ２から時間ｔ３に遅延され、入力信号がオフ時には、低耐圧ＦＥＴ４２、４３のオフ時間が時間ｔ６から時間ｔ７まで遅延される。このように、入力信号のオン時、オフ時とも、低耐圧ＦＥＴ４２、４３の動作時間範囲内に高耐圧ＦＥＴ４１、４４の動作時間が存在するようにできるので、高耐圧ＦＥＴ４１、４４のオン時に、低耐圧ＦＥＴ４２、４３のオフ状態を無くすことができる。これにより、低耐圧ＦＥＴ４２、４３を高電圧による破壊から守ることができる。 FIG. 5B shows the relationship between the operation response times of the high breakdown voltage FETs 41 and 44 and the low breakdown voltage FETs 42 and 43 according to the input signal of this embodiment. By introducing the diodes 46a, 46b, 48a, 48b and the resistors 47a, 47b, 49a, 49b, when the input signal is turned on / off, each operation response time of turning on each high voltage FET and turning off each low voltage FET is delayed. can do. That is, as shown in B2 part and A2 part surrounded by a dotted line in FIG. 5B, when the input signal is on, the on-operation response time of the high breakdown voltage FETs 41 and 44 is delayed from time t2 to time t3. When the input signal is off, the off time of the low breakdown voltage FETs 42 and 43 is delayed from time t6 to time t7. As described above, since the operation time of the high voltage FETs 41 and 44 can be present within the operation time range of the low voltage FETs 42 and 43 both when the input signal is turned on and off, when the high voltage FETs 41 and 44 are turned on, The OFF state of the low breakdown voltage FETs 42 and 43 can be eliminated. As a result, the low breakdown voltage FETs 42 and 43 can be protected from destruction by a high voltage.

次に、本発明の第５の実施形態に係る半導体リレー装置について図６を参照して説明する。本実施形態は、特に図示しないが、上述の各実施形態において、外部端子に接続される負荷電圧が、所定の電圧Ｖ１以上において高周波変動し、この高周波変動の最低電位を所定電圧Ｖ１とし、その最高電位を電圧Ｖ１に電圧Ｖ１より小さいある電圧Ｖ２を加えた電圧（Ｖ１＋Ｖ２）であるとする場合、出力部の低耐圧ＦＥＴが電圧Ｖ２以上の耐圧を持つものである。 Next, a semiconductor relay device according to a fifth embodiment of the present invention will be described with reference to FIG. Although this embodiment is not particularly illustrated, in each of the above-described embodiments, the load voltage connected to the external terminal fluctuates at a high frequency at a predetermined voltage V1 or higher, and the lowest potential of the high-frequency fluctuation is set to the predetermined voltage V1, When the highest potential is a voltage (V1 + V2) obtained by adding a certain voltage V2 smaller than the voltage V1 to the voltage V1, the low withstand voltage FET in the output section has a withstand voltage equal to or higher than the voltage V2.

本実施形態において、外部端子４５ａ、４５ｂ間の耐圧Ｖは、高耐圧ＦＥＴの耐圧をＶ１とし、低耐圧ＦＥＴの耐圧をＶ２とすると、（Ｖ１＋Ｖ２）となる。従って、図６に示すように、負荷電流が負荷の所定電位（Ｖａとする）以上において高周波動作しており、例えば、高周波変動の振幅（Ｖｂとする）を１０Ｖとし、負荷の所定電位Ｖａを２００Ｖとして、高周波変動の振幅１０Ｖが所定電位２００Ｖに重畳されているような波形を持つ場合、低耐圧ＦＥＴの耐圧Ｖ２を高周波変動の振幅１０Ｖ以上程度にすることができる。前述のように、ＭＯＳＦＥＴのオフ容量は、小さいことが望まれるので、必要とされる耐圧が小さければ小さいほど良い。そのため、高周波変動の振幅Ｖｂを超える範囲において、低耐圧ＦＥＴの耐圧Ｖ２をできるだけ小さくする方が良い。本実施形態によれば、必要最小限の耐圧のＭＯＳＦＥＴを選択できるので、オフ容量の小さいＭＯＳＦＥＴを使用でき、高周波特性に優れたリレーを実現することが容易となる。 In this embodiment, the withstand voltage V between the external terminals 45a and 45b is (V1 + V2), where the withstand voltage of the high withstand voltage FET is V1 and the withstand voltage of the low withstand voltage FET is V2. Accordingly, as shown in FIG. 6, the load current operates at a high frequency when the load current is equal to or higher than a predetermined potential (Va) of the load. For example, the amplitude (Vb) of the high-frequency fluctuation is 10 V, and the predetermined potential Va of the load is When 200 V has a waveform in which the amplitude 10V of the high frequency fluctuation is superimposed on the predetermined potential 200V, the withstand voltage V2 of the low breakdown voltage FET can be set to about 10V or more of the amplitude of the high frequency fluctuation. As described above, the off-capacitance of the MOSFET is desired to be small, so that the smaller the required withstand voltage, the better. Therefore, it is better to make the withstand voltage V2 of the low withstand voltage FET as small as possible within the range exceeding the amplitude Vb of the high frequency fluctuation. According to this embodiment, a MOSFET having a minimum necessary withstand voltage can be selected, so that a MOSFET having a small off-capacitance can be used, and a relay excellent in high-frequency characteristics can be easily realized.

次に、本発明の第６の実施形態に係る半導体リレー装置について図７を参照して説明する。本実施形態は、低耐圧ＦＥＴ４２、４３のドレイン−ソース間に、低耐圧ＦＥＴ４２、４３の耐圧以下の耐圧を持つツェナーダイオード５ａ、５ｂを逆並列に備えている Next, a semiconductor relay device according to a sixth embodiment of the present invention will be described with reference to FIG. In the present embodiment, Zener diodes 5a and 5b having a breakdown voltage equal to or lower than the breakdown voltage of the low breakdown voltage FETs 42 and 43 are provided in reverse parallel between the drain and source of the low breakdown voltage FETs 42 and 43.

本実施形態によれば、低耐圧ＦＥＴ４２、４３と逆並列にツェナーダイオード５ａ、５ｂを形成し、かつそのツェナーダイオード５ａ、５ｂが前記図６の高周波振動の振幅電圧Ｖ２以上であって、低耐圧ＦＥＴ４２、４３の耐圧以下のツェナー電圧を持つ。これにより、低耐圧ＦＥＴ４２、４３に過電圧が印加された場合に、低耐圧ＦＥＴ４２、４３をブレークダウンさせずにツェナーダイオード５ａ、５ｂがブレークダウンするために、過電圧による低耐圧ＦＥＴ４２、４３の破壊を防ぐことができる。 According to this embodiment, the Zener diodes 5a and 5b are formed in antiparallel with the low breakdown voltage FETs 42 and 43, and the Zener diodes 5a and 5b are equal to or higher than the amplitude voltage V2 of the high-frequency vibration shown in FIG. It has a Zener voltage below the breakdown voltage of the FETs 42 and 43. As a result, when an overvoltage is applied to the low breakdown voltage FETs 42 and 43, the Zener diodes 5a and 5b break down without breaking down the low breakdown voltage FETs 42 and 43. Can be prevented.

次に、本発明の第７の実施形態に係る半導体リレー装置について説明する。本実施形態は、前記第６の実施形態において、ツェナーダイオード５ａ、５ｂが低耐圧ＦＥＴ４２、４３と同一チップに形成され、かつ低耐圧ＦＥＴ４２、４３のゲート電極材料と同じポリシリコンで形成されているものである。 Next, a semiconductor relay device according to a seventh embodiment of the present invention will be described. In the present embodiment, in the sixth embodiment, the Zener diodes 5a and 5b are formed on the same chip as the low breakdown voltage FETs 42 and 43, and are formed of the same polysilicon as the gate electrode material of the low breakdown voltage FETs 42 and 43. Is.

本実施形態においては、ツェナーダイオード５ａ、５ｂは、低耐圧ＦＥＴ４２、４３と同一チップにて形成されるので、作製時に低耐圧ＦＥＴのゲート電極材料であるポリシリコンで同時に形成することができる。従って、ツェナーダイオード５ａ、５ｂの半導体製造プロセスの工程数を削減することができる。また、加工性の良いポリシリコンを材料に使用することにより、単結晶シリコンよりも高精度にツェナー電圧を決定できる。このため、ツェナーダイオード５ａ、５ｂを複数直列に接続して、高耐圧のツェナーダイオードアレイを精度良く形成することができる。これにより、ツェナーダイオードアレイの電圧を、高周波振動の振幅電圧以上で、かつ低耐圧ＦＥＴ４２、４３の耐圧以下に精度よく形成でき、低耐圧ＦＥＴ４２、４３の耐圧電圧を必要以上に大きくすることなく、低耐圧ＦＥＴ４２、４３の耐圧保護作用を得ることができる。 In the present embodiment, the Zener diodes 5a and 5b are formed on the same chip as the low breakdown voltage FETs 42 and 43, and therefore can be formed simultaneously with polysilicon, which is the gate electrode material of the low breakdown voltage FET. Therefore, the number of steps of the semiconductor manufacturing process of the Zener diodes 5a and 5b can be reduced. Further, by using polysilicon with good workability as the material, the Zener voltage can be determined with higher accuracy than single crystal silicon. For this reason, a plurality of Zener diodes 5a and 5b are connected in series, and a high voltage Zener diode array can be formed with high accuracy. Thereby, the voltage of the Zener diode array can be accurately formed to be equal to or higher than the amplitude voltage of the high-frequency vibration and lower than the breakdown voltage of the low breakdown voltage FETs 42 and 43, and without increasing the breakdown voltage of the low breakdown voltage FETs 42 and 43 more than necessary. The withstand voltage protecting action of the low withstand voltage FETs 42 and 43 can be obtained.

上述した各種実施形態に係る半導体リレー装置によれば、高耐圧用出力ＭＯＳＦＥＴと低耐圧用出力ＭＯＳＦＥＴの２組の出力部４ａ、４ｂを、各低耐圧用出力ＭＯＳＦＥＴ４２、４３の共通のソース端子に関して互いに対称に構成することにより、各高耐圧用出力ＭＯＳＦＥＴ４１、４４の各ドレインを外部端子４５ａ、４５ｂすることができ、外部端子４５ａ、４５ｂの双方向よりの高電圧を印加可能とし、安全性、利便性が向上すると共に、複数の低容量の低耐圧用出力ＭＯＳＦＥＴ４２、４３の直列接続により外部端子間容量を小さくして高周波特性を向上することができる。これにより、低容量、高耐圧の特性を兼ね備え、かつ負荷の電位の高低に関係なく双方向の接続が可能な、高性能で、高い安全性と利便性の半導体リレー装置を得ることができる。 According to the semiconductor relay device according to the various embodiments described above, two sets of output portions 4a and 4b of the high breakdown voltage output MOSFET and the low breakdown voltage output MOSFET are connected to the common source terminal of each of the low breakdown voltage output MOSFETs 42 and 43. By constituting symmetrically, the drains of the high-breakdown-voltage output MOSFETs 41 and 44 can be external terminals 45a and 45b, and a high voltage can be applied in both directions of the external terminals 45a and 45b. The convenience is improved, and the high-frequency characteristics can be improved by reducing the capacitance between the external terminals by connecting a plurality of low-capacity low-breakdown-voltage output MOSFETs 42 and 43 in series. As a result, it is possible to obtain a high-performance, high safety and convenience semiconductor relay device that has characteristics of low capacity and high withstand voltage and can be connected bidirectionally regardless of the level of the load potential.

本発明の第１の実施形態に係る半導体リレー装置の回路構成図。The circuit block diagram of the semiconductor relay apparatus which concerns on the 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体リレー装置の回路構成図。The circuit block diagram of the semiconductor relay apparatus which concerns on the 2nd Embodiment of this invention. 上記装置における各出力用ＭＯＳＦＥＴのオン、オフの動作応答時間の相対的遅延関係を示す図。The figure which shows the relative delay relationship of the on-off operation response time of each output MOSFET in the said apparatus. （ａ）は、本発明の第３の実施形態に係る半導体リレー装置の回路構成図、（ｂ）は同装置における各出力用ＭＯＳＦＥＴのオン、オフの動作応答時間の相対的遅延関係を示す図。(A) is a circuit block diagram of the semiconductor relay apparatus which concerns on the 3rd Embodiment of this invention, (b) is a figure which shows the relative delay relationship of the on-off operation response time of each output MOSFET in the apparatus. . （ａ）は、本発明の第４の実施形態に係る半導体リレー装置の回路構成図、（ｂ）は同装置における各出力用ＭＯＳＦＥＴのオン、オフの動作応答時間の相対的遅延関係を示す図。(A) is a circuit block diagram of the semiconductor relay apparatus which concerns on the 4th Embodiment of this invention, (b) is a figure which shows the relative delay relationship of the on-off operation response time of each output MOSFET in the apparatus. . 高周波振動の振幅が重畳された負荷電圧の波形を示す図。The figure which shows the waveform of the load voltage on which the amplitude of the high frequency vibration was superimposed. 本発明の第６の実施形態に係る半導体リレー装置の回路構成図。The circuit block diagram of the semiconductor relay apparatus which concerns on the 6th Embodiment of this invention. 従来の半導体リレー装置の回路構成図。The circuit block diagram of the conventional semiconductor relay apparatus.

Explanation of symbols

１発光部
１１発光ダイオード（発光素子）
２受光部
３充放電制御回路（電圧制御部）
４出力部
４ａ、４ｂ第１、第２出力部
４１、４４高耐圧用出力ＭＯＳＦＥＴ
４２、４３低耐圧用出力ＭＯＳＦＥＴ
４５ａ、４５ｂ外部端子
４６ａ、４６ｂ、４８ａ、４８ｂダイオード
４７ａ、４７ｂ、４９ａ、４９ｂ抵抗
５ａ、５ｂツェナーダイオード DESCRIPTION OF SYMBOLS 1 Light emission part 11 Light emitting diode (light emitting element)
2 Light receiver 3 Charge / discharge control circuit (voltage controller)
4 Output unit 4a, 4b First and second output units 41, 44 High breakdown voltage output MOSFET
42, 43 Low breakdown voltage output MOSFET
45a, 45b External terminal 46a, 46b, 48a, 48b Diode 47a, 47b, 49a, 49b Resistor 5a, 5b Zener diode

Claims

An input unit provided with a light emitting element that outputs an optical signal in response to an input signal, a light receiving unit that receives the optical signal and generates a predetermined voltage, and a voltage control unit that controls switching of the output MOSFET using the predetermined voltage And a semiconductor relay device that opens and closes the output unit in response to the input signal, and an output unit having a pair of output MOSFETs connected in series to each other in common.
At least two sets of the light receiving unit, the voltage control unit, and the output unit, respectively,
The voltage control unit is formed by a charge / discharge control circuit, and a gate and a source of each output MOSFET are connected to a high potential side and a low potential side of the charge / discharge control circuit, respectively.
Each of the pair of output MOSFETs includes a high breakdown voltage output MOSFET and a low breakdown voltage output MOSFET,
A semiconductor relay device characterized in that the two output units are connected in series by connecting the drains of the low withstand voltage output MOSFETs, and the drain terminals of the high withstand voltage output MOSFETs are external terminals.

When the input signal is turned off, the operation response time of the low withstand voltage output MOSFET is delayed, and the operation response time of the high withstand voltage output MOSFET is increased, so that the falling speed of the low withstand voltage output MOSFET is increased. 2. The semiconductor relay device according to claim 1, wherein the output MOSFET is slower than a falling speed of the output MOSFET.

When the input signal is turned on, the operation response time of the low withstand voltage output MOSFET is shortened, and the operation response time of the high withstand voltage output MOSFET is slowed down so that the rising speed of the low withstand voltage output MOSFET is increased. 2. The semiconductor relay device according to claim 1, wherein the semiconductor relay device is faster than a rising speed of the MOSFET.

When the input signal is turned off, the operation response time of the low withstand voltage output MOSFET is delayed, and the operation response time of the high withstand voltage output MOSFET is increased, so that the falling speed of the low withstand voltage output MOSFET is increased. The low withstand voltage is reduced by lowering the falling speed of the output MOSFET, and when the input signal is turned on, the operation response time of the low withstand voltage output MOSFET is shortened and the operation response time of the high withstand voltage output MOSFET is delayed. 2. The semiconductor relay device according to claim 1, wherein a rising speed of the output MOSFET is set higher than a rising speed of the high breakdown voltage output MOSFET.

A diode and a resistor are connected in parallel between the gate of each low withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit, and the cathode of the diode is connected to the gate of each low withstand voltage output MOSFET. The semiconductor relay device according to claim 2, wherein the semiconductor relay device is provided.

A diode and a resistor are connected in parallel between the gate of each high withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit, and the anode of the diode is connected to the gate of each high withstand voltage output MOSFET. The semiconductor relay device according to claim 3, wherein the semiconductor relay device is provided.

A diode and a resistor are connected in parallel between the gate of each low withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit, and the cathode of the diode is the gate of each low withstand voltage output MOSFET. And a diode and a resistor are connected in parallel between the gate of each high withstand voltage output MOSFET and the high voltage side of each charge / discharge control circuit, and the anode of the diode is connected to each high withstand voltage The semiconductor relay device according to claim 4, wherein the semiconductor relay device is connected to a gate of the output MOSFET.

The load voltage connected to the external terminal fluctuates at a high frequency at a predetermined voltage Va or higher, the lowest potential of the high-frequency fluctuation is the predetermined voltage Va, and the highest potential is a voltage lower than the voltage Va. 8. The semiconductor relay according to claim 1, wherein when the voltage is Vb plus voltage (Va + Vb), the low withstand voltage output MOSFET of the output section has a withstand voltage equal to or higher than the voltage Vb. apparatus.

9. The semiconductor relay device according to claim 8, wherein a Zener diode having a withstand voltage equal to or lower than the withstand voltage of the low withstand voltage output MOSFET is provided in reverse parallel between the drain and source of the low withstand voltage output MOSFET.

10. The semiconductor relay according to claim 9, wherein the Zener diode is formed on the same chip as the low breakdown voltage output MOSFET and is formed of the same polysilicon as a gate electrode material of the low breakdown voltage output MOSFET. apparatus.