CN101515569A - Integrated circuit die structure and manufacture method thereof - Google Patents
Integrated circuit die structure and manufacture method thereof Download PDFInfo
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- CN101515569A CN101515569A CNA2008100072324A CN200810007232A CN101515569A CN 101515569 A CN101515569 A CN 101515569A CN A2008100072324 A CNA2008100072324 A CN A2008100072324A CN 200810007232 A CN200810007232 A CN 200810007232A CN 101515569 A CN101515569 A CN 101515569A
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- polysilicon layer
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Abstract
The invention provides an integrated circuit die structure and a manufacture method thereof. The manufacture method comprises the following steps: 1, depositing a first polysilicon layer and a second plysilicon layer on a substrate; 2, coating photo resist on the second polysilicon layer and/or the first polysilicon layer and etching the photo resist; 3, etching the first polysilicon layer and the second plysilicon layer, and removing the photo resist, partial first polysilicon layer and partial second polysilicon layer; 4, depositing an SIN pad, performing etching in a large area on the SIN pad, and making the pad minimum along polysilicon residue; and 5, oxidizing the plysilicon residue. The method has the advantage that the method increases a step of depositing the SIN pad to treat the polysilicon residue, so the oxidized polysilicon residue cannot generate adverse influence on subsequent processes.
Description
Technical field
The present invention relates to the semiconductor fabrication process technical field, particularly a kind of integrated circuit die structure and manufacture method thereof.
Background technology
At present, in semi-conductive manufacturing process, the etching meeting of flash memory and nonvolatile memory (NVM) unit produces the residual polycrystalline silicon thing, and the residual polycrystalline silicon thing makes element failure above-mentioned in might or wiping process in programming.Secondly, because technological reason is difficult to shift out residue by etching process.
Summary of the invention
In view of above-mentioned, the object of the present invention is to provide a kind of novel method, adopt the SiN liner, then carry out oxidation step, residual polysilicon is carried out oxidation, make the wafer of integrated circuit.
The invention provides a kind of manufacture method of integrated circuit die structure, may further comprise the steps:
Step 1, deposition first polysilicon layer and second polysilicon layer in substrate;
Step 2 applies photoresistance and photoresistance is carried out etching on second polysilicon layer and/or first polysilicon layer;
Step 3 is carried out etching to first polysilicon layer and second polysilicon layer, removes photoresistance, part first polysilicon layer and part second polysilicon layer;
Step 4, deposition SIN liner then carries out the large tracts of land etching to the SIN liner, only is coated with side clearance walls in the side of floating grid and control grid, selection grid, residual polycrystalline silicon;
Step 5 is carried out oxidation to residual polycrystalline silicon.
As preferably, has shallow slot isolation structure in the above-mentioned substrate.
As preferably, above-mentioned first polysilicon layer covers above-mentioned second polysilicon layer, has oxide-nitride-oxide layer between first polysilicon layer and second polysilicon layer.
As preferably, in the step 1, at first in substrate, deposit one deck tunnel oxidation layer.
The present invention also provides a kind of integrated circuit die structure, comprise substrate, has shallow slot isolation structure in the above-mentioned substrate, deposit one deck tunnel oxidation layer in the substrate, on tunnel oxidation layer, deposit the floating grid and the control grid that constitute jointly by first polysilicon layer and second polysilicon layer, the selection grid that constitutes by second polysilicon layer, between floating grid and control gate and the selection grid residual polycrystalline silicon is arranged, floating grid and control grid, select grid, the residual polycrystalline silicon side is coated with side clearance walls, floating grid and control grid, select grid, the residual polycrystalline silicon surface-coated has sull.
As preferably, the material of above-mentioned side clearance walls is SIN.
Beneficial effect of the present invention is, by this method, increased the step of a deposition SIN liner, the residual polycrystalline silicon thing is handled, it can not had a negative impact to follow-up process after oxidation, particularly can not influence control grid and the tunnel oxidation layer of selecting the grid below.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.For the person of ordinary skill in the field, from detailed description of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.
Description of drawings
Fig. 1 is the vertical view of the nonvolatile memory of a preferred embodiment of the present invention.
Fig. 2 is the sectional view that deposits multicrystal substrate of a preferred embodiment of the present invention;
Fig. 3 is the sectional view of substrate behind the deposition of a preferred embodiment of the present invention and the etching photoresistance;
The sectional view of substrate behind etching photoresistance of Fig. 4 a preferred embodiment of the present invention and the polysilicon;
The sectional view of substrate behind the deposition SiN liner of Fig. 5 a preferred embodiment of the present invention;
The sectional view of substrate behind the deposition SiN liner of Fig. 6 a preferred embodiment of the present invention;
The sectional view of the substrate behind oxidation process of Fig. 7 a preferred embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments a kind of integrated circuit die structure of the present invention and manufacture method thereof are described in further detail.
As shown in Figure 1, nonvolatile memory or flash cell are in manufacture process, and source electrode and grid are middle if the residue of polysilicon then is easy to make A-B or B-C to lose efficacy, or produce the leakage of control grid to source electrode.Therefore, need make improvements.
Shown in Fig. 2-7, the SIN liner that adopts in oxidation process of expression a preferred embodiment of the present invention is made the method for wafer.
As shown in Figure 2, semiconductor substrate 11 at first is provided, deposit first polysilicon layer 13 and second polysilicon layer 14 in the substrate 11, the thickness of first polysilicon layer 13 is greatly between 1000A-2000A, the thickness of second polysilicon layer 14 is greatly between 1500A-2000A, above-mentioned first polysilicon layer is as floating grid (floating gate), above-mentioned second polysilicon layer is with the grid that elects (select gate) and control grid (controlgate), has shallow slot isolation structure (sti structure) 12 in the substrate 11, the area of second polysilicon layer 14 is greater than first polysilicon layer 13, and cover first polysilicon layer 13 fully, has oxide-nitride thing-oxide (ONO) layer 22 between first polysilicon layer 13 and second polysilicon layer 14, be used to separate first polysilicon layer 13 and second polysilicon layer 14, in substrate 11, also deposit one deck tunnel oxidation layer 21, certainly, substrate of the present invention can also have multiple shape and arrangement, is not limited to above-mentioned.
As shown in Figure 3, apply photoresistance 15 and photoresistance 15 is carried out etching on second polysilicon layer 14, between 4000A～5000A, after the etching, the photoresistance that only is used as the part of grid is retained on second polysilicon layer 14 thickness of the photoresistance of coating greatly.
As shown in Figure 4, first polysilicon layer 13 and second polysilicon layer 14 are carried out etching, remove photoresistance, part first polysilicon layer and part second polysilicon layer, only residue is as the part of selecting grid 24, floating grid 23 and control grid 25, wherein floating grid 23 is positioned at and selects the grid below, by oxide-nitride-oxide layer 22 at interval.Selecting between grid 24 and floating grid 23 and the control grid 25, also has residual polycrystalline silicon 15, this residual polycrystalline silicon 15 is residual by first polysilicon layer, second polysilicon layer is residual and oxide-nitride-oxide layer between it residual composition, can not produce fully because of etching.First polysilicon layer is residual can to cause wafer to lose efficacy because of the unit bridges between the unit bridges between the AB unit (cell bridge) or BC, the AD unit, second polysilicon layer is residual can be caused controlling grid and leak to producing between the source electrode to control grid bridge, control grid.
As shown in Figure 5, deposition SIN liner 17 in substrate 11, the thickness of this liner is greatly between 100A-300A, the purpose that deposits this liner is that it can passivation floating grid 23 and select tunnel oxidation layer 21 between the grid 24 and floating grid 23 and the oxide-nitride-oxide layer of controlling between the grid 25 22.
As shown in Figure 6, SIN liner 17 is carried out large tracts of land etching (blanket etch), etch depth is a predetermined value, etched purpose is to etch into one and determines the degree of depth, etch away the SIN liner on substrate top layer, only residue has the SIN liner on grid and residual polycrystalline silicon next door, forms the SIN side clearance walls, and this SIN side clearance walls exposes the part residual polycrystalline silicon along residual polycrystalline silicon 15 minimums.
As shown in Figure 7, residual polycrystalline silicon 15 is carried out oxidation processes (oxidation), along with the process that residual polycrystalline silicon 15 is carried out oxidation, wherein this process can be a wet oxidation, rapid thermal oxidation (RTO) etc., the oxidation residual polycrystalline silicon, and can not influence the oxidation of selecting grid 24, control grid 25, also can not influence the thickness and the quality of oxide-nitride-oxide layer 22.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; If do not break away from the spirit and scope of the present invention, the present invention is made amendment or is equal to replacement, all should be encompassed in the middle of the protection range of claim of the present invention.
Claims (6)
1, a kind of manufacture method of integrated circuit die structure is characterized in that may further comprise the steps:
Step 1, deposition first polysilicon layer and second polysilicon layer in substrate;
Step 2 applies photoresistance and photoresistance is carried out etching on second polysilicon layer and/or first polysilicon layer;
Step 3 is carried out etching to first polysilicon layer and second polysilicon layer, removes photoresistance, part first polysilicon layer and part second polysilicon layer;
Step 4, deposition SIN liner then carries out the large tracts of land etching to the SIN liner, only is coated with side clearance walls in the side of floating grid and control grid, selection grid, residual polycrystalline silicon;
Step 5 is carried out oxidation to residual polycrystalline silicon.
2, the manufacture method of integrated circuit die structure according to claim 1 is characterized in that, has shallow slot isolation structure in the above-mentioned substrate.
3, the manufacture method of integrated circuit die structure according to claim 1 is characterized in that, above-mentioned first polysilicon layer covers above-mentioned second polysilicon layer, has oxide-nitride-oxide layer between first polysilicon layer and second polysilicon layer.
4, the manufacture method of integrated circuit die structure according to claim 1 is characterized in that, in the step 1, at first deposits one deck tunnel oxidation layer in substrate.
5, a kind of integrated circuit die structure, it is characterized in that comprising substrate, has shallow slot isolation structure in the above-mentioned substrate, deposit one deck tunnel oxidation layer in the substrate, on tunnel oxidation layer, deposit the floating grid and the control grid that constitute jointly by first polysilicon layer and second polysilicon layer, the selection grid that constitutes by second polysilicon layer, between floating grid and control gate and the selection grid residual polycrystalline silicon is arranged, floating grid and control grid, select grid, the residual polycrystalline silicon side is coated with side clearance walls, floating grid and control grid, select grid, the residual polycrystalline silicon surface-coated has sull.
6, integrated circuit die structure according to claim 5 is characterized in that, the material of above-mentioned side clearance walls is SIN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100072324A CN101515569B (en) | 2008-02-19 | 2008-02-19 | Integrated circuit die structure and manufacture method thereof |
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| CN2008100072324A CN101515569B (en) | 2008-02-19 | 2008-02-19 | Integrated circuit die structure and manufacture method thereof |
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| CN101515569A true CN101515569A (en) | 2009-08-26 |
| CN101515569B CN101515569B (en) | 2011-08-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108269739A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | The forming method of polysilicon gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0783066B2 (en) * | 1989-08-11 | 1995-09-06 | 株式会社東芝 | Method for manufacturing semiconductor device |
| CN1133215C (en) * | 1998-06-24 | 2003-12-31 | 台湾积体电路制造股份有限公司 | Read-only memory and its manufacture |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108269739A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | The forming method of polysilicon gate |
| CN108269739B (en) * | 2016-12-30 | 2021-06-04 | 无锡华润上华科技有限公司 | Method for forming polysilicon grid |
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| CN101515569B (en) | 2011-08-03 |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |
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