CN101515310B - Random verifying method and system of microprocessor floating point unit - Google Patents
Random verifying method and system of microprocessor floating point unit Download PDFInfo
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Abstract
The invention relates to a random verifying method and system of a microprocessor floating point unit. The method includes the followings: step one, constraint rules in an instruction template are configured; step two, initialization is carried out for a floating point pool according to the constraint rules, and floating point pool mapping is initialized in a memory; step three, floating point operating instructions are generated, and operand is selected from the floating point pool; step four, the implementation of the floating point operating instructions is simulated; step five, a microprocessor to be verified obtains corresponding mapping of the selected operand from the floating point pool mapping, and the floating point unit of the microprocessor to be verified carries out the floating point operating instructions; compared with the action result and stimulation result, if both two are not matched, the floating point unit of the microprocessor unit to be verified has defects. The invention can control the numerical value of a register participating operation in instruction sequence in instruction level random verification, thereby improving verification efficiency.
Description
Technical field
The present invention relates to the computer unit verification technique, relate in particular to the random verification method and the system of microprocessor floating point unit.
Background technology
Simplation verification is the major technique in the current processor checking, though formalization method can provide the correctness proof of identifying object, owing to the existence of a series of problems such as state explosion is difficult to be applied in the middle of the large-scale Design Verification of Integrated Circuit.Floating point unit is the important component part of microprocessor, and since its huge space to be verified, singularity such as complicated operation, and its design verification all the time all is the focus of paying close attention to.With 32 floating adds in the MIPS compatible processor is example, and the span of two operands can be 0x00000000-0xFFFFFFFF, and the possible various combination number of operand of input test instruction has reached 264, wherein has various border condition simultaneously.The generation method of current main test procedure comprises that the instruction grade stochastic test produces, hand-written test vector and application program encapsulation etc.Huge just because of the composite of operand of floating-point checking, adopting constraint automatically to generate at random is the method for comparison nature.
But, for the processor checking, what the constraint by instruction-level generated generation at random is the instruction sequence of appointment, sends into as input then and goes in the design to be verified to carry out, and the result of its execution result and reference model is compared to judge design correctness.So the state of implementation is to be decided by initial machine state (comprising register and internal storage location) and whole instruction sequence.For the floating-point operation instruction of MIPS compatible processor, every is instructed required operand all in register, generally the flating point register number in the RISC machine is 32, in case after the original state of machine determined, the value in the register will be made amendment by performed instruction.If when controlling the value of operand of certain bar floating point instruction, can use this register to get final product then by the initial value of certain register is set as source-register.But, after all registers all have been used, just are difficult to control certain bar after this and have instructed the concrete operations number in the employed source-register.For common control module, may the numerical value in the register that participate in computing not had very special requirement, but for floating point unit, the performance level of its checking is closely-related with concrete numerical value.In addition, incomplete because of having lost the controlled checking that causes of the numerical value of participation computing for long cycle tests, it will be more serious can't covering situation such as corner state.
The verification method that current instruction grade stochastic verification technology is used for floating point unit has been described among Fig. 1, generally include 7 parts, instruction database 101, instruction template module 102, constraint solver 103, instruction generate engine 104, instruction-level simulator 105, instruction filter 106, simulated environment module 107.Comprise all floating point instructions that processor is supported in the instruction database 101; Generation to instruction in the instruction template module 102 is configured and standard; 103 pairs of instruction templates of constraint solver are found the solution, and teaching instruction generates engine 104 and generates corresponding instruction; Instruction-level simulator 105 is the simplest reference models of design to be verified, and current floating point unit simulator is only supported the fundamental norms of IEEE754 standard usually, and the specific requirement of MIPS compatible processor is lacked support; Can also comprise instruction in the instruction filter 106 and submit module to, judge whether it is illegal instruction according to the execution result of instruction-level simulator 105, whether decision will abandon this instruction, in time recovers the state of this instruction generation front processor simulator; Can also comprise Compare Logic in the simulated environment module 107, the operation simulated environment is to be wrapped in outer field a series of logics of design to be verified and operation, mainly comprises initialization, I/O and Compare Logic etc.
In addition, how accurately to judge efficiently whether the execution result of floating point unit is correctly most important equally for design verification.According to Fig. 1, the correctness that floating point unit is carried out is to compare by the result with the result of design to be verified and reference model to obtain, therefore reference model need accurately be simulated the implementation of floating-point, comprises the processing or the like of rounding mode, Exception Type and the unnomalized number of IEEE754 institute standard definition.Because reference model is abstract to what design, complexity design to be verified relatively is lower, generally adopts senior language compilation such as C, particularly for functional verification, does not have the requirement of sequential.And the C language provides abundant system call to supply the simulation floating-point operation, can set rounding mode, judges Exception Type that floating-point operation causes or the like.But, because the IEEE754 standard is the explanation of standardization, does not relate to specific implementation, for given operand, the different system of its operation result can both obtain identical result, but has different implementation methods for rounding mode with the abnormality processing different system.For example, that stipulates in the IEEE754 standard has 5 kinds unusually, it is respectively V (invalid computing, Invalid Exception), Z (is removed zero, Division by Zero), O (overflow, OverflowException), U (underflow, Underflow Exception) and I (out of true, InexactException), and MIPS architecture handbook defined has 6 kinds unusually, increased E (be unrealized unusual, Unimplemented Exception), be mainly used in and abnormal operation number and FPU occur and can't handle some rightly and trigger as a result the time.
Because what verification environment adopted is the system of X86 architecture, therefore adopt the floating point unit implementation status of the impossible accurately simulation of the system call MIPS system of C language.In this case,, can only verify the operation result correctness for the floating point unit of non-X86 architecture processes device, insufficient for the checking of different rounding modes and abnormality mark setting.Just because of the difference of verification environment and design architecture to be verified, must redesign the instruction-level simulator of floating point unit, finish the execution that different rounding modes give an order, the accurate setting of abnormality mark, the processing of unnomalized number etc.
In sum, existing instruction grade stochastic verification technology is to have that it is circumscribed to the checking of floating point unit in the microprocessor.The instruction grade stochastic verification of floating point unit lacks the controllability to the span of floating-point operation number, can't specify the operation of the floating number in a certain scope of required checking in instruction template, has caused a large amount of corner cases to be difficult to cover;
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides the random verification method and the system of microprocessor floating point unit, can be in instruction grade stochastic verification participate in the numerical value in the register of computing in the steering order sequence, improve verification efficiency, and the floating point unit of MIPS system accurately simulated, fully to verify.
The random verification method of the microprocessor floating point unit that the invention discloses comprises:
Step 3 generates the floating-point operation instruction according to described constraint rule, and from described floating point pool the selection operation number;
Step 4 is simulated the implementation of described floating-point operation instruction;
Described step 3 also comprises:
The reflection that microprocessor to be verified is obtained selecteed operand correspondence in the described step 6 from described floating point pool mapping is further carried out described load instruction for described microprocessor to be verified.
Described step 21 further comprises:
Step 32, the address of calculating the correspondence reflection of operand in described floating point pool mapping of selecting, described address is as the memory access address of load instruction;
Step 33, load instruction is inserted into described floating-point operation instruction before.
Also comprise between described step 21 and the described step 4,
Step 41 is preserved the state of current machine;
When described step 5 instructs the described floating-point operation of illegal cancellation to instruct in floating-point operation, also comprise:
Step 42, cancellation load instructs, and recovers the state of the machine of described preservation.
Described step 5 also comprises:
Step 51, instruct when legal in described floating-point operation, write back described floating point pool if judge result with Simulation execution, whether described floating point pool satisfies described constraint rule, if satisfy, then from described floating point pool, select at random, selecteed operand is updated to the result of described Simulation execution and execution in step 52;
Step 52 is inserted the store instruction in described floating-point operation instruction back, and the address of videoing with the correspondence of the described operand that is updated in described floating point pool mapping is the memory address of store instruction;
Described step 6 also comprises, described microprocessor to be verified is submitted in described store instruction, and after described microprocessor floating point unit to be verified executed described floating-point operation instruction, described microprocessor to be verified was carried out described store instruction.
Described step 4 further is, according to the implementation of IEEE754 standard and the described floating-point operation instruction of MIPS architecture simulation.
Described step 4 further comprises:
Step 71, operand and operational code according to IEEE754 standard and the described floating-point operation instruction of MIPS architecture analysis relate to are provided with the floating-point control register;
Step 72 is carried out computing according to described floating-point operation instruction to described floating-point operation number, judges that whether computing is effective, calculates operation result;
Step 73, and identifies correspondence of carrying out in described floating-point control register unusually that causes in the described operation of rounding off the operation result operation of rounding off according to the control information in the floating-point control register.
The accidental validation system of the microprocessor floating point unit that the invention also discloses, comprise that instruction database, instruction template module, constraint solver, instruction generate engine, instruction-level simulator, comprise the simulated environment module that instruction is submitted the instruction filter of module to, comprised Compare Logic, described system also comprises the floating point pool module that is used to store as the floating point pool in operand source, described simulated environment module also comprises the internal memory initialization module
Described instruction template module, be used for according to instruction database floating-point operation instruction type configuration-direct template, described instruction template comprises floating-point operation instruction type and the probability of occurrence thereof that is used for the standard generation, floating-point operation number of instructions, and the constraint rule of the type of floating-point operation number and its probability of occurrence;
Described constraint solver is used for by described constraint rule the floating point pool of floating point pool module being carried out initialization;
Described instruction generates engine, be used for generating the floating-point operation instruction according to described constraint rule, and from described floating point pool the selection operation number;
Described instruction-level simulator is used to simulate the implementation of described floating-point operation instruction;
Described instruction filter, be used for judging according to the execution result of described instruction-level simulator whether described floating-point operation instruction is legal, if it is legal, then by described instruction submit to module with described floating-point operation instruct, the execution result and the described operand of described instruction-level simulator submit to described simulated environment module in the address that the correspondence of described floating point pool mapping is videoed, if illegal, then with described floating-point operation instruction cancellation;
Described internal memory initialization module is used for using the initialization value initialization internal memory floating point pool mapping of described floating point pool;
Described simulated environment module, also be used for after receiving the information that described instruction filter submits to described information stores to microprocessor to be verified, so that microprocessor to be verified is obtained the reflection of selecteed operand correspondence by the address of described operand corresponding reflection in described floating point pool mapping from described floating point pool mapping, the floating point unit of described microprocessor to be verified is that operand is carried out described floating-point operation instruction with described reflection;
Described Compare Logic is used for the execution result of floating point unit of more described microprocessor to be verified and the execution result of described instruction-level simulator, if both do not match, determines that then there is defective in the floating point unit of described microprocessor to be verified; If the bar number that both couplings and the floating-point operation of having verified are instructed does not reach the floating-point operation number of instructions in the described constraint rule, then start described instruction and generate engine.
Described floating point pool module further comprises floating number memory module and writing module as a result,
Described floating number memory module is used to store the floating point pool as the operand source;
Described constraint solver is further used for trying to achieve by described constraint rule the floating point pool in the floating point pool module is carried out initialized initial value;
Described writing module as a result is used for described initial value is write described floating number memory module.
Described instruction generates engine and also be used for inserting the load instruction before the floating-point operation instruction, the memory access address of instructing as load with the address of the correspondence reflection of operand in described floating point pool mapping of described selection;
Described instruction filter is further used for submitting to module that described simulated environment module is submitted in described load instruction by described instruction when submitting to module that described operand is submitted to described simulated environment module in the address of the correspondence reflection of described floating point pool mapping by described instruction.
Described microprocessor to be verified is further used for carrying out described load instruction when obtaining the reflection of selecteed operand correspondence from described floating point pool mapping.
Described instruction generates the process that engine is further used for carrying out described generation floating-point operation instruction, and determines the quantity of described load instruction according to the quantity of the source-register of floating-point operation instruction; Indication floating point pool module selection operation number; And after receiving the address of the correspondence reflection of operand in described floating point pool mapping of the selection that the floating point pool module returns, the load instruction is inserted into described floating-point operation instruction before;
Described floating point pool module also comprises the address read module,
Described address read module is used for selecting to treat fetch operand at random from described floating point pool, and calculates the address of the correspondence reflection of operand in described floating point pool mapping of selecting, and described address is sent to described instruction generate engine.
Described instruction generates engine and also is used for after the insertion load instruction, preserving the state of current machine before described floating-point operation instruction;
Described instruction filter also is used for when floating-point operation instructs the described floating-point operation of illegal cancellation to instruct, and cancellation load instructs, and recovers the state of the machine of described preservation.
Described instruction filter also is used for instructing when legal in described floating-point operation, indicates described floating point pool module to upgrade operation;
Described floating point pool module is used to judge if the result of Simulation execution is write back described floating point pool when carrying out described renewal operation, whether described floating point pool satisfies described constraint rule, if satisfy, selection operation number at random from described floating point pool then, selecteed operand is updated to the result of described Simulation execution, and insert the store instruction in described floating-point operation instruction back, the address of videoing with the correspondence of the described operand that is updated in described floating point pool mapping is the memory address of store instruction;
Described instruction filter also is used for submitting to module that described simulated environment module is submitted in described store instruction by described instruction;
Described simulated environment module also is used for described microprocessor to be verified is submitted in described store instruction, so that described microprocessor to be verified is carried out described store instruction after the floating point unit of described microprocessor to be verified executes described floating-point operation instruction.
Described instruction-level simulator is further used for the implementation according to IEEE754 standard and the described floating-point operation instruction of MIPS architecture simulation.
Described instruction-level simulator further comprises abnormal operation number and illegal operation processing module, computing module, the result rounds off and abnormality mark is provided with module,
Described abnormal operation number and illegal operation processing module are used for the operand and the operational code that relate to according to the described floating-point operation instruction of IEEE754 standard and MIPS architecture analysis, and the floating-point control register is set;
Described computing module is used for according to described floating-point operation instruction described floating-point operation number being carried out computing, judges whether computing is effective, calculates the result, operation result is sent to the result rounds off and abnormality mark is provided with module;
Described result rounds off and abnormality mark is provided with module and is used for according to the control information of floating-point control register the operation result operation of rounding off, and correspondence of carrying out in described floating-point control register unusually that causes in the described operation of rounding off identified.
The random verification method of microprocessor floating point unit of the present invention and system, the floating number value constraint by increasing has improved verification efficiency, has quickened the checking convergence; According to IEEE754 floating-point standard, while is at the singularity of MIPS architecture, designed accurate floating point unit instruction-level simulator, accurately simulate execution, the accurate setting of abnormality mark and the processing of unnomalized number that the different rounding modes of MIPS handbook defined give an order, made checking work more abundant, perfect.
Description of drawings
Fig. 1 is the verification system structural drawing of prior art;
Fig. 2 is the process flow diagram of the random verification method of microprocessor floating point unit of the present invention;
Fig. 3 is the structural drawing of the accidental validation system of microprocessor floating point unit of the present invention;
Fig. 4 is that floating point pool module and instruction of the present invention generates the interactive relation figure that module is submitted in engine, constraint solver and instruction to;
Fig. 5 is the structural drawing of instruction-level simulator of the present invention;
Fig. 6 is that result of the present invention rounds off and abnormality mark is provided with the flowchart of module;
Fig. 7 is a floating-point control register form synoptic diagram in the MIPS architecture handbook.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
As shown in Figure 2, the random verification method of floating point unit in a kind of microprocessor may further comprise the steps:
Step S201, according to floating-point operation instruction type configuration-direct template in the instruction database, described instruction template comprises and is used for floating-point operation instruction type and the probability of occurrence thereof that standard generates, floating-point operation number of instructions, and the constraint rule of the type of floating-point operation number and all types of probability of occurrence.Also floating-point operation instruction type and the probability of occurrence thereof that promptly generates according to standard in the floating-point operation instruction type configuration-direct template in the instruction database, floating-point operation number of instructions, and the constraint rule of the type of floating-point operation number and probability of occurrence thereof.
Wherein, single precision and double-precision quantity probability proportion are 1: 1.
Floating-point operation is counted type and is comprised two kinds, the self-defined and User Defined of system.
The self-defining floating-point operation of system is counted type and is had 20 kinds, be respectively PNorm (the regular number of formatting), PSubNorm (positive unnomalized number), PZero (positive zero), POne (positive 1), PMaxNorm (the maximum regular number of formatting), PMinNorm (the minimum regular number of formatting), PInf (just infinite), PMaxSubNorm (maximum positive unnomalized number), PMinSubNorm (minimum positive unnomalized number), NNorm (negative standardizing number), NSubNorm (negative unnomalized number), NZero (negative zero), NOne (negative 1), NMaxNorm (maximum negative standardizing number), NMinNorm (minimal negative standardizing number), NInf (negative infinite), NMaxSubNorm (maximum negative unnomalized number), NMinSubNorm (minimal negative unnomalized number), QNan (static non-number), SNan (the non-number of reporting to the police).The user can be in instruction template designated order type and relative probability, for example " { PNorm 4; PZero 1} ", to count type be that the probability of PNorm is 4/5 in floating-point operation in the presentation directives, to count type be that the probability of PZero is 1/5 in floating-point operation in the instruction.The user can also oneself define the floating number scope as the floating-point operation number, and scope interval and relative probability are counted in floating-point operation in the designated order in instruction template, for example " { 0x3f800001 0,x3f,800,004 2; 0x4f0000000x5fbbbbbb 3} ", it is interval for the probability of 0x3f800001～0x3f800004 is 2/5 that scope is counted in floating-point operation in the presentation directives, and to count the scope interval be 3/5 for the probability of 0x4f000000～0x5fbbbbbb in floating-point operation in the instruction.
Step S202 carries out initialization by described constraint rule to the floating point pool of originating as operand, with floating point pool mapping in the initialization value initialization internal memory of described floating point pool.
Floating point pool is used to deposit the floating-point operation number that the user specifies number, as the operand source of all floating point instructions.Wherein the probability distribution of float satisfies the constraint rule in the instruction template.
Floating point pool mapping in the internal memory, operand source for microprocessor floating point unit to be verified, be consistent with the content of storing in the floating point pool, operand in the floating point pool mapping in the internal memory is corresponding one by one with the operand in the floating point pool, and the operand in the floating point pool mapping is the reflection of operand in its corresponding floating point pool.
Step S202 specific operation process calculates the absolute probability of each floating point type at first resolving the instruction template file, leaves in floating point type (floatType) table; Generate the initial value of floating point pool according to the probability of the floating point type of appointment in the floating point type table.The floating point type table is as follows.
| PNorm | 0.4 | Type1 | 0.2 |
| PZero | 0.1 | Type2 | 0.3 |
Step S203 generates the floating-point operation instruction according to constraint rule, and from described floating point pool the selection operation number.
The specific implementation method of selection operation number is, selection operation number at random from floating point pool.
Step S203 also comprises: increase a series of load instruction before every floating point instruction, so that be loaded in the source-register of this floating point instruction in the floating point pool mapping of correspondence reflection from internal memory of the operand that microprocessor to be verified will use in will simulating in floating point pool mapping.Simultaneously, preserve wherein each bar load instruction and carry out preceding machine state.Specific implementation method is as follows.
Step 231, the source-register and the destination register information of preserving the floating point instruction that generates.
Step 232, bar number according to the definite load instruction that should insert of the different source-register numbers of this floating point instruction, may be 1,2,3, in order to loading the action required number from floating point pool mapping, so the destination register of load instruction depends on the different source-registers number of the floating point instruction of preserving in the step 231.
Step 233, the address of calculating the correspondence reflection of operand in floating point pool mapping of selecting, this address is the memory access address of load instruction.
Computing method are according to start address and the operand of selection in floating point pool the corresponding item No. of floating point pool mapping in internal memory, the address of the correspondence reflection of calculating operation number in floating point pool mapping.
Step 234, load instruction is inserted into the floating-point operation instruction of generation before.
Step 235 after the load of Resources allocation instruction all generates, is recovered the floating point instruction that begins to preserve.
Step 236 is preserved current machine state successively.
This is because each bar for the load instruction that peek from floating point pool increases, all might be cancelled because of illegal floating point instruction thereafter and cancel, but owing to judges when floating point instruction is cancelled that the load instruction has caused modification to machine state.
Step S204 simulates the implementation of described floating-point operation instruction.
Accurately simulate the implementation of floating point instruction according to IEEE754 standard and MIPS architecture handbook, comprise execution, the accurate setting of abnormality mark and the processing of unnomalized number that different rounding modes give an order.
In the MIPS architecture handbook, the floating-point control register is FCR31, and its form as shown in Figure 7.
In Fig. 7, the bit0-bit1 position of this register is the rounding mode field, and IEEE has stipulated four kinds of rounding modes, is respectively RN, RZ, RP, RM, and the present invention can carry out floating-point operation under these four kinds of different patterns.
The bit2-bit6 of FCR31 register is the Flags field, what wherein deposit is the floating-point exception signs that all floating point instructions are carried out the accumulation that the back is provided with, and comprises that Invalid Exception (V), Divisionby Zero Exception (Z), Overflow Exception (O), Underflow Exception (U), five kinds of Inexact Exception (I) are unusual.The inventive method can also accurately be provided with corresponding sign wherein except calculating the result.
The bit7-bit11 of FCR31 register is the Enables field, can be provided with by the user, in order to shield the generation that different floating-points are absorbed in.What regulation can shield has five kinds unusually, is respectively V, Z, O, U, I, is non-maskable unusually but Unimplemented is Exception (E).The user can freely adjust unusual that design is allowed by this field is set when carrying out, making can be enough abundant for the checking of different floating-point exceptions.
The bit12-bit17 of FCR31 register is the Cause field, and what wherein deposit is last complete caused afterwards unusual of floating point instruction.The sign that can be provided with comprises six kinds of UnimplementedException (E), Invalid Exception (V), Division by Zero Exception (Z), Overflow Exception (O), Underflow Exception (U), Inexact Exception (I).The present invention need simulate accurately to the set abnormality mark of the execution of every floating point instruction, and the Causes field among the result who in step S207 the result of Simulation execution and microprocessor floating point unit to be verified is carried out compares, and judges whether the execution of design is correct.
Operation result for unnormalized, the IEEE754 regulation is not as long as satisfy the condition of UnderflowException (U), be abnormality mark not to be set, but stipulate according to the MIPS handbook, for coarse unnormalized result, if allow Underflow Exception (U) and InexactException (I) to be absorbed in or the zero clearing of FS position, Unimplemented Exception (E) sign will be set.And for the source operand of unnormalized, if not comparison order, design specifications of the present invention is same to require to be provided with Unimplemented Exception (E) sign.
The specific implementation process is as follows:
Step 241 is analyzed the operand and the operational code that participate in floating-point operation, and corresponding abnormality mark among the FCR31 is set, and comprises Unimplemented Exception (E), InvalidException (V), Division by Zero (Z);
Step 242, difference according to floating point instruction, send into different modules and carry out computing, have respectively add, subtraction block, multiplication and division method module is taken advantage of to add, take advantage of subtraction block, and evolution and evolution are asked the reverse mould piece, type conversion module and floating-point comparison module, and judge the validity of floating-point operation and the result of computations computing.
Step 243, read in the intermediate operations result of each module, according to the corresponding control information among the FCR31, comprise the operation of rounding off of FS, rounding mode and Enables field, simultaneously the abnormality mark that may cause in this operating process is provided with, comprises the Enables of FCR31 and the corresponding positions in the Flags field.
Step S205 judges according to the execution result of simulation whether described floating-point operation instruction is legal, if legal, then if execution in step S206 illegal, then cancels described floating-point operation instruction, cancels the load instruction simultaneously, recovers the machine state of preserving before this.
Step S205 concrete operation method is as follows.
Step 251 judges whether floating point instruction will be cancelled, if then do not submit the modification to system state to.
Load instruction before the step 252, this floating point instruction that is cancelled was if in the past submitted, and this moment is with its cancellation.
Step 253, because the submission of load instruction is revised machine state, the machine state that will recover to preserve before this this moment is popped the machine state that is kept in the stack successively.
Step S206, write back described floating point pool if judge result with Simulation execution, whether described floating point pool satisfies described constraint rule, if satisfy, then from described floating point pool, select at random, the selecteed fetch operand for the treatment of is updated to the result of described Simulation execution, and inserts the store instruction in floating-point operation instruction back, the address of videoing with the correspondence of operand in floating point pool mapping that is updated is the memory address of store instruction.
The execution result of floating-point operation instruction is write the flating point register heap, comprise add, subtract, multiplication and division, take advantage of add, take advantage of subtract, instructions such as evolution, type conversion; The all floating-point exceptions that produce in the implementation of floating-point operation instruction will write Flags and the Causes field of FCR31, and the while, tests for later conditional branch instruction the C position that the result writes FCR31 for the floating-point comparison order.
Step S207, microprocessor to be verified is obtained the reflection of selecteed operand correspondence by the address of operand corresponding reflection in floating point pool mapping from floating point pool mapping, the floating point unit of microprocessor to be verified is that operand is carried out the floating-point operation instruction with this reflection; The execution result of more described microprocessor floating point unit to be verified and the execution result of simulation if both do not match, determine that then there is defective in described microprocessor floating point unit to be verified; If the bar number that both couplings and the floating-point operation of having verified are instructed does not reach the floating-point operation number of instructions in the described constraint rule, then execution in step S203.
Microprocessor to be verified obtains operand by carrying out the load instruction; Instruct synchronous floating point pool to upgrade floating point pool mapping by carrying out store.
The accidental validation system of floating point unit as shown in Figure 3 in a kind of microprocessor.
Wherein, comprise two kinds of the self-defining and user's appointment of system.
The self-defining floating-point operation of system is counted type and is had 20 kinds, be respectively PNorm (the regular number of formatting), PSubNorm (positive unnomalized number), PZero (positive zero), POne (positive 1), PMaxNorm (the maximum regular number of formatting), PMinNorm (the minimum regular number of formatting), PInf (just infinite), PMaxSubNorm (maximum positive unnomalized number), PMinSubNorm (minimum positive unnomalized number), NNorm (negative standardizing number), NSubNorm (negative unnomalized number), NZero (negative zero), NOne (negative 1), NMaxNorm (maximum negative standardizing number), NMinNorm (minimal negative standardizing number), NInf (negative infinite), NMaxSubNorm (maximum negative unnomalized number), NMinSubNorm (minimal negative unnomalized number), QNan (static non-number), SNan (the non-number of reporting to the police).The user is designated order type and relative probability in instruction template, and for example " { PNorm 4; PZero 1} ";
The user can also oneself define the floating number scope as the floating-point operation number, designated order scope interval and relative probability in instruction template, for example " { 0x3f800001 0,x3f,800,004 2; 0x4f0000000x5fbbbbbb 3} ".
Constraint solver 302 is used to resolve the instruction template file, determines the absolute probability of various floating point types and generates initial distribution, and the floating point pool in the floating point pool module 303 is carried out initialization.
Constraint solver 302 is at first resolved the instruction template file, calculates the absolute probability of each floating point type, leaves in floating point type (floatType) table as shown in Figure 7.Constraint solver 302 generates the initial value of floating point pool according to the probability of the floating point type of appointment in the floating point type table.
Floating point pool module 303 is used to deposit the floating number that the user specifies number, as the operand source of all floating point instructions.
Whole floating numbers that the initializes that floating point pool module 303 is tried to achieve according to constraint solver 302 is wherein deposited.
Floating point pool module 303 and instructions generate the mutual situation of the instruction submission module 361 of engine 3 04, constraint solver 302 and instruction filtering module 306, as shown in Figure 4.
Floating point pool module 303 comprises: have 256 floating number memory module 331, and address read module 332, writing module 333 as a result.
The initial value of floating number memory module 331 is tried to achieve according to the constraint rule of instruction template by constraint solver 303, and the initial value of floating number memory module 331 is set by writing module 333 as a result.
Generate engine 3 04 for instruction, when producing a floating point instruction, need be from floating number memory module 331 at random fetch operand carry out computing.At this moment, by the address of reflection in internal storage location of address read module 332 these operands of acquisition correspondence in floating point pool mapping, the source operand that instructs as the load that inserts returns to instruction generation engine 3 04.
When a floating point instruction is performed the back by 361 submissions of instruction submission module, need dynamically update floating number memory module 331, if the result of computing puts into the probability distribution that floating point pool can satisfy the instruction template appointment, then upgrade in the floating number memory module 331 one randomly by writing module 333 as a result, and insert the store instruction in described floating-point operation instruction back, the address of videoing with the correspondence of operand in floating point pool mapping that is updated is the memory address of store instruction.
Instruction generates engine 3 04, be used to generate the floating-point operation instruction, and from floating point pool, obtain operand, and before every floating point instruction, increase a series of load instruction, be used for and will specify numerical value from the floating point pool mapping of internal memory, to be loaded in the source-register of this floating point instruction.Preserve wherein each bar load instruction simultaneously successively and carry out preceding machine state.
Source-register and destination register information that constraint solver 302 is preserved the floating point instruction that generates.
Instruction generates the bar number (may be 1,2,3) of engine 3 04 according to the definite load instruction that should insert of the different source-register numbers of this floating point instruction, in order to loading the action required number from floating point pool, so the destination register of load instruction depends on the different source-registers number of the floating point instruction of preserving in the constraint solver 302.The memory access address portion of load instruction obtains by the address read module 332 of floating point pool module 303.After the load of Resources allocation instruction all generates, recover the floating point instruction that begins to preserve.
The load instruction that each bar increases for peek from floating point pool, all might be because illegal floating point instruction thereafter is cancelled and cancels, but owing to judge when floating point instruction is cancelled, the load instruction has caused modification to machine state, therefore need preserve current machine state successively before carrying out this load instruction.
Instruction-level simulator 305 is accurately simulated the implementation of floating point instruction according to IEEE754 standard and MIPS handbook, and abnormality mark accurately is set.
Instruction-level simulator 305 dummy instructions generate the implementation of the instruction of engine 3 04 generation, for floating-point operation: the operand and the operational code that participate in floating-point operation are carried out tentatively analyzing, corresponding abnormality mark among the FCR31 is set, comprises Unimplemented Exception (E), InvalidException (V), Division by Zero (Z); According to the difference of floating point instruction, the disparate modules of sending in the computing module 352 carries out computing, and plus-minus method module 502 is arranged respectively, multiplication and division module 503, take advantage of to add and take advantage of subtraction block 504, evolution and evolution are asked reverse mould piece 505, type conversion module 506 and floating-point comparison module 507.Judge the validity of floating-point operation and the result of computations computing therein; Read in the intermediate operations result of each module, according to the corresponding control information among the FCR31, comprise the operation of rounding off of fields such as FS, rounding mode and Enables, simultaneously the abnormality mark that may cause in this operating process is provided with, comprises the Enables of FCR31 and the corresponding positions in the Flags field.
Instruction-level simulator 305 structures as shown in Figure 5.Instruction-level simulator 305 comprises abnormal operation number and illegal operation processing module 351, and computing module 352 and result round off and abnormality mark is provided with module 353.Computing module 352 comprises, FCR31 control register 501, and plus-minus method module 502, multiplication and division module 503 is taken advantage of to add and take advantage of subtraction block 504, and evolution and evolution are asked reverse mould piece 505, type conversion module 506, floating-point comparison module 507.
Abnormal operation number and illegal operation processing module 351 are used for the operand and the operational code that participate in floating-point operation are carried out tentatively judging, and the corresponding sign of FCR31 control register S402 are set.
Computing module 352 is used for according to described floating-point operation instruction described floating-point operation number being carried out computing, judges whether computing is effective, calculates the result, operation result is sent to the result rounds off and abnormality mark is provided with module 353.
The result rounds off and abnormality mark is provided with module 353, is used for according to the control information of floating-point control register the operation result operation of rounding off, and correspondence of carrying out in described floating-point control register unusually that causes in the described operation of rounding off identified.
When the operand that participates in floating-point operation and operational code are one of following certain situation, abnormal operation number and illegal operation processing module 351 will be provided with Unimplemented Exception (E) zone bit of FCR31:
Situation one, floating-point operation are not comparison orders, and arbitrary operand is a unnomalized number;
Situation two, floating-point operation are not comparison orders, and arbitrary operand is QNan;
Situation three illegally reaches unconsummated order format;
Situation four, the operational code of reservation.
Because this is that maskable is not unusual unusually, this sign is set up and must causes floating-point and be absorbed in, and transfers to exception handler and handles according to the IEEE754 standard.
When the arbitrary operand that participates in floating-point operation is SNan, abnormal operation number and illegal operation processing module 351 will be provided with Invalid Exception (V) zone bit of FCR31.
When the floating-point operation that participates in computing is that division and divisor are 0, when dividend is limited non-0 number, abnormal operation number and illegal operation processing module 351 will be provided with Division by ZeroException (Z) zone bit of FCR31.
Finish the plus and minus calculation of single, double precision and two single-precision number (pair single) in the plus-minus method module 502, if carried out in the calculating process being equivalent to (+∞)+(operation ∞), InvalidException (V) will be set, at last all intermediate operations results be given that the result rounds off and abnormality mark is provided with module 353.
Finish the multiplication and division computing of single, double precision and two single-precision numbers in the multiplication and division module 503, if 0 * ∞, 0/0 or the operation of ∞/∞ is arranged in the calculating process, Invalid Exception (V) will be set, at last all intermediate operations results be sent into that the result rounds off and abnormality mark is provided with module 353.
Take advantage of to add and take advantage of and finish taking advantage of of single, double precision and two single-precision numbers among the subtraction block S405 and add, take advantage of and subtract computing.All intermediate operations results send into that the result rounds off and abnormality mark is provided with module 353.
Evolution and evolution ask evolution and the evolution of finishing single, double precision and two single-precision numbers in the reverse mould piece 505 to ask computing reciprocal.If source operand is less than 0 in the calculating process, InvalidException (V) will be set, be easy to occur the situation that the operand figure place is lost in addition in the evolution process, Inexact Exception (I) will be set, at last all intermediate operations results be sent into that the result rounds off and abnormality mark is provided with module 353.
Finish mutual conversion, the conversion between the different floating-point format and floating number between floating-point and the integer number in the type conversion module 506 to operations such as rounding off of integer number.At last all intermediate operations results are sent into that the result rounds off and abnormality mark is provided with module 353.
Finish the floating-point compare operation of single, double precision and two single-precision numbers in the floating-point comparison module 507, operation result is directly sent into the C position of FCR31, the comparative result sign is set, the condition jump instruction test after being provided with is used.
The result rounds off and abnormality mark is provided with in the module 353, the result who sends into according to computing module 352, and the rounding mode that from FCR31, reads, the unusual information such as sign, FS that allow, to result's operation of rounding off, corresponding sign among the FCR31 is set simultaneously, and the sign that may be provided with has UnimplementedException (E), Invalid Exception (V), Overflow Exception (O), UnderflowException (U), Inexact Exception (I).
The execution flow process that the result rounds off and abnormality mark is provided with module 353 as shown in Figure 6.
Step S601 reads the control information among the FCR31 that is provided with in advance by the user, comprises rounding mode RM, FS and the value that allows field Enables unusually.
Step S602 according to the rounding mode of appointment, is provided with the value that should revise in the time of need rounding off operation to current results.
Whether can cause the result to surpass the maximum Finite Number scope that object format can represent after step S603, basis for estimation rounding mode round off to current results and cause overflow.At this moment, the Causes of FCR31 and Overflow Exception (O) position of Flags field will be set.
Step S604 because round-off result upwards overflows, will be provided with final operation result according to different rounding modes, and the operation result of this moment and the relation of rounding mode are provided by following table.
Step S605 judges whether operation result can cause Underflow Exception.
According to the IEE754 standard code, there are two kinds of situations can cause Underflow, be respectively Tininess and Loss of Accuracy, its concrete implication is as follows.
Tininess can round off preceding or round off and then judge that whether the value of operation result is ± 2 according to the IEEE754 standard
E minBetween come to determine, if then a minimum nonzero value has appearred in expression, may calculating process afterwards in exception throw.But MIPS architecture handbook is only required at the Tininess of back to the result that round off and is judged that this also is to the refinement of IEEE754 standard and specific implementation.
Loss of Accuracy can be detected under the situation of Denormalization Loss or Inexact Result according to the standard of IEEE754, but MIPS architecture handbook is only required the situation of just representing to have occurred Loss of Accuracy when satisfying Inexact Result.This is the specific implementation to the IEEE754 standard equally.
Therefore, for the MIPS compatible processor, value is ± 2 after intermediate results of operations rounds off
E minBetween, and UnderflowException (U) position of Causes and Flags field will be set when Inexact having occurred.
Step S606 has caused overflowing downwards owing to calculate, if allow Underflow and Inexact to be absorbed in (corresponding Enables set), perhaps the FS position is 0, and this moment, operation result was constant.If above-mentioned condition does not satisfy, the result of computing this moment will define according to the MIPS handbook and provide, and will be as shown in the table.
Step S607, caused Underflow Exception owing to calculate,, except Underflow Exception will be set also need according to Enables and fs field in the FCR31 that read Unimplemented Exception (E) field be set according to the regulation of MIPS handbook this moment.If allow Underflow and Inexact to be absorbed in, perhaps the FS position is 0, and Unimplemented Exception (E) position among Causes and the Flags is set this moment.
Step S608 is provided with Inexact Exception (I) position of FCR31, if rounding bit is non-0, then needs this zone bit is set, and illustrates that result calculated is compared on precision with the computation process of infinite range to lose.
Step S609 adds the modified value that obtains among the step S502 with former intermediate result, the result after finally being rounded off.
Instruction filter 306, according to the execution result of instruction-level simulator 305, if this floating-point operation instruction will be cancelled, this moment, a series of load instructions for its load operation number also will be cancelled, cancel the load instruction simultaneously to the modification that machine state causes, return to state before this.
Instruction filter 306 judges whether floating point instruction will be cancelled, and does not submit the modification of module submission to system state to if then do not send into instruction; Load instruction before this floating point instruction that is cancelled is in the past submitted, should cancel it this moment; Because the submission of load instruction is revised machine state, the machine state that will recover to preserve before this this moment is popped the machine state that is kept in the stack successively.
If the floating-point operation instruction is legal, be not cancelled, then instruction filter 306 also submits to module 361 that the simulated environment module is submitted in the instruction of all generations by described instruction; And indication floating point pool module 303 is upgraded.
Wherein will be according to the initial value initialization internal memory corresponding units of floating point pool.
Internal memory initialization module 371 is used for using the initialization value initialization simulated environment module memory floating point pool mapping of described floating point pool.
Microprocessor to be verified obtains operand by carrying out the load instruction from floating point pool mapping, the floating point unit of microprocessor to be verified is finished corresponding operating to the operand that obtains by carrying out the floating-point operation instruction from the load instruction, microprocessor to be verified instructs synchronous floating point pool that floating point pool mapping is upgraded by carrying out store.
Compare Logic 372 is used for the execution result of more described microprocessor floating point unit to be verified and the execution result of described instruction-level simulator, comprise the value of flating point register heap and the value of floating-point control register FCR31, if both do not match, determine that then there is defective in described microprocessor floating point unit to be verified.
Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determine by the scope of claims.
Claims (15)
1. the random verification method of a microprocessor floating point unit is characterized in that, comprising:
Step 1, according to floating-point operation instruction type configuration-direct template in the instruction database, described instruction template comprises the constraint rule of probability of occurrence of the type of the type that is used for floating-point operation instruction type that standard generates and probability of occurrence, floating-point operation number of instructions and floating-point operation instruction floating-point operation number and each described floating-point operation number;
Step 2 is carried out initialization by described constraint rule to the floating point pool of originating as operand, with floating point pool mapping in the initialization value initialization internal memory of described floating point pool;
Step 3 generates the floating-point operation instruction according to described constraint rule, and from described floating point pool the selection operation number;
Step 4 is simulated the implementation of described floating-point operation instruction;
Step 5 judges according to the execution result of described simulation whether described floating-point operation instruction is legal, if legal, then execution in step 6, if illegal, then cancels described floating-point operation instruction;
Step 6, microprocessor to be verified is obtained the reflection of selecteed operand correspondence by the address of described operand corresponding reflection in described floating point pool mapping from described floating point pool mapping, the floating point unit of described microprocessor to be verified is that operand is carried out described floating-point operation instruction with described reflection; The execution result of the floating point unit of more described microprocessor to be verified and the execution result of described simulation, if both do not match, there is defective in the floating point unit of then determining described microprocessor to be verified, if the bar number that both couplings and the floating-point operation of having verified are instructed does not reach the floating-point operation number of instructions in the described constraint rule, then execution in step 3.
2. the random verification method of microprocessor floating point unit as claimed in claim 1 is characterized in that,
Described step 3 also comprises:
Step 21 is inserted the load instruction before floating-point operation instruction, the memory access address of instructing as load with the address of the correspondence reflection of operand in described floating point pool mapping of described selection;
The reflection that microprocessor to be verified is obtained selecteed operand correspondence in the described step 6 from described floating point pool mapping is further carried out described load instruction for described microprocessor to be verified.
3. the random verification method of microprocessor floating point unit as claimed in claim 2 is characterized in that,
Described step 21 further comprises:
Step 31 is determined the quantity of described load instruction according to the quantity of the source-register of floating-point operation instruction;
Step 32, the address of calculating the correspondence reflection of operand in described floating point pool mapping of selecting, described address is as the memory access address of load instruction;
Step 33, load instruction is inserted into described floating-point operation instruction before.
4. the random verification method of microprocessor floating point unit as claimed in claim 3 is characterized in that, also comprise between described step 21 and the described step 4,
Step 41 is preserved the state of current machine;
When described step 5 instructs the described floating-point operation of illegal cancellation to instruct in floating-point operation, also comprise:
Step 42, cancellation load instructs, and recovers the state of the machine of described preservation.
5. the random verification method of microprocessor floating point unit as claimed in claim 1 is characterized in that,
Described step 5 also comprises:
Step 51, instruct when legal in described floating-point operation, write back described floating point pool if judge result with Simulation execution, whether described floating point pool satisfies described constraint rule, if satisfy, then from described floating point pool, select at random, selecteed operand is updated to the result of described Simulation execution and execution in step 52;
Step 52 is inserted the store instruction in described floating-point operation instruction back, and the address of videoing with the correspondence of the described operand that is updated in described floating point pool mapping is the memory address of store instruction;
Described step 6 also comprises, described microprocessor to be verified is submitted in described store instruction, and after described microprocessor floating point unit to be verified executed described floating-point operation instruction, described microprocessor to be verified was carried out described store instruction.
6. the random verification method of microprocessor floating point unit as claimed in claim 1 is characterized in that,
Described step 4 further is, according to the implementation of IEEE754 standard and the described floating-point operation instruction of MIPS architecture simulation.
7. the random verification method of microprocessor floating point unit as claimed in claim 6 is characterized in that,
Described step 4 further comprises:
Step 71, operand and operational code according to IEEE754 standard and the described floating-point operation instruction of MIPS architecture analysis relate to are provided with the floating-point control register;
Step 72 is carried out computing according to described floating-point operation instruction to described floating-point operation number, judges that whether computing is effective, calculates operation result;
Step 73, and identifies correspondence of carrying out in described floating-point control register unusually that causes in the described operation of rounding off the operation result operation of rounding off according to the control information in the floating-point control register.
8. the accidental validation system of a microprocessor floating point unit, comprise that instruction database, instruction template module, constraint solver, instruction generate engine, instruction-level simulator, comprise the simulated environment module that instruction is submitted the instruction filter of module to, comprised Compare Logic, it is characterized in that, described system also comprises the floating point pool module that is used to store as the floating point pool in operand source, described simulated environment module also comprises the internal memory initialization module
Described instruction template module, be used for according to instruction database floating-point operation instruction type configuration-direct template, described instruction template comprises the constraint rule of probability of occurrence of the type of the type that is used for floating-point operation instruction type that standard generates and probability of occurrence, floating-point operation number of instructions and floating-point operation instruction floating-point operation number and described floating-point operation number;
Described constraint solver is used for by described constraint rule the floating point pool of floating point pool module being carried out initialization;
Described internal memory initialization module is used for using the initialization value initialization internal memory floating point pool mapping of described floating point pool;
Described instruction generates engine, be used for generating the floating-point operation instruction according to described constraint rule, and from described floating point pool the selection operation number;
Described instruction-level simulator is used to simulate the implementation of described floating-point operation instruction;
Described instruction filter, be used for judging according to the execution result of described instruction-level simulator whether described floating-point operation instruction is legal, if it is legal, then by described instruction submit to module with described floating-point operation instruct, the execution result and the described operand of described instruction-level simulator submit to described simulated environment module in the address that the correspondence of described floating point pool mapping is videoed, if illegal, then with described floating-point operation instruction cancellation;
Described simulated environment module, also be used for after receiving the information that described instruction filter submits to described information stores to microprocessor to be verified, so that microprocessor to be verified is obtained the reflection of selecteed operand correspondence by the address of described operand corresponding reflection in described floating point pool mapping from described floating point pool mapping, the floating point unit of described microprocessor to be verified is that operand is carried out described floating-point operation instruction with described reflection;
Described Compare Logic is used for the execution result of floating point unit of more described microprocessor to be verified and the execution result of described instruction-level simulator, if both do not match, determines that then there is defective in the floating point unit of described microprocessor to be verified; If the bar number that both couplings and the floating-point operation of having verified are instructed does not reach the floating-point operation number of instructions in the described constraint rule, then start described instruction and generate engine.
9. the accidental validation system of microprocessor floating point unit as claimed in claim 8 is characterized in that,
Described floating point pool module further comprises floating number memory module and writing module as a result,
Described floating number memory module is used to store the floating point pool as the operand source;
Described constraint solver is further used for trying to achieve by described constraint rule the floating point pool in the floating point pool module is carried out initialized initial value;
Described writing module as a result is used for described initial value is write described floating number memory module.
10. the accidental validation system of microprocessor floating point unit as claimed in claim 9 is characterized in that,
Described instruction generates engine and also be used for inserting the load instruction before the floating-point operation instruction, the memory access address of instructing as load with the address of the correspondence reflection of operand in described floating point pool mapping of described selection;
Described instruction filter is further used for submitting to module that described simulated environment module is submitted in described load instruction by described instruction when submitting to module that described operand is submitted to described simulated environment module in the address of the correspondence reflection of described floating point pool mapping by described instruction;
Described microprocessor to be verified is further used for carrying out described load instruction when obtaining the reflection of selecteed operand correspondence from described floating point pool mapping.
11. the accidental validation system of microprocessor floating point unit as claimed in claim 10 is characterized in that,
Described instruction generates engine and be used for inserting the load instruction before the floating-point operation instruction, further comprises according to the quantity of the source-register of floating-point operation instruction as the memory access address of load instruction with the address of the correspondence reflection of operand in described floating point pool mapping of described selection and determines the quantity that described load instructs; Indication floating point pool module selection operation number; And after receiving the address of the correspondence reflection of operand in described floating point pool mapping of the selection that the floating point pool module returns, the load instruction is inserted into described floating-point operation instruction before;
Described floating point pool module also comprises the address read module,
Described address read module is used for selecting to treat fetch operand at random from described floating point pool, and calculates the address of the correspondence reflection of operand in described floating point pool mapping of selecting, and described address is sent to described instruction generate engine.
12. the accidental validation system of microprocessor floating point unit as claimed in claim 11 is characterized in that,
Described instruction generates engine and also is used for after the insertion load instruction, preserving the state of current machine before described floating-point operation instruction;
Described instruction filter also is used for when floating-point operation instructs the described floating-point operation of illegal cancellation to instruct, and cancellation load instructs, and recovers the state of the machine of described preservation.
13. the accidental validation system of microprocessor floating point unit as claimed in claim 8 is characterized in that,
Described instruction filter also is used for instructing when legal in described floating-point operation, indicates described floating point pool module to upgrade operation;
Described floating point pool module is used to judge if the result of Simulation execution is write back described floating point pool when carrying out described renewal operation, whether described floating point pool satisfies described constraint rule, if satisfy, selection operation number at random from described floating point pool then, selecteed operand is updated to the result of described Simulation execution, and insert the store instruction in described floating-point operation instruction back, the address of videoing with the correspondence of the described operand that is updated in described floating point pool mapping is the memory address of store instruction;
Described instruction filter also is used for submitting to module that described simulated environment module is submitted in described store instruction by described instruction;
Described simulated environment module also is used for described microprocessor to be verified is submitted in described store instruction, so that described microprocessor to be verified is carried out described store instruction after the floating point unit of described microprocessor to be verified executes described floating-point operation instruction.
14. the accidental validation system of microprocessor floating point unit as claimed in claim 8 is characterized in that,
Described instruction-level simulator is further used for the implementation according to IEEE754 standard and the described floating-point operation instruction of MIPS architecture simulation.
15. the accidental validation system of microprocessor floating point unit as claimed in claim 14 is characterized in that,
Described instruction-level simulator further comprises abnormal operation number and illegal operation processing module, computing module, the result rounds off and abnormality mark is provided with module,
Described abnormal operation number and illegal operation processing module are used for the operand and the operational code that relate to according to the described floating-point operation instruction of IEEE754 standard and MIPS architecture analysis, and the floating-point control register is set;
Described computing module is used for according to described floating-point operation instruction described floating-point operation number being carried out computing, judges whether computing is effective, calculates the result, operation result is sent to the result rounds off and abnormality mark is provided with module;
Described result rounds off and abnormality mark is provided with module and is used for according to the control information of floating-point control register the operation result operation of rounding off, and correspondence of carrying out in described floating-point control register unusually that causes in the described operation of rounding off identified.
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Assignee: Beijing Loongson Zhongke Technology Service Center Co., Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract fulfillment period: 2009.12.16 to 2028.12.31 Contract record no.: 2010990000062 Denomination of invention: Random verifying method and system of microprocessor floating point unit License type: exclusive license Record date: 20100128 |
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Application publication date: 20090826 Assignee: Longxin Zhongke Technology Co., Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: 2015990000066 Denomination of invention: Random verifying method and system of microprocessor floating point unit Granted publication date: 20101006 License type: Common License Record date: 20150211 |
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