CN101510584A - Multi-state phase-change memory unit element and preparation method - Google Patents
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Abstract
The invention provides a multi-level phase change memory unit device with remarkably resistance variation and a preparation method thereof. The multi-level phase change memory unit device comprises a bottom electrode layer, a heating electrode layer which is arranged on the surface of the bottom electrode layer and is a conductive material, a combinatorial layer arranged on the surface of the heating electrode layer, an up contact electrode layer on the surface of the combinatorial layer, and a top electrode layer on the surface of the up contact electrode layer. The combinatorial layer comprises a phase-change material area which spreads from the surface of the layer to the inside of the layer to form a first pyramidal shape and continues to spread from the bottom of the first pyramidal shape to the inside of the layer to form a second pyramidal shape, and an insulation material which is combined with the phase-change material area to form a layer structure, wherein the widths of the tops of the first pyramidal shape and the second pyramidal shape are both 0.01 time-0.03 time of that of the heating electrode layer. The preparation method comprises the following steps: firstly, a bottom electrode through hole is prepared on the substrate of a semi-conductor and conductive materials are deposited in the electrode through hole so as to form a metal embolism, then phase-change materials are deposited by sputtering and the surface is polished with chemical machinery, and finally the conductive materials are deposited to form the metal embolism.
Description
Technical field
The present invention relates to a kind of phase-change memory unit element and preparation method, particularly a kind of multi-state phase-change memory unit element and preparation method.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) conception of " phase-change thin film can be applied to the phase change memory medium " of Ti Chuing is set up.Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following memory main product and become the device of commercial product at first.Memory device as a kind of low price, stable performance, it can be made on the silicon wafer substrate, critical material is recordable phase-change thin film, heating electrode material, heat-insulating material and extraction electrode material, therefore, the focus of research also just launches around its device technology, comprise: how the physical mechanism research of device reduces device material etc.
The basic principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.For example, wipe operation (RESET): after the phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the fusion temperature, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET): when apply one long and pulse enable signal phase-change material temperature moderate strength is raised under the fusion temperature, on the crystallization temperature after, and keep a period of time to impel nucleus growth, thereby realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation after adding a very weak pulse signal that can not exert an influence to the state of phase-change material, is read its state by the resistance value of measuring element unit.Can realize read-write operation to phase transition storage etc. thus.
Mechanism's great majority of being engaged at present the phase transition storage R﹠D work in the world are major companies of semicon industry, and the focus that they pay close attention to all concentrates in the commercialization that realizes phase transition storage how as early as possible, and therefore corresponding operating current promptly reduces power consumption; Device architecture design and the research of storage mechanism etc.; The manufacturing process research of high-density device array, comprise the nanoscale problem that how to realize device cell, the technological problems of high-density device chip, the Problem of Failure of device cell etc., all become the emphasis of research, and wherein very crucial and the importantly reduction of device power consumption, because the phase transition process of phase transformation memory device unit finally will lean on the driving of the complementary oxide semiconductor tube of metal to realize, for realize with high density memory chips in the CMOS tube power be complementary the essential power consumption that reduces device.The method that reduces device power consumption has: the contact area that reduces electrode and phase-change material; Improve the resistance of phase-change material; Between electrode and phase-change material or the inner thermoresistance layer or the like that adds of phase-change material.But these methods are all not high enough on the efficiency of heating surface, can not finely satisfy the requirement of present device.According to bibliographical information, 85% heat is dissipated in phase transition storage, and 15% the heat of only having an appointment is used to phase transformation, and this is present phase transition storage low-power consumption, restraining factors at a high speed.And document reports that also the phase transition storage (PCRAM) of different structure has different RESET electric currents, and the utilance of heat has relation in RESET electric current and the structure, that is: the high structure of heat utilization ratio, and the RESET electric current is little.
Existing multi-state phase-change memory unit element core texture generally is made of phase-change material, insulating material, extraction electrode material etc., as shown in Figure 1, one multi-state phase-change memory unit element comprises: insulation material layer 5, bottom electrode 1, phase-change material layers (GST) 2, go up contact electrode layer 3, and upper electrode layer 4, wherein, insulation material layer 5 adopts SiO2, width is L1=1000nm, and thickness is h1=550nm; Bottom electrode 1 adopts the W material, and width is L1=130nm, and thickness is h1=550nm; Phase-change material layers 2 width are bigger more than 6 times than the width of bottom electrode 1, and its width is L1=1000nm, and thickness is h2=150nm; Last contact electrode layer 3 adopts the TiN material, and its thickness is h3=50nm, and width is L1=1000nm; Upper electrode layer (top) 4 adopts the W material, and its thickness is h4=500nm, and width is L1=1000nm.When described multi-state phase-change memory unit element is passed to the electric current of varying strength, phase-change material on the bottom electrode 1 passes through decrease temperature crystalline, make the crystal region of sealing bottom electrode fully change to some extent, the resistance value of the described multi-state phase-change memory unit element that this variation causes changes, and can realize polymorphic storage thus.And when current impulse is enough big, makes and can come whole fusions of phase-change material on the bottom electrode 1 the Control current pulse by dual mode then, thereby make described multi-state phase-change memory unit element be in different resistance states.For example, under the prerequisite of the amorphous of in the assurance cooling rate makes melt region inadequately, growing, reduce current impulse intensity, in this process, some temperature of phase-change material by big melted drops to below the melt temperature, and the beginning crystallization is shown in Fig. 2 a-2d.In addition, by regulating the slope that current impulse descends, it is the crystallization control time, can reach crystallization degree in the control melt region equally, and then control the resistance of described multi-state phase-change memory unit element, shown in Fig. 3 a-3b, the crystallization situation of decline 4mA at the 25ns place is the same in the crystallization situation in 300ns the 10ns of decline 4mA voltage condition time the and the 700ns.Therefore, when multi-state phase-change memory unit element was applied in as shown in Figure 4 operating current, its resistance had 4 to change comparatively significantly, that is: (3.7mA, 500k Ω) (2.5mA, 223k Ω) (2.4mA, 103k Ω) (0.3mA, 0.7k Ω), as shown in Figure 5.
From the above, the operating current variation of multi-state phase-change memory unit element can cause that resistance of equal value becomes series connection from parallel connection in the phase-change material, causes the phase-change memory unit element changes in resistance thus.Yet, structure at the existing phase-change memory unit element of using always, the change of electric current makes its resistance phasic Chang not too remarkable, so cause the utilance of its heat on the low side, therefore, how to design the multi-state phase-change memory structure that a kind of resistance phasic Chang is remarkable, heat utilization ratio is high,, become the technical task that those skilled in the art need to be resolved hurrily in fact to reduce device power consumption.
Summary of the invention
The object of the present invention is to provide a kind of multi-state phase-change memory unit element,, and then can effectively reduce the power consumption of device so that it has remarkable interim resistance variations.
Another object of the present invention is to provide a kind of preparation method of multi-state phase-change memory unit element.
Reach other purposes in order to achieve the above object, the significant multi-state phase-change memory unit element of resistance variations provided by the invention comprises: the lower electrode layer of electric conducting material; Be in described lower electrode layer surface and be the heating electrode layer of electric conducting material; Be in the combination layer of described heating electrode laminar surface, described combination layer comprise from laminar surface in floor, diffuse into first taper and continue in floor, to be shrunk to from place, described first taper awl bottom second taper the phase-change material district, and and described phase-change material district be combined to form the insulating material district of floor structure, wherein, the width of the cone top part of described first taper and second taper all is between 0.01 times to 0.03 times of described heating electrode layer width; Be in described combination layer surface and be the last contact electrode layer of electric conducting material; Be in described upward contact electrode laminar surface and be the upper electrode layer of electric conducting material.
Preferably, described heating electrode layer width is 1000nm, and the width of the cone top part of described first taper and second taper is preferably 20nm between 10nm to 30nm.
Preferably, the thickness of described lower electrode layer is 450nm, and described heating electrode layer thickness is 100nm, and the thickness of described combination layer is 500nm, and the described thickness of going up the contact electrode layer is 100nm, and described upper electrode layer thickness is 400nm.
Preferably, the material in described phase-change material district can be (Ge, Sb, Te), (Si, Sb, Te), and (Si, Sb) a kind of in being; The material in described insulating material district can be SiO2, ZrO2, TiO2,, Y203, Hf20, Ta205, amorphous Si or C; The material of described lower electrode layer and upper electrode layer can be W, TiN, Ta or Pt; The material of described heating electrode layer and last contact electrode can be TiN etc.
In addition, described lower electrode layer, heating electrode layer, combination layer, go up contact electrode, and the width and the thickness of upper electrode layer can carry out the equal proportion convergent-divergent according to actual needs.
The method for preparing the significant multi-state phase-change memory unit element of resistance variations of the present invention comprises step: 1) prepare bottom electrode through hole on Semiconductor substrate, and fasten plug toward the interior deposits conductive material of described bottom electrode through hole to form metal; 2) deposit an insulation material layer at the body structure surface that forms metal plug, and the described insulation material layer of etching to be forming taper through hole wide at the top and narrow at the bottom, and described taper via bottoms width is between 0.01 times to 0.03 times of described insulation material layer width; 3) sputtering sedimentation phase-change material in the described taper through hole, and the phase-change material of etching the first half makes it wear into up-narrow and down-wide taper, and the width at taper top is between 0.01 times to 0.03 times of described insulation material layer width; 4) replenish deposition of insulative material on established cone structure surface, and the chemico-mechanical polishing surface, make insulating material district and phase-change material district be combined to form the combination layer structure; And 5) described group and laminar surface deposits conductive material to form metal closures.
Wherein, the material of described insulation material layer can be SiO2, ZrO2, TiO2,, Y203, Hf20, Ta205, amorphous Si or C etc.
In sum, the significant multi-state phase-change memory unit element of resistance variations of the present invention can make melt region seal upper/lower electrode fully at very little operating current, and then along with the increasing of load, non-crystalline areas has interim change big, a plurality of Resistance states are changed significantly, and then can realize the low-power consumption and the high speed storing of memory cell.
Description of drawings
Fig. 1 is existing multi-state phase-change memory unit element longitudinal cross-section axially symmetric structure schematic diagram.
Fig. 2 a-2d is that current impulse drops to 5mA, 2.5mA, 2.4mA, when reaching 0.3mA, has the crystallization distribution situation schematic diagram of multi-state phase-change memory unit element now.
Fig. 3 a is current impulse 300ns decline 4mA, the amorphous distribution schematic diagram of the existing multi-state phase-change memory unit element in 10ns place.
Fig. 3 b is current impulse 700ns decline 4mA, the amorphous distribution schematic diagram of the existing multi-state phase-change memory unit element in 25ns place.
Fig. 4 is existing multi-state phase-change memory unit element current impulse schematic diagram.
Fig. 5 is existing multi-state phase-change memory unit element resistance variations schematic diagram under operating current effect shown in Figure 4.
Fig. 6 is the significant multi-state phase-change memory unit element of a resistance variations of the present invention longitudinal cross-section structural representation.
Fig. 7 is the significant multi-state phase-change memory unit element of resistance variations of the present invention resistance marked change schematic diagram under operating current effect shown in Figure 4.
Embodiment
See also Fig. 6, the significant multi-state phase-change memory unit element of resistance variations of the present invention comprises at least: lower electrode layer 6, heating electrode layer 5, combination layer, go up contact electrode layer 2, and upper electrode layer 1 etc.
Described lower electrode layer 6 can adopt electric conducting materials such as W, TiN, Ta or Pt, and its width is L4=1000nm, and thickness is h5=450nm.In the present embodiment, it adopts the W material.
Described heating electrode layer 5 is in described lower electrode layer 6 surfaces, and also is electric conducting material, and its width is L4=1000nm, and thickness is h6=100nm.In the present embodiment, it adopts the TiN material.
Described combination layer is in described heating electrode layer 5 surface, width is L4=1000nm, thickness is h7=500nm, comprise from laminar surface and in floor, diffuse into first taper (being the taper of the first half) and locate continuation is shrunk to second taper (being the taper of Lower Half) in floor phase-change material district 4 from described first taper awl bottom, reach the insulating material district 3 that is combined to form floor structure with described phase-change material district 4, wherein, the width of the cone top part of described first taper and second taper all is between 0.01 times to 0.03 times of described heating electrode layer width, be between the 10nm to 30nm, in the present embodiment, the width L5=20nm of the cone top part of described first taper and second taper, thickness are h7=500nm.The thickness in insulating material district 3 is h7=500nm, can adopt SiO2, ZrO2, TiO2,, materials such as Y203, Hf20, Ta205, amorphous Si or C, in the present embodiment, adopt SiO2.
The described contact electrode layer 2 of going up is in described combination layer surface, and is electric conducting material, for example is the TiN material, and its width is L4=1000nm, and thickness is h8=100nm.
Described upper electrode layer 1 is in described upward contact electrode layer 2 surface, and is electric conducting material, for example is the W material, and its width is L4=1000nm, and thickness is h9=400nm.
Be with noting, described lower electrode layer, heating electrode layer, combination layer, go up contact electrode, and the width and the thickness of upper electrode layer can carry out the equal proportion convergent-divergent according to actual needs, for example, dwindle 10% simultaneously.
After the significant multi-state phase-change memory unit element of described resistance variations is passed to as shown in Figure 4 operating current, it can produce different resistance, as shown in Figure 7, apparent in view resistance: (1.3mA 31000k Ω), (0.7mA, 15000k Ω), (0.4mA, 6842k Ω), (0.2mA, 1850k Ω), (0.1mA, 88k Ω) and (0.01mA, 32k Ω), compare (as shown in Figure 5) with the resistance of existing multi-state phase-change memory unit element, the significant multi-state phase-change memory unit element resistance variations of resistance variations of the present invention is more remarkable.
The preparation method of the significant multi-state phase-change memory unit element of described resistance variations is as follows:
At first, at Semiconductor substrate (impurity diffusion zone that comprises MOS, source-drain area, contact conductor, through hole, perhaps PN diode, bipolar transistor etc.) preparation bottom electrode through hole, its size is according to the process conditions adjustment, and its clear size of opening can be greater than or less than the size in phase-change material hole, then deposits conductive material in the bottom electrode through hole, such as W, TiN, conducting mediums such as silicide, Ta or Pt, to form metal plug, promptly form lower electrode layer 6 and heating electrode layer 5.
Then, deposit an insulation material layer (for example depositing SiO2) at the body structure surface that forms metal plug, and the described insulation material layer of etching is to form taper through hole wide at the top and narrow at the bottom, and described taper via bottoms width is between 0.01 times to 0.03 times of described insulation material layer width, i.e. 10nm-30nm.
Then, toward the interior sputtering sedimentation phase-change material of described taper through hole, thickness is 500～600nm, and the phase-change material of etching the first half makes it wear into up-narrow and down-wide taper, and the attenuate phase-change material is to 500nm thickness, the width at taper top is between 0.01 times to 0.03 times of described insulation material layer width,, i.e. 10nm-30nm.
Then, replenish deposition of insulative material (being SiO2) on established cone structure surface, and the chemico-mechanical polishing surface, make insulating material district and phase-change material district be combined to form the combination layer structure.
At last,, promptly form and go up contact electrode layer 2 and upper electrode layer 1 to form metal closures at electric conducting materials such as described phase-change material surface deposition TiN or W.
From the above mentioned, the significant multi-state phase-change memory unit element of resistance variations of the present invention is by regulating the operating current pulse, can effectively control the state of phase-change material, make it in low-resistance polycrystalline attitude, high-resistance amorphous state, change mutually between the different molten states, thereby produce visibly different multiple resistance, compared to existing multi-state phase-change memory unit element, it can make melt region seal upper/lower electrode fully under very little operating current, and then along with the increasing of load, non-crystalline areas has interim change big, make its resistance phasic Chang more remarkable, can effectively realize the low-power consumption and the high speed storing of memory cell thus.
Be noted that, more than the size of each layer structure among each embodiment be illustration only, be not to be used to limit the present invention, those skilled in the art can be adjusted according to actual conditions, for example can be according to the increase of the density of integrated circuit and equal proportion convergent-divergent etc.
The foregoing description just lists expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, the scope of the present invention should be listed as claims.
Claims (11)
1. significant multi-state phase-change memory unit element of resistance variations is characterized in that comprising:
The lower electrode layer of electric conducting material;
Be in described lower electrode layer surface and be the heating electrode layer of electric conducting material;
Be in the combination layer of described heating electrode laminar surface, described combination layer comprise from laminar surface in floor, diffuse into first taper and continue in floor, to be shrunk to from place, described first taper awl bottom second taper the phase-change material district, and and described phase-change material district be combined to form the insulating material district of floor structure, wherein, the width of the cone top part of described first taper and second taper all is between 0.01 times to 0.03 times of described heating electrode layer width;
Be in described combination layer surface and be the last contact electrode layer of electric conducting material;
Be in described upward contact electrode laminar surface and be the upper electrode layer of electric conducting material.
2. the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 1 is characterized in that: described heating electrode layer width is 1000nm, and the width of the cone top part of described first taper and second taper is between 10nm to 30nm.
3. the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 2 is characterized in that: the width of the cone top part of described first taper and second taper is preferably 20nm.
4. multi-state phase-change memory unit element as claimed in claim 1, it is characterized in that: the thickness of described lower electrode layer is 450nm, described heating electrode layer thickness is 100nm, the thickness of described combination layer is 500nm, the described thickness of going up the contact electrode layer is 100nm, and described upper electrode layer thickness is 400nm.
5. as claim 1 or 2 or the 3 or 4 significant multi-state phase-change memory unit elements of described resistance variations, it is characterized in that: described lower electrode layer, heating electrode layer, combination layer, last contact electrode, the width that reaches upper electrode layer and thickness is the equal proportion convergent-divergent according to actual needs.
6. the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 1 is characterized in that: the material in described phase-change material district for (Ge, Sb, Te), (Si, Sb, Te), and (Si, Sb) a kind of in being.
7. the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 1 is characterized in that: the material in described insulating material district is SiO2, ZrO2, TiO2,, Y2O3, Hf2O, Ta2O5, amorphous Si, and C in a kind of.
8. the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 1 is characterized in that: the material of described lower electrode layer and upper electrode layer be W, TiN, Ta, and Pt in a kind of.
9. the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 1 is characterized in that: the material of described heating electrode layer and last contact electrode is TiN.
10. method for preparing the significant multi-state phase-change memory unit element of resistance variations is characterized in that comprising step:
1) on Semiconductor substrate, prepares bottom electrode through hole, and fasten plug to form metal toward the interior deposits conductive material of described bottom electrode through hole;
2) deposit an insulation material layer at the body structure surface that forms metal plug, and the described insulation material layer of etching to be forming taper through hole wide at the top and narrow at the bottom, and described taper via bottoms width is between 0.01 times to 0.03 times of described insulation material layer width;
3) sputtering sedimentation phase-change material in the described taper through hole, and the phase-change material of etching the first half makes it wear into up-narrow and down-wide taper, and the width at taper top is between 0.01 times to 0.03 times of described insulation material layer width;
4) replenish deposition of insulative material on established cone structure surface, and the chemico-mechanical polishing surface, make insulating material district and phase-change material district be combined to form the combination layer structure;
5) described group and laminar surface deposits conductive material to form metal closures.
11. the method for preparing the significant multi-state phase-change memory unit element of resistance variations as claimed in claim 10 is characterized in that: the material of described insulation material layer is SiO2, ZrO2, TiO2,, Y2O3, Hf2O, Ta2O5, amorphous Si, and C in a kind of.
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| CN103106926A (en) * | 2011-11-10 | 2013-05-15 | 中国科学院微电子研究所 | One-time programming memory and preparation method thereof |
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