CN101504860B - Bit-line voltage generator with low coupling effect and controlling method thereof - Google Patents
Bit-line voltage generator with low coupling effect and controlling method thereof Download PDFInfo
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- CN101504860B CN101504860B CN200810004865XA CN200810004865A CN101504860B CN 101504860 B CN101504860 B CN 101504860B CN 200810004865X A CN200810004865X A CN 200810004865XA CN 200810004865 A CN200810004865 A CN 200810004865A CN 101504860 B CN101504860 B CN 101504860B
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Abstract
The invention discloses a bit line voltage generator and a control method thereof. The bit line voltage generator comprises an enhanced discharge voltage bias source and a switch element. The switch element comprises a clamping transistor, a switch transistor, a resistor and a capacitor, wherein in the clamping transistor, a grid electrode is connected to the enhanced discharge voltage bias source, and a drain electrode receives a voltage; in the switch transistor, a grid electrode receives a control signal, a drain electrode is connected to a source electrode of the clamping transistor, the source electrode is connected to a memory array, and a parasitic capacitor is arranged between the grid electrode and the source electrode of the clamping transistor; a first end of the resistor is connected to the drain electrode of the switch transistor, and a second end of the resistor is earthed; and a first end of the capacitor is connected to the drain electrode of the switch transistor, and the second end of the capacitor is earthed. The control method for the bit line voltage generator comprises the following steps that: the enhanced discharge voltage bias source charges the parasitic capacitor when the switch transistor is started; and when a drain voltage of the switch transistor rises to a stable value, the parasitic capacitor discharges through a discharge path of the enhanced discharge voltage bias source.
Description
Technical field
This case is a kind of voltage generator, refers to a kind of bit-line voltage generator with low coupling effect especially.
Background technology
Storer is that computing machine is used for the device of storage data and instruction.See also Fig. 1, it is the circuit diagram of the memory bit line voltage generator commonly used.This circuit comprises a voltage regulator 11 and a switch element 12, and in order to voltage to one memory array 13 to be provided, wherein this voltage regulator 11 is connected in this switch element 12, and this switch element 12 is connected in this memory array 13.This voltage regulator 11 comprises an operational amplifier 111, a pull-up transistor Mph, resistance R 1 and R2, wherein the inverting input of this operational amplifier 111 receives a reference voltage Vref, non-inverting input is connected between resistance R 1 and the R2, and output terminal is connected to the grid of this pull-up transistor Mph.The source electrode of this pull-up transistor Mph receives a voltage Vpp, and drain electrode is connected to first end of resistance R 1.First end of resistance R 2 is connected in second end of resistance R 1, and the second end ground connection.
This switch element 12 comprises a switching transistor Msw and a clamping transistor Mclamp, and wherein the grid of this switching transistor Msw receives a control signal
Drain electrode receives this voltage Vpp, and source electrode is connected in the drain electrode of this clamping transistor Mclamp.The grid of this clamping transistor Mclamp is connected in the drain electrode of this pull-up transistor Mph, and source electrode is connected in the bit line of this memory array 13.Have a stray capacitance Cp between the grid of this clamping transistor Mclamp and the source electrode, this stray capacitance Cp carries out precharge (precharge) via this pull-up transistor Mph, and discharges via resistance R 1 and R2.This memory array 13 is made up of a plurality of transistor 131, and wherein the grid of each transistor 131 is connected to a high voltage Vh respectively.
Above-mentioned this pull-up transistor Mph, this switching transistor Msw, this clamping transistor Mclamp, and transistor 131 be mos field effect transistor (MOSFET).
See also Fig. 2, it is the oscillogram of each node of Fig. 1 circuit, wherein node NB is between this pull-up transistor Mph and this clamping transistor Mclamp, node NC is between this switching transistor Msw and this clamping transistor Mclamp, and node ND is then between this clamping transistor Mclamp and this memory array 13.As shown in Figure 2, when this control signal
The time, this switching transistor Msw opens, and voltage V (ND) rises to 7V by 0V, so the electric charge among this stray capacitance Cp can be via resistance R 1 and R2 discharge 7V.Therefore, when this switching transistor Msw opens, can produce a surge voltage on the node NB, and because commonly using voltage regulator 11 only discharges via resistance string, so discharge time is quite long.In addition, because it is long to commonly use the limited setting time (finite settling time) of voltage regulator 11, so also can produce the problem of this stray capacitance Cp over-discharge can.The problems referred to above will cause providing voltage V (ND) instability to the bit line of this memory array 13.
In view of this, the applicant is because the disappearance of known techniques is invented out this case " bit-line voltage generator with low coupling effect ", in order to improve the above-mentioned disappearance of commonly using means.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of bit-line voltage generator with low coupling effect, in order to the coupling electric charge of reduction coupled source, and the discharge capability of raising bias generator.
According to above-mentioned conception, this case provides a kind of bit-line voltage generator, and it comprises an enhanced discharge bias generator and a switch element.This switch element comprises clamping transistor, switching transistor, bleeder resistance, reaches a maintenance electric capacity, and its grid is connected in this enhanced discharge bias generator, and its drain electrode receives a voltage; One switching transistor, its grid receives a control signal, and its drain electrode is connected in the source electrode of this clamping transistor, and its source electrode is connected to a memory array, wherein has a stray capacitance between the grid of this clamping transistor and the source electrode; One resistance, its first end is connected in the drain electrode of this switching transistor, its second end ground connection; An and electric capacity, its first end is connected in the drain electrode of this switching transistor, its second end ground connection, wherein the electric charge of this stray capacitance when this switching transistor opens and closes much at one, thereby reduce the coupling effect between this switch element and this enhanced discharge bias generator, and then the stable bias voltage that is applied to this memory array.
According to above-mentioned conception, this case provides a kind of bit-line voltage generator in addition, and it comprises an enhanced discharge bias generator and a switch element.This switch element has clamping transistor, switching transistor, bleeder resistance, reaches a maintenance electric capacity, and be connected between this an enhanced discharge bias generator and the memory array, wherein the electric charge of this stray capacitance when this switching transistor opens and closes much at one, thereby reduce the coupling effect between this switch element and this enhanced discharge bias generator, and then the stable bias voltage that is applied to this memory array.
According to above-mentioned conception, this case provides a kind of control method of bit-line voltage generator again, this bit-line voltage generator comprises an enhanced discharge bias generator and a switch element, this switch element comprises clamping transistor, switching transistor, bleeder resistance, reaches a maintenance electric capacity, has a stray capacitance between the grid of this clamping transistor and the source electrode, the source electrode of clamping transistor connects the drain electrode of switching transistor, its step comprises: when this switching transistor was opened, this enhanced discharge bias generator was to this stray capacitance charging; And when the drain voltage of this switching transistor rose to a stationary value, this stray capacitance was via the discharge path discharge of this enhanced discharge bias generator.
Description of drawings
Fig. 1: it is the circuit diagram of the memory bit line voltage generator commonly used.
Fig. 2: it is the oscillogram of each node of Fig. 1 circuit.
Fig. 3: it is the calcspar of the bit-line voltage generator with low coupling effect of this case.
Fig. 4: it is the circuit diagram of the bit-line voltage generator with low coupling effect of this case one preferred embodiment.
Fig. 5: it is the oscillogram of each node of Fig. 2 circuit.
Fig. 6: it is the circuit diagram of the enhanced discharge bias generator of another preferred embodiment of this case.
Fig. 7: it is the circuit diagram of the enhanced discharge bias generator of the another preferred embodiment of this case.
[main element symbol description]
11: voltage regulator
111: operational amplifier
12: switch element
13: memory array
131: transistor
31: the enhanced discharge bias generator
311:AB class output stage
312: operational amplifier
32: the low coupling effect switch element
33: memory array
331: transistor
Embodiment
See also Fig. 3, it is the calcspar of the bit-line voltage generator with low coupling effect of this case.This bit-line voltage generator with low coupling effect comprises an enhanced discharge bias generator 31 and a low coupling effect switch element 32, wherein this enhanced discharge bias generator 31 is connected in this low coupling effect switch element 32, and this low coupling effect switch element 32 then is connected to a memory array 33.Have a node NB between this enhanced discharge bias generator 31 and this low coupling effect switch element 32, and have a node ND between this low coupling effect switch element 32 and this memory array 33.
See also Fig. 4, it is the circuit diagram of the bit-line voltage generator with low coupling effect of this case one preferred embodiment.This enhanced discharge bias generator 31 comprises an operational amplifier 312, an AB class output stage 311, reaches resistance R 1 and R2, and wherein this AB class output stage 311 comprises two diode D1 and D2, a current source Ib, a pull-up transistor Mph, reaches a pulldown transistors Mpl.The non-inverting input of this operational amplifier 312 receives a reference voltage Vref, and inverting input is connected to first end of resistance R 2, and output terminal then is connected to the anode of diode D1 and the grid of this pull-up transistor Mph.The negative electrode of diode D1 is connected in the anode of diode D2, and the negative electrode of diode D2 is connected in the input end of this current source Ib.The grid of this pulldown transistors Mpl is connected in the input end of this current source Ib, and drain electrode is connected in the source electrode of this pull-up transistor Mph, source electrode then with the output terminal common ground of this current source Ib.The grid of this pull-up transistor Mph is connected in the output terminal of this operational amplifier 312, and drain electrode receives a voltage Vpp, and source electrode is connected in first end of resistance R 1.Second end of resistance R 1 is connected in first end of resistance R 2, and second end of resistance R 2 is ground connection then.
This low coupling effect switch element 32 comprises a clamping transistor Mclamp, a switching transistor Msw, a bleeder resistance Rlk, reaches a maintenance capacitor C h, wherein has a stray capacitance Cp between the grid of this clamping transistor Mclamp and the source electrode.The grid of this clamping transistor Mclamp is connected in the source electrode of this pull-up transistor Mph, and drain electrode receives this voltage Vpp, and source electrode then is connected in the drain electrode of this switching transistor Msw.The grid of this switching transistor Msw receives a control signal, and source electrode then is connected to the bit line of this memory array 33.First end of first end of this bleeder resistance Rlk and this maintenance capacitor C h is connected in the drain electrode of this switching transistor Msw jointly, and second end of this bleeder resistance Rlk and this keep second end of capacitor C h then to distinguish ground connection.
Above-mentioned this pull-up transistor Mph, this pulldown transistors Mpl, this clamping transistor Mclamp, and this switching transistor Msw be MOSFET.This memory array 33 is made up of a plurality of MOSFET 331, and wherein the grid of each MOSFET 331 system receives a high voltage Vh respectively.
Except resistance R 1, discharge path that R2 formed, this pulldown transistors Mpl provide another discharge path, to accelerate release time when this switching transistor Msw opens.Diode D1, D2 and this current source Ib system provide voltage drop, can open a little simultaneously to guarantee this pull-up transistor Mph and this pulldown transistors Mpl.This bleeder resistance Rlk can cause small leakage current Il, and therefore the value of the value of the voltage V (NC) when this switching transistor Msw closes and the voltage V (NC) when this switching transistor Msw opens is very approaching.And should keep capacitor C h can be when this switching transistor Msw opens regulation voltage V (NC).
When
The time, this switching transistor Msw closes, and voltage V this moment (NC) is a fixed value.And work as
The time, this switching transistor Msw opens, and voltage V this moment (NC) descends, voltage V (NB) also descends, so this enhanced discharge bias generator 31 can be to this stray capacitance Cp charging, and as voltage V (NC) when stablizing, this stray capacitance Cp can discharge via the discharge path of this enhanced discharge bias generator 31.
See also Fig. 5, it is the oscillogram of each node of Fig. 4 circuit.As shown in Figure 5, when this switching transistor Msw opens, this stray capacitance Cp about 0.3V that need charge.When this switching transistor Msw opened, voltage V (NB) can descend suddenly along with the decline of voltage V (NC), so this enhanced discharge bias generator 31 can charge to this stray capacitance Cp earlier.Then, voltage V (NC) rises to a stationary value, and owing to slightly overcharging that voltage V (NB) is caused when descending suddenly, voltage V (NB) can produce slight outstanding (overshoot) phenomenon.Because this enhanced discharge bias generator 31 has powerful dragging down (pull low) ability,, thereby eliminate the protrusion phenomenon of voltage V (NB) apace so this stray capacitance Cp can be via these enhanced discharge bias generator 31 rapid discharges.
The enhanced discharge bias generator 31 of this case is not limited to sample attitude shown in Figure 4, so long as can accelerate the bias generator of the velocity of discharge, all can be used as the enhanced discharge bias generator 31 of this case.
See also Fig. 6, it is the circuit diagram of the enhanced discharge bias generator of another preferred embodiment of this case.This enhanced discharge bias generator 31 comprises a current source Isource, a first transistor M1, a transistor seconds M2, one the 3rd transistor M3, one the 4th transistor M4, one the 5th transistor M5, one the 6th transistor M6, a pull-up transistor Mph, a pulldown transistors Mpl, reaches resistance R 1 and R2.The input end of this current source Isource is connected to the source electrode of this first transistor M1 and the source electrode of this transistor seconds M2, output head grounding.The grid of this first transistor M1 is connected between resistance R 1 and the R2, and drain electrode is connected in the source electrode of the 3rd transistor M3.The grid of this transistor seconds M2 receives a reference voltage Vref, and drain electrode is connected in the source electrode of the 4th transistor M4.The grid of the 3rd transistor M3 is connected in its source electrode, and drain electrode receives a voltage Vpp.The grid of the 4th transistor M4 is connected in its source electrode, and drain electrode receives this voltage Vpp.The grid of the 5th transistor M5 is connected in the grid of the 3rd transistor M3, and drain electrode is connected to this reference voltage Vpp, and source electrode is connected in the drain electrode of the 6th transistor M6.The grid of the 6th transistor M6 is connected in its drain electrode, source ground.The grid of this pull-up transistor Mph is connected in the grid of the 4th transistor M4, and drain electrode receives this voltage Vpp, and source electrode is connected in the drain electrode of this pulldown transistors Mpl.The grid of this pulldown transistors Mpl is connected in the grid of the 6th transistor M6, source ground.First end of resistance R 1 is connected in the source electrode of this pull-up transistor Mph, and second end is connected in first end of resistance R 2.The second end ground connection of resistance R 2.
Above-mentioned this first transistor M1, this transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, this pull-up transistor Mph, this pulldown transistors Mpl, this clamping transistor Mclamp, and this switching transistor Msw be MOSFET.
See also Fig. 7, it is the circuit diagram of the enhanced discharge bias generator of the another preferred embodiment of this case.This enhanced discharge bias generator 31 comprises a current source Isource, a first transistor M1, a transistor seconds M2, one the 3rd transistor M3, one the 4th transistor M4, one the 5th transistor M5, one the 6th transistor M6, a pull-up transistor Mph, a pulldown transistors Mpl, a miller compensation capacitor C c, reaches resistance R 1 and R2.The input end of this current source Isource receives a voltage Vpp, and output terminal is connected to the drain electrode of this first transistor M1 and the drain electrode of this transistor seconds M2.The grid of this first transistor M1 receives a reference voltage Vref, and source electrode is connected in the drain electrode of the 3rd transistor M3.The grid of this transistor seconds M2 is connected between resistance R 1 and the R2, and source electrode is connected in the drain electrode of the 4th transistor M4.The grid of the 3rd transistor M3 is connected in the grid of the 4th transistor M4, source ground.The grid of the 4th transistor M4 is connected in the grid of the 3rd transistor M3, source ground.The grid of the 5th transistor M5 is connected in its source electrode, and drain electrode is connected to this voltage Vpp, and source electrode is connected in the drain electrode of the 6th transistor M6.The grid of the 6th transistor M6 is connected in the grid of the 3rd transistor M3, source ground.The grid of this pull-up transistor Mph is connected in the grid of the 5th transistor M5, and drain electrode is connected to this voltage Vpp, and source electrode is connected in the drain electrode of this pulldown transistors Mpl.The grid of this pulldown transistors Mpl is connected in the drain electrode of the 3rd transistor M3, source ground.This coupling capacitance Cc is connected between the grid and drain electrode of this pulldown transistors Mpl.First end of resistance R 1 is connected in the source electrode of this pull-up transistor Mph, and second end is connected in first end of resistance R 2.The second end ground connection of resistance R 2.
Above-mentioned this first transistor M1, this transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, this pull-up transistor Mph, this pulldown transistors Mpl, this clamping transistor Mclamp, and this switching transistor Msw be MOSFET.
In sum, this case is to use an enhanced discharge bias generator and a low coupling effect switch element to obtain a low coupling effect bit-line voltage, can obtain a stable bias voltage that can be applied to bit line by this case, it can be applicable to all storeies, for example flash memory (flash mempry).Therefore, this case can effectively improve the disappearance of known techniques, hereat has industrial value, and then reaches the purpose of development this case.
This case must be thought and is to modify as all by the personage Ren Shi craftsman who is familiar with this skill, the scope of right neither disengaging claims institute desire protection.
Claims (14)
1. a bit-line voltage generator is characterized in that, comprises:
One enhanced discharge bias generator; And
One switch element, this switch element comprises:
One clamping transistor, its grid are connected in this enhanced discharge bias generator, and its drain electrode receives a voltage;
One switching transistor, its grid receives a control signal, and its drain electrode is connected in the source electrode of this clamping transistor, and its source electrode is connected to a memory array, wherein has a stray capacitance between the grid of this clamping transistor and the source electrode;
One resistance, its first end is connected in the drain electrode of this switching transistor, its second end ground connection; And
One electric capacity, its first end is connected in the drain electrode of this switching transistor, its second end ground connection, wherein the electric charge of this stray capacitance when this switching transistor opens and closes much at one, thereby reduce the coupling effect between this switch element and this enhanced discharge bias generator, and then the stable bias voltage that is applied to this memory array.
2. bit-line voltage generator according to claim 1 is characterized in that, this enhanced discharge bias generator comprises:
One operational amplifier, its non-inverting input receives a reference voltage;
One first diode, its anode is connected in the output terminal of this operational amplifier;
One second diode, its anode is connected in the negative electrode of this first diode;
One current source, its input end is connected in the negative electrode of this second diode, its output head grounding;
One pulldown transistors, its grid is connected in the input end of this current source, and its source electrode is connected in the output terminal of this current source;
One pull-up transistor, its grid is connected in the output terminal of this operational amplifier, and its drain electrode receives this voltage, and its source electrode is connected in the drain electrode of this pulldown transistors;
One first resistance, its first end is connected in the source electrode of this pull-up transistor, and its second end is connected in the inverting input of this operational amplifier; And
One second resistance, its first end is connected in the inverting input of this operational amplifier, its second end ground connection.
3. bit-line voltage generator according to claim 2 is characterized in that, the source electrode of this pull-up transistor is connected in the grid of this clamping transistor.
4. bit-line voltage generator according to claim 1 is characterized in that, this enhanced discharge bias generator comprises:
One current source, its output head grounding;
One the first transistor, its source electrode is connected in the input end of this current source;
One transistor seconds, its grid receives a reference voltage, and its source electrode is connected in the input end of this current source;
One the 3rd transistor, its grid is connected in its source electrode, and its drain electrode receives this voltage, and its source electrode is connected in the drain electrode of this first transistor;
One the 4th transistor, its grid is connected in its source electrode, and its drain electrode receives this voltage, and its source electrode is connected in the drain electrode of this transistor seconds;
One the 5th transistor, its grid are connected in the 3rd transistorized grid, and its drain electrode receives this voltage;
One the 6th transistor, its grid is connected in its drain electrode, and its drain electrode is connected in the 5th transistorized source electrode, its source ground;
One pull-up transistor, its grid are connected in the 4th transistorized grid, and its drain electrode receives this voltage;
One pulldown transistors, its grid are connected in the 6th transistorized grid, and its drain electrode is connected in the source electrode of this pull-up transistor, its source ground;
One first resistance, its first end is connected in the source electrode of this pull-up transistor, and its second end is connected in the grid of this first transistor; And
One second resistance, its first end is connected in second end of this first resistance, its second end ground connection.
5. bit-line voltage generator according to claim 4 is characterized in that, the source electrode of this pull-up transistor is connected in the grid of this clamping transistor.
6. bit-line voltage generator according to claim 1 is characterized in that, this enhanced discharge bias generator comprises:
One current source, its input end receives this voltage;
One the first transistor, its grid receives a reference voltage, and its drain electrode is connected in the output terminal of this current source;
One transistor seconds, its drain electrode is connected in the output terminal of this current source;
One the 3rd transistor, its drain electrode is connected in the source electrode of this first transistor, its source ground;
One the 4th transistor, its grid are connected in the 3rd transistorized grid, and its drain electrode is connected in the source electrode of this transistor seconds, its source ground;
One the 5th transistor, its grid is connected in its source electrode, and its drain electrode receives this voltage;
One the 6th transistor, its grid are connected in the 3rd transistorized grid, and its drain electrode is connected in the 5th transistorized source electrode, its source ground;
One pull-up transistor, its grid are connected in the 5th transistorized grid, and its drain electrode receives this voltage;
One pulldown transistors, its grid is connected in the 3rd transistor drain, and its drain electrode is connected in the source electrode of this pull-up transistor, its source ground;
One coupling capacitance is connected between the grid and drain electrode of this pulldown transistors;
One first resistance, its first end is connected in the source electrode of this pull-up transistor, and its second end is connected in the grid of this transistor seconds; And
One second resistance, its first end is connected in second end of this first resistance, its second end ground connection.
7. bit-line voltage generator according to claim 6 is characterized in that, the source electrode of this pull-up transistor is connected in the grid of this clamping transistor.
8. a switch element is characterized in that, comprises:
One the first transistor, its grid are connected in an enhanced discharge bias generator, and its drain electrode receives a voltage;
One transistor seconds, its grid receives a control signal, and its drain electrode is connected in the source electrode of this first transistor, and its source electrode is connected to a memory array, wherein has a stray capacitance between the grid of this first transistor and the source electrode;
One resistance, its first end is connected in the drain electrode of this transistor seconds, its second end ground connection; And
One electric capacity, its first end is connected in the drain electrode of this transistor seconds, its second end ground connection, wherein the electric charge of this stray capacitance when this transistor seconds opens and closes much at one, thereby reduce the coupling effect between this switch element and this enhanced discharge bias generator, and then the stable bias voltage that is applied to this memory array.
9. a bit-line voltage generator is characterized in that, comprises:
One enhanced discharge bias generator; And
One switch element, have clamping transistor, switching transistor, bleeder resistance, reach a maintenance electric capacity, wherein has a stray capacitance between the grid of clamping transistor and the source electrode, the source electrode of clamping transistor connects the drain electrode of switching transistor, and this switch element is connected between this an enhanced discharge bias generator and the memory array
Wherein the electric charge of this stray capacitance when this switching transistor opens and closes much at one, thereby reduce coupling effect between this switch element and this enhanced discharge bias generator, and then stablize the bias voltage that is applied to this memory array.
10. the control method of a bit-line voltage generator, this bit-line voltage generator comprises an enhanced discharge bias generator and a switch element, this switch element comprises clamping transistor, switching transistor, bleeder resistance, reaches a maintenance electric capacity, wherein has a stray capacitance between the grid of this clamping transistor and the source electrode, the source electrode of clamping transistor connects the drain electrode of switching transistor, it is characterized in that its step comprises:
When this switching transistor was opened, this enhanced discharge bias generator was to this stray capacitance charging; And
When the drain voltage of this switching transistor rose to a stationary value, this stray capacitance was via the discharge path discharge of this enhanced discharge bias generator.
11. method according to claim 10 is characterized in that, when this switching transistor cut out, the drain voltage of this switching transistor was a fixed value.
12. method according to claim 10 is characterized in that, the discharge path of this enhanced discharge bias generator comprises one first discharge path and one second discharge path.
13. method according to claim 12 is characterized in that, this first discharge path is made up of a first transistor and a transistor seconds.
14. method according to claim 12 is characterized in that, this second discharge path is through a pulldown transistors.
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| CN200810004865XA CN101504860B (en) | 2008-02-05 | 2008-02-05 | Bit-line voltage generator with low coupling effect and controlling method thereof |
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| CN200810004865XA CN101504860B (en) | 2008-02-05 | 2008-02-05 | Bit-line voltage generator with low coupling effect and controlling method thereof |
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| CN101504860B true CN101504860B (en) | 2011-09-14 |
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