CN101499789B - Time-delay regulator with high resolution - Google Patents

Abstract

The invention relates to a delay regulator which is used for regulating the delay time of signals and comprises a first capacitor unit and a variable capacitor unit which is coupled with the first capacitor unit in series and regulates the capacitance value of the variable capacitor unit according to a first control signal; the variable capacitor unit comprises a plurality of second capacitors and at least one first switch which is coupled with at least one of the plurality of second capacitors.

Description

A kind of time-delay regulator with high-res

Technical field

The present invention is relevant to a kind of time-delay regulator, refers to a kind of time-delay regulator with high-res especially.

Background technology

In integrated circuit, because the passing time of signal can be subjected to parasitic capacitance, drive current and operating voltage on the plain conductor ... the influence that waits, make signal on transmitting, can produce one transmission delay period, this transmission delay time is in the application of some high speed circuits or some special circuits, have important considering, in general, the transmission delay time can be estimated by following formula

$\mathrm{Td}=\frac{C}{I}\×\left(\frac{1}{2}\right)\×\mathrm{Vdd}$ (formula one)

Wherein Td is the transmission delay time, and C gives birth to electric capacity in season, and I is a drive current, and Vdd is an operating voltage.Because circuit can be subjected to processing procedure drift, voltage drift and temperature effect, making the transmission delay time become can't expect, therefore might make circuit produce abnormal running, so in some cases, the transmission delay time need be compensated, and makes the circuit normal operation.In known technology, commonly adopt the practice of electric capacity parallel connection, adjust the transmission delay time, and the method is with present processing procedure, adjustable resolution approximately can arrive 10ps, but on the high speed circuit or circuit application that some are special of some, also need higher adjustment resolution, make the characteristic of circuit integral body become better.

Summary of the invention

Therefore, one of purpose of the present invention is to provide a kind of time-delay regulator with high-res.

According to one embodiment of the invention, disclose a kind of time-delay regulator, this time-delay regulator is used for adjusting the time of delay of a signal, and it comprises: one first capacitor cell; One variable-capacitance unit, this first capacitor cell of coupled in series, this variable-capacitance unit foundation first control signal is adjusted the capacitance of this variable-capacitance unit, and this variable-capacitance unit comprises: a plurality of second electric capacity; And at least one first switch, couple at least one these a plurality of second electric capacity.

Description of drawings

The 1st figure is a time-delay regulator of the present invention.

The 2nd figure is the analog to digital converter that time-delay regulator of the present invention is applied to a time alternating expression.

The 3rd figure is that time-delay regulator of the present invention is applied to a receiver.

[main element symbol description]

100	Time-delay regulator
		102	Electric capacity
104	Variable-capacitance unit
		106	Application circuit
C1、C2、C3	Electric capacity
		SW1、SW2、SW3	Transistor switch
202	The time alternation type analog to digital converter
		204、206、322、324	Analog to digital converter
208	Multiplexer
		210	The phase-locked loop
212、326	Phase detector
		214、328	Control unit
216	Control signal
		302	Band selector
304	Low noise amplifier
		306	Local oscillator
308、310	Frequency mixer
		312	Phase shifter
314、316	Filter
		318、320	Variable gain amplifier

Embodiment

Below explanation illustrates preferred embodiment of the present invention with reference to correlative type, make any those skilled in the art can implement the present invention according to this, though embodiments of the invention are difference to some extent, but Shuo Ming indivedual characteristics, structure or feature is in order to get in touch arbitrary embodiment herein, in need not to depart from the scope of the present invention, can be implemented on according to this among other embodiment, but not the following stated mode only.In addition, the arrangement of the individual elements among the embodiment of each exposure and position work as in not departing from the scope of the present invention and can do suitable change, so protection scope of the present invention are as the criterion when looking appended the claim person of defining." coupling (couple to) " mentioned in this specification includes " directly connecting " and " indirect connection ".

See also the 1st figure, the 1st figure is one embodiment of the invention, time-delay regulator 100 is coupled to the output of an application circuit 106, be used for adjusting the transmission delay time of application circuit 106 output signals, postpone to adjust 100 and comprise an electric capacity 102 and a variable-capacitance unit 104, wherein, electric capacity 102 forms a tandem junction structure with variable-capacitance unit 104; Variable-capacitance unit 104 comprises capacitor C 1, C2, C3 and transistor switch SW1, SW2, SW3, wherein capacitor C 1 couples mutually with transistor switch SW1, capacitor C 2 couples mutually with transistor switch SW2, capacitor C 3 couples mutually with transistor switch SW3, for convenience of description, the capacitance equivalence of supposing electric capacity 102 is Cx, the capacitance equivalence of variable-capacitance unit 104 is Cy, the equivalent capacitance value of time-delay regulator 100 is Ceff, because electric capacity 102 and variable-capacitance unit 104 are cascaded structure, the equivalent capacitance value Ceff of time-delay regulator 100 can be by following formulate

$\mathrm{Ceff}=\frac{\mathrm{Cx}\×\mathrm{Cy}}{\mathrm{Cx}+\mathrm{Cy}}$ (formula two)

If Cy=α * Cx and α＞＞1 item

$\mathrm{Ceff}=\left(\frac{\mathrm{\α}}{1+\mathrm{\α}}\right)\×\mathrm{Cx}=\left(\frac{1}{1+\frac{1}{\mathrm{\α}}}\right)\×\mathrm{Cx}\≅(1-\frac{1}{\mathrm{\α}})\×\mathrm{Cx}$ (formula three)

As shown from the above formula, if select bigger α value, for example α is 100, Ceff=0.99*Cx then, on the whole, be equivalent to only Cx adjusted 1%, as if the transmission delay time with circuit, use this kind time-delay regulator 100, the esolving degree that can improve the delay adjustment time is to 0.1ps, and therefore, circuit designers can be utilized control signal, oxide-semiconductor control transistors switch SW 1, SW2 and SW3, adjust electric capacity number in parallel in the variable-capacitance unit 104 with school capacitance Cy such as adjustment, the signal propagation delay time that obtains wanting, wherein, control signal can be designed to analog control signal or digital controlled signal according to designer's demand.Though present embodiment is 100 as embodiment with α, α also can be designed to other value, and for example, α is more than or equal to 2, and α is more than or equal to 10, and α is more than or equal to 20.In addition, electric capacity of the present invention can adopt metal (Metal) electric capacity, polysilicon (Poly-Silicon) electric capacity or golden oxygen half (MOS) electric capacity to finish.

See also the 2nd figure, the 2nd figure is an embodiment of time-delay regulator of the present invention, be applied in the analog to digital converter (Time-Interleaved Analog to Digital Converter) 202 of time alternation type, the analog to digital converter 202 of alternating expression comprises first analog to digital converter 204, second analog to digital converter 206 and multiplexer 208, wherein first analog to digital converter 204 and second analog to digital converter 206 receive 210 clock signal clk1 and the clk2 that exported from the phase-locked loop respectively, and 90 ° of phase phasic differences, because clock signal clk1 and clk2 are the important references signal of the analog to digital converter 202 of time alternation type, it is used as the clock pulse of sampling, if the phase place of this two clock signals clk1 and clk2 produces and does not match, be clk1, the phase phasic difference of clk2 is not 90 °, then can have influence on the normal operation of the analog to digital converter 202 of time alternation type, and generation time (Timing error), therefore, time-delay regulator 100 can be used to adjust the phase error of this two clock signals clk1 and clk2, makes that the analog to digital converter 202 of alternating expression can normal operation; As shown in the figure, time-delay regulator 100 is coupled to the output of phase-locked loop 210, phase detector 212 is used for detecting the phase error of arteries and veins signal clk1 and clk2, to produce detecting result to a control unit 214, then, control unit 214 produces the variable-capacitance unit 104 of a control signal 216 to this time-delay regulator 100 according to this detecting result, by changing its capacitance, adjust the phase place of clk2, make the phase difference of clk1, clk2 can equal 90 °.

See also the 3rd figure, the 3rd figure is an embodiment of time-delay regulator of the present invention, be applied in the receiver, this receiver comprises band selector (band selector) 302, low noise amplifier (lownoise amplifier, LNA) 304, local oscillator (local oscillator, LO) 306, first frequency mixer 308, second frequency mixer 310, phase shifter 312, first filter 314, second filter 316, first variable gain amplifier (variable gain amplifier, VGA) 318, second variable gain amplifier 320, first analog to digital converter 322 and second analog to digital converter 324; When signal is received into, behind band selector 302 and low noise amplifier 304, frequency mixer 308,310 is done mixing respectively with input signal and oscillator signal OS1 and OS2 (its phase difference is 90 °), signal after the mixing is again by the element of rear end, after filter, variable gain amplifier and analog to digital converter process, output I signal and Q signal.But oscillator signal OS1 and OS2 may be subjected to processing procedure, voltage and the scale of thermometer and influence such as move, and make receiver that do not match (the IQ mismatch) of I signal and Q signal can take place, and the whole circuit running of influence.Therefore, time-delay regulator 100 can be used to adjust the phase error of this two oscillator signals OS1 and OS2, makes that receiver can normal operation, to reduce I signal and the unmatched problem of Q signal; As shown in the figure, time-delay regulator 100 is coupled to the output of local oscillator 306, phase detector 326 is used for detecting the phase error of arteries and veins signal OS1 and OS2, to produce detecting result to a control unit 328, then, control unit 328 produces the variable-capacitance unit 104 of a control signal 330 to this time-delay regulator 100 according to this detecting result, by changing its capacitance, to adjust the phase place of OS2, make the phase difference of OS and OS2 can equal 90 °.

Another embodiment, the electric capacity 102 of the time-delay regulator 100 of the 1st figure is a variable capacitance 102, wherein, the structure of this variable capacitance 102 is similar to the variable-capacitance unit 104 of the 1st figure, has comprised a plurality of capacitor cells and corresponding switch.By the capacitance of this variable capacitance 102 with these a plurality of capacitor cells of this variable-capacitance unit 104 designed through simple, variable capacitance 102 can be considered as the delay cell of a coarse adjustment, variable capacitance 102 is considered as the delay cell of a fine setting, the operation of this embodiment is similar to the embodiment of first figure, this no longer superfluous retouching.

Though the present invention is with the analog to digital converter of time alternation type and the receiver range of application as time-delay regulator, but the time-delay regulator that utilizes an electric capacity and a variable-capacitance unit to be in series can be applied in other the application, for example, in the analogy video signal fore device, conveyer (transmitter) in the analog to digital converter of processing rgb signal and the communication field ... etc.In addition, in the embodiments of the invention, electric capacity 102 and variable-capacitance unit 104 its location swaps, also can implement, and, though time-delay regulator of the present invention is connected as embodiment with an electric capacity and a variable-capacitance unit, the circuit structure that produces other according to this invention idea also is category of the present invention.

The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (25)

1. a time-delay regulator, in order to according to first control signal to adjust the time of delay of signal, this time-delay regulator comprises:

One first capacitor cell; And

One variable-capacitance unit, coupled in series be to this first capacitor cell, and this variable-capacitance unit is adjusted the capacitance of this variable-capacitance unit according to this first control signal, and this variable-capacitance unit comprises:

A plurality of second electric capacity; And

At least one first switch, each couples in these a plurality of second electric capacity one, in order to adjust the capacitance of this variable-capacitance unit according to this first control signal.

2. time-delay regulator as claimed in claim 1, wherein this first capacitor cell is one second variable-capacitance unit, this second variable-capacitance unit is used for adjusting the capacitance of this second variable-capacitance unit according to second control signal.

3. time-delay regulator as claimed in claim 2, wherein this first capacitor cell comprises:

A plurality of the 3rd electric capacity; And

At least one second switch, each is coupled in these a plurality of the 3rd electric capacity one.

4. time-delay regulator as claimed in claim 1 is applied in the analog to digital converter.

5. time-delay regulator as claimed in claim 4, wherein this analog to digital converter is the analog to digital converter of a time alternating expression.

6. time-delay regulator as claimed in claim 5, wherein this signal is first clock signal.

7. time-delay regulator as claimed in claim 6 is coupled to the output of a phase-locked loop.

8. time-delay regulator as claimed in claim 7, wherein the analog to digital converter of this time alternation type comprises:

One detecting unit is used for detecting the phase difference of this first clock signal and second clock signal; And

One control unit is coupled to this detecting unit, is used for detecting result according to this detecting unit, produces this first control signal.

9. time-delay regulator as claimed in claim 1 is applied in the receiver.

10. time-delay regulator as claimed in claim 9, wherein this signal is first oscillator signal.

11. time-delay regulator as claimed in claim 10, wherein this receiver comprises:

One first frequency mixer is used for mixing input signal and this first oscillator signal; And

One second frequency mixer is used for mixing this input signal and second oscillator signal;

Wherein, this first oscillator signal becomes 90 degree phase differences with this second oscillator signal.

12. time-delay regulator as claimed in claim 11 is coupled to this first frequency mixer, this time-delay regulator be used for according to this first control signal adjust this first with the phase difference of this second oscillator signal.

13. as claim 12 a described time-delay regulator, wherein this receiver comprises:

One detecting unit is used for detecting the phase difference of this first oscillator signal and this second oscillator signal; And

One control unit is coupled to this detecting unit, is used for detecting result according to this detecting unit, produces this first control signal.

14. time-delay regulator as claimed in claim 1, wherein this signal is an oscillator signal.

15. time-delay regulator as claimed in claim 14, wherein this first capacitor cell receives this oscillator signal.

16. time-delay regulator as claimed in claim 14, wherein this variable-capacitance unit receives this oscillator signal.

17. time-delay regulator as claimed in claim 1, wherein this control signal is a digital controlled signal.

18. time-delay regulator as claimed in claim 1, wherein this control signal is an analog control signal.

19. time-delay regulator as claimed in claim 1, wherein this first capacitor cell and second electric capacity are a metal (Metal) electric capacity.

20. time-delay regulator as claimed in claim 1, wherein this first capacitor cell and second electric capacity are a polysilicon (Poly-Silicon) electric capacity.

21. time-delay regulator as claimed in claim 1, wherein this first capacitor cell and second electric capacity are a gold medal oxygen half (MOS) electric capacity.

22. time-delay regulator as claimed in claim 1, wherein the capacitance of this variable-capacitance unit is greater than the capacitance of this first capacitor cell.

23. time-delay regulator as claimed in claim 1, wherein at least two times of capacitances of the capacitance of this variable-capacitance unit greater than this first capacitor cell.

24. time-delay regulator as claimed in claim 1, wherein at least ten times of capacitances of the capacitance of this variable-capacitance unit greater than this first capacitor cell.

25. time-delay regulator as claimed in claim 1, wherein at least two ten times of capacitances of the capacitance of this variable-capacitance unit greater than this first capacitor cell.

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