CN101494579B - Bus scheduling device and method - Google Patents
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Abstract
The invention provides a bus dispatching device and a method. The bus dispatching device comprises a receiving unit and a transmitting unit, wherein, the receiving unit continuously receives data packets of scheduled amount after transmitting a writing request to an interface at an opposite end, or the transmitting unit transmits the processed data packets accumulated to the scheduled amount to the interface at the opposite end by one-time operation after transmitting a reading request to the opposite end. The invention receives and/or transmits the data packets in batches, which can prevent packet-loss phenomenon in the intermediate process, and avoid the frequent transmitting of reading and writing requests and the waiting for response, thus guaranteeing the reliability of data transmission and improving the transmission efficiency.
Description
Technical field
The present invention relates to mobile communcations system, especially device interconnection and bus scheduling device and the method used in the mobile communcations system.
Background technology
The IEEE802.16 technology is a wireless access wide band technology, provides professional through inserting core net to the user, and core net adopts the network based on the IP agreement usually.The physical layer of IEEE802.16e can be selected single carrier, OFDM (OFDM) and OFDM (OFDMA) totally 3 kinds of technology for use.The single carrier option mainly is for the line-of-sight transmission of compatible 10GHz to the 66GHz frequency range.IEEE 802.16e can support 128,512,1024 and 2048 totally 4 kinds of different subcarriers quantity to the OFDMA physical layer, but subcarrier spacing is constant, and signal bandwidth is directly proportional with number of subcarriers.This technology is called extendible OFDMA (Scalable OFDMA).Adopt this technology, system can be in mobile environment the variation of flexible adaptation channel width.IEEE 802.16 technology can obtain different access rates under different wireless parameter combinations.With the 10MHz carrier bandwidths is example, if adopt 64QAM (quadrature amplitude modulation) modulation system, the single carrier bandwidth can provide effective access rate of about 30Mbit/second.The carrier bandwidths scope that IEEE 802.16 standards are suitable for does not wait from 1.75MHz to 20MHz, and under the situation of 20MHz channel width, 64QAM modulation, transmission rate can reach 74.81Mbit/second.
Multiple-input and multiple-output (MIMO) technology is that future mobile communication system is realized high data rate, improves the important channel of transmission reliability, and the method that solves following wireless access wide band technology volume of business demand bottleneck problem is provided.The MIMO technology adopts a plurality of antennas respectively at transmitting terminal and receiving terminal exactly, thereby improves the service quality (bit error rate or data rate) that each user obtains, and utilizes the MIMO technology can reach higher channel width, improves the service performance of network.
IEEE 802.16e standard reasonable development space resources on the basis of OFDM OFDMA, the technology combination formation MIMO OFDMA system with MIMO and OFDM OFDMA can provide higher data transmission bauds.Simultaneously, because the technology of OFDM OFDMA has added guardtime at interval, has very strong anti-multipath interference performance.When multidiameter delay is protected at interval less than it; Can make system not receive the puzzlement of intersymbol interference; This just allows Single Frequency Network can be used for the wideband orthogonal fdma system, and the emission array that relies on a large amount of low power transmissions antennas to form is eliminated shadow effect, realizes covering fully.
Because the baseband system of 802.16e need be supported the MIMO technology, so must satisfy the channel width demand of 20MHz, this just means on the data link of base band need reach higher transmission speed.In baseband system; Because the input and output of coprocessor all are to dispatch with the form of packet; Packet input/output scheduling to coprocessor is a key technology place of improving transmission speed on the whole data link; Prior art realizes data packet dispatching through the parallel bidirectional bus structures, comprises receiving terminal and transmitting terminal, and data can be carried out transmitted in both directions simultaneously.Receiving terminal is handled and is sent to end interface through transmitting terminal by the internal data processing module after receiving packet, and in this process, the intact packet of inter-process resume module is promptly to end interface is sent a packet.The packet loss phenomenon possibly appear because link is unstable in this mechanism; Fail safe to transfer of data can not guarantee; And, cause the data transmission efficiency of total system low because need need often response reading and writing request to end interface constantly to end interface is sent the reading and writing request.
Summary of the invention
The technical problem that the present invention will solve provides a kind of bus scheduling device and method, to guarantee reliability of data transmission and to improve efficiency of transmission.
For solving the problems of the technologies described above; The present invention provides a kind of bus scheduling device; This device comprises receiving element and transmitting element, and receiving element receives the scheduled traffic data bag continuously after transmission is once write request to end interface; Or transmitting element is after read request is sent in the opposite end, sends to end interface packet is disposable after the processing that is accumulated to scheduled volume.
Further, receiving element comprises the reception control module and receives formation, wherein receives control module and receives the packet to the end interface transmission in order to control, it is deposited into receive in the formation, sends to inner Co-processor Module then; Receive the packet that formation receives in order to buffer memory, wait for that receiving control module sense data bag gives inner Co-processor Module;
Transmitting element comprises transmission control module and transmit queue; Wherein sending scheduled traffic data bag storage after control module will be passed through Co-processor Module and handle in order to control sets out and send in the formation; Once send to then end interface, and send handle the back packet after to the transmit queue initialization; Transmit queue, in order to the packet after the processing of buffer memory Co-processor Module, its space is enough to storing predetermined amount packet, waits disposable all the scheduled traffic data bags of reading of control module to be sent to give end interface.
Further, receiving formation and transmit queue all is the read-write isochronous queue, and in order to the packet that receives is lined up according to the mode of FIFO, wherein receiving formation in a single day has data to write, and promptly begins read operation.
Further; Receiving element also comprises handles preceding packet counter; Be used for counting depositing the packet that receives formation in, transmitting element also comprises handles back packet counter, is used for the packet that deposits transmit queue in is counted; When sending currency that control module judges this two counter and equating, be used for sending all data that read request and disposable transmission are stored in transmit queue.
Further; Adopt high speed parallel bus to connect between the bus scheduling device; Receiving element and transmitting element adopt and interrupt communication mechanism control reception and send data; Receiving element interrupts to end interface being sent the request write, and receives and sends packet to inner Co-processor Module, up to sending the packet that carries frame end; Transmitting element receives the packet after the processing, when the preceding data packet number of data packet number after the judgment processing and processing is identical, interrupts the packet after all processing of disposable transmission to end interface is sent read request.
For solving the problems of the technologies described above; The present invention also provides a kind of bus scheduling method; This end interface writes once that the request back receives the scheduled traffic data bag continuously or after end interface being sent read request, with disposable sending to end interface behind the packet after the processing that is accumulated to scheduled volume to end interface is sent.
This method may further comprise the steps:
(a) this end interface receives the packet that end interface is sent to end interface is sent the request of writing, and sends the coprocessor of giving device inside;
(b) packet after this end interface is handled inner coprocessor writes buffer memory, runs up to the scheduled traffic data bag to end interface is sent read request, and sends to end interface the scheduled traffic data bag is disposable.
Further, different components adopts high speed parallel bus to connect, and step (a) further comprises:
(a1) this end interface interrupts to end interface is sent the request write;
(a2) after this end interface is received end interface replied, begin to receive and data cached bag, the sense data bag is given inner Co-processor Module simultaneously;
(a3) when this end interface buffer memory was sky, repeating step (a1) was to (a2), up to receiving the scheduled traffic data bag;
Step (b) further comprises:
(b1) data pack buffer after this end interface will be handled is up to receiving all packets;
(b2) this end interface interrupts to end interface being sent read request, receive end interface replied after, with disposable the sending to of all packets of buffer memory to end interface.
Further, the cached data packet counting is received in the butt joint of this end interface in the step (a2); This end interface, is thought to receive all packets when the data packet number before handling the back cached data packet and handling equates to handling back cached data packet counting in the step (b2).
Compared to prior art; Bus scheduling device that the present invention introduces between different devices and method; Realized the batch of packet is received, sends in batches; Prevent that pilot process from producing the packet loss phenomenon, avoid frequently sending the reading and writing request and awaiting a response, to guarantee reliability of data transmission and to improve efficiency of transmission.
Description of drawings
Fig. 1 is the structural representation of embodiment of the invention high speed parallel bus scheduling implement device.
Fig. 2 is the state flow chart of the reception control module of apparatus of the present invention.
Fig. 3 is the state flow chart of the transmission control module of apparatus of the present invention.
Fig. 4 is the sketch map of bus scheduling method of the present invention.
Embodiment
The thought of bus scheduling device of the present invention and method is to end interface is sent request once write or read request; And after obtaining end interface replied; Need not to send read request once more or write request, receive continuously and send that packet was disposable after the scheduled traffic data bag maybe will be accumulated to the processing of scheduled volume sends to end interface to inner Co-processor Module.The advantage of this mechanism is to realize that the batch to packet receives, sends in batches, can prevent that pilot process from producing the packet loss phenomenon, avoids frequently sending the reading and writing request, improves efficiency of transmission.
The scheduled traffic data bag can be that a frame data bag also can be based on one group of packet or several packets that data characteristic is divided, and the packet number that concrete batch sends can be grasped based on concrete applicable cases flexibly.
In the practical application; Adopting to receive in batches still to send in batches also needs according to end interface is decided; Same EBI (being bus scheduling device) can adopt simultaneously and receive in batches and send in batches; Also can only adopt to receive in batches or send in batches, no matter which kind of situation can both embody advantage of the present invention.
Bus scheduling device of the present invention is an EBI; Comprise receiving element and transmitting element; Accept the unit realize receiving in batches with or transmitting element realize sending in batches, promptly receiving element to end interface is sent once write request after, receive the scheduled traffic data bag continuously; And/or transmitting element is after read request is sent in the opposite end, sends to end interface packet is disposable after the processing that is accumulated to scheduled volume.
Below mainly describe to embody to send in batches.
Bus scheduling device of the present invention comprises receiving element and transmitting element, wherein,
Receiving element sends to the Co-processor Module of device inside in order to receive the packet that end interface is sent behind the buffer memory;
Packet after transmitting element is handled through Co-processor Module in order to buffer memory is accumulated to disposable sending to end interface behind the scheduled traffic data bag.
Based on inventive concept; Can adopt the serial or parallel bidirectional bus to connect each device and realize the present invention; But the packet of considering the inventive method is imported and packet output can be carried out at times, and in order to improve resource utilization, the embodiment of the invention adopts high speed parallel bus; And introduce to interrupt communication mechanism, below be that example describes in detail to apparatus of the present invention with the high speed parallel bus.
As shown in Figure 1, each device of GSM links to each other through the high-speed parallel data/address bus, bus scheduling device of the present invention; Utilize and interrupt the scheduling that communication mechanism is realized processing data packets; The receiving element of this dispatching device comprises the reception control module and receives formation that transmitting element comprises transmission control module and transmit queue, in addition; Packet counter before receiving element is provided with and handles; Transmitting element is provided with handles back packet counter, receives formation packet that receives and the number-of-packet that transmit queue receives through checking and equates, the packet that guarantees once to send in batches all batches sends to end interface.
Wherein:
Receive control module, receive the packet that end interface is sent, it is deposited in the reception formation, send to inner Co-processor Module then in order to control; And after having sent the scheduled traffic data bag to packet counter O reset before handling;
Receive control module and write the request interruption based on the state transmission that receives formation; If receive formation is empty; (specifically refer to; When receiving control module and receive the init state signal that receives formation) then, end interface interrupts to being sent the request write, reply if end interface made read request, then send write signal to receiving formation.
Receiving formation, is a read-write isochronous queue, in order to the packet that receives, lines up according to the mode of FIFO, waits for that receiving control module gives subordinate's processing module according to calling over packet;
Be the raising input efficiency, the embodiment of the invention receives formation and adopts read-write synchronously, after data write the reception formation, promptly begins read operation, because the time difference of write operation and read operation is very little, can be similar to and thinks that this reception formation is that read-write is synchronous.After accomplishing the writing and read an of packet, receiving formation be sky, at this moment; Receiving control module interrupts to end interface being sent the request write once more; Receive end interface replied after, begin to write next packet, up to receiving the packet that has frame end mark to receiving formation.
The packet counter is used for counting depositing the packet that receives formation in before handling;
Send control module; Packet storage after will passing through Co-processor Module and handle in order to control is seted out and is sent in the formation, when packet counter after the judgment processing with handle before packet counter when equating, the interruption of transmission read request; Receive end interface replied after; Send read signal to transmit queue, once send to then, and after sending processing back packet, the transmit queue initialization is reached handling back packet counter O reset end interface;
Transmit queue; It is a read-write isochronous queue; Data in order to after inner Co-processor Module is handled are lined up according to the mode of FIFO; Once send to end interface through interrupting communication mechanism etc. control module to be sent, the space of transmit queue is enough to the data that storing predetermined batch sends, as storing frame data.
Handling back packet counter is used for the packet that deposits transmit queue in is counted.
In concrete application example; Inner Co-processor Module is that unit handles data with the packet; Receiving element in the parallel bus dispatching device of the present invention whenever sends the request once write and interrupts, and receives a packet, after the packet accumulation after transmit queue is handled inner coprocessor is cached to frame data; Send control module and send read request and interrupt, issue end interface frame data are disposable.
If a last mode that also adopts batch to send to end interface is sent packet; Then receiving control module interrupts to end interface is sent the request once write; Can all scheduled traffic data bags (like a frame) be write the reception formation; Constantly send to simultaneously inner Co-processor Module, send to next in batches by sending control module control transmit queue again end interface.
Fig. 2 is the state flow chart of reception control module of the present invention, and it is specific as follows that it receives state of a control:
After state 1, the system reset, receive control module and enter into the IDLE state;
State 2, after the initializing signal that receives formation arrives, interrupt to end interface is sent the request write, receive control module and enter into the request interrupt INT _ SEND state of writing that sends,
State 3, end interface received in the request of writing have no progeny that the high-speed bus dispatching device in this device sends packet, receive control module and get into the formation WRITE_PRE_FIFO state that receives of writing;
State 4, reception control module are lined up according to the mode of FIFO the packet that receives in receiving formation; After the data of certain byte are received in the reception formation; The reception control module enters into reads to receive formation READ_PRE_FIFO state, and counts to inner Co-processor Module and to the packet that receives according to the packet that calls over of FIFO, is read sky if receive formation; The reception control module circulates again and gets the hang of 1 to state 4; Until having sent the packet that has frame end mark, the reception control module is not redispatched and is write the request interruption, enters into the IDLE state again.
Fig. 3 is the state flow chart of transmission control module of the present invention, and it is specific as follows that it sends state of a control:
State 1: behind the system initialization, send control module and enter into idle IDLE_P state, wait for that inner Co-processor Module sends to handle packet;
State 2: after the Co-processor Module in the device is handled the packet of reception, the packet after handling is mail to the high-speed bus dispatching device, send control module and enter into the transmit queue WRITE_POST_FIFO state of writing;
The packet storage is seted out and is sent formation after the processing of state 3, high-speed bus dispatching device Co-processor Module reception internally, and packet after the processing that receives is counted; If the number-of-packet that number-of-packet and reception control module are received after the processing that receives equates, then send control module and interrupt to end interface is sent read request, enter into transmission read request interruption READ_FRAME_INT state;
State 4: reply if end interface made read request, then send control module and enter into the transmit queue READ_POST_FIFO state of reading;
The mode of packet in the transmit queue according to FIFO sent to end interface, all data in having sent transmit queue, packet sends control module and enters into the IDLE_P state again.
Bus scheduling method of the present invention; To end interface is sent request once write or read request; And after obtaining end interface replied, receive continuously and send that packet was disposable after the scheduled traffic data bag maybe will be accumulated to the processing of scheduled volume sends to end interface to inner Co-processor Module.As shown in Figure 4, this method may further comprise the steps:
Step 401: this end interface receives the packet that end interface is sent to end interface is sent the request of writing, and sends the coprocessor of giving device inside;
Step 402: the packet after this end interface is handled inner coprocessor, write buffer memory, run up to the scheduled traffic data bag to end interface is sent read request, and send to end interface the scheduled traffic data bag is disposable.
Particularly, adopt the bus scheduling method of bus scheduling device shown in Figure 2 may further comprise the steps:
Step 1, bus scheduling device interrupt to end interface is sent the request write;
Step 2, end interface received in the request of writing has no progeny that the dispatching device in this device sends packet;
Step 3, reception control module are lined up according to the mode of FIFO the packet that receives in receiving formation;
Step 4, after receiving the data of certain byte; The reception control module counts to inner Co-processor Module and to the packet that receives according to the packet that calls over of FIFO; If receive formation is empty; Repeating step 1-4 until sending the packet that has frame end mark, gets into step 5;
After step 5, Co-processor Module are handled the packet of reception, the packet after handling is mail to the high-speed bus dispatching device;
The packet storage is seted out and is sent formation after the processing that step 6, bus scheduling device will receive from Co-processor Module, and packet after the processing that receives is counted;
If the number-of-packet that number-of-packet and reception control module receive after the processing that step 7 receives equates, then, end interface interrupts to being sent read request;
If step 8 has been made read request end interface and having been replied, then the dispatching device in this device sends to the mode of the data in the transmit queue according to FIFO to end interface all data in having sent transmit queue.
Step 9, bus scheduling device the processing of a frame after packet send to after the end interface, to receiving formation and transmit queue initialization, and, wait for the packet of reception next frame to counter O reset.The whole input of packet is insensitive to the packet sequence of input; And send to the packet of output successively to end interface according to the order in transmit queue, carry out order rearrangement by the inter-process module of opposite end according to the packet sequence number in the packet header.
In practical application; Mechanism to end interface is different with the identical also possibility of bus scheduling device possibility of the present invention, but can adopt inventive concept, carries out the batch transmission to sending to corresponding data to end interface; Thereby prevent loss packet, guarantee safety of data transmission.
Apparatus of the present invention and method can be applied in the various high-speed mobile communication systems; Wherein receiving element sends the request of once writing; Receive the scheduled traffic data bag continuously; Packet after the transmitting element judgment processing with handle before data packet number when equating to end interface is sent read request, and put end mark on the packet of transmission in the end.
Compared with prior art; The present invention introduces a kind of bus scheduling device between different devices, realize the batch of packet is received, sends in batches, prevents that pilot process from producing the packet loss phenomenon; Avoid frequently sending the reading and writing request and awaiting a response, improved efficiency of transmission.Compare with the scheduling mechanism of existing parallel bidirectional bus; Though real-time is good not as the parallel bidirectional bus; But because this high speed parallel bus is applied to the scheduling to coprocessor; Real-time requires not high, handles so can make the one-way data packet scheduling fully, has improved the flexibility and the Yi Hangxing of whole system.
Claims (7)
1. bus scheduling device; This device comprises receiving element and transmitting element; It is characterized in that: receiving element is after transmission is once write request to end interface; Receive continuously the scheduled traffic data bag, or transmitting element is after read request is sent in the opposite end, sends to end interface packet after the processing that is accumulated to scheduled volume is disposable;
Receiving element comprises the reception control module and receives formation, wherein receives control module and receives the packet to the end interface transmission in order to control, it is deposited into receive in the formation, sends to inner Co-processor Module then; Receive the packet that formation receives in order to buffer memory, wait for that receiving control module sense data bag gives inner Co-processor Module;
Transmitting element comprises transmission control module and transmit queue; Wherein sending scheduled traffic data bag storage after control module will be passed through Co-processor Module and handle in order to control sets out and send in the formation; Once send to then end interface, and send handle the back packet after to the transmit queue initialization; Transmit queue, in order to the packet after the processing of buffer memory Co-processor Module, its space is enough to storing predetermined amount packet, waits disposable all the scheduled traffic data bags of reading of control module to be sent to give end interface.
2. device as claimed in claim 1 is characterized in that: receiving formation and transmit queue all is the read-write isochronous queue, and in order to the packet that receives is lined up according to the mode of FIFO, wherein receiving formation in a single day has data to write, and promptly begins read operation.
3. device as claimed in claim 1; It is characterized in that: receiving element also comprises handles preceding packet counter; Be used for counting depositing the packet that receives formation in, transmitting element also comprises handles back packet counter, is used for the packet that deposits transmit queue in is counted; When sending currency that control module judges this two counter and equating, be used for sending all data that read request and disposable transmission are stored in transmit queue.
4. like each described device in the claim 1 to 3; It is characterized in that: adopt high speed parallel bus to connect between the bus scheduling device; Receiving element and transmitting element adopt and interrupt communication mechanism control reception and send data; Receiving element interrupts to end interface being sent the request write, and receives and sends packet to inner Co-processor Module, up to sending the packet that carries frame end; Transmitting element receives the packet after the processing, when the preceding data packet number of data packet number after the judgment processing and processing is identical, interrupts the packet after all processing of disposable transmission to end interface is sent read request.
5. bus scheduling method; It is characterized in that: this end interface is once write the request back and receives scheduled traffic data bag or this end interface continuously after end interface being sent read request, with disposable sending to end interface behind the packet after the processing that is accumulated to scheduled volume to end interface is sent;
This method may further comprise the steps:
(a) this end interface receives the packet that end interface is sent to end interface is sent the request of writing, and sends the coprocessor of giving device inside;
(b) packet after this end interface is handled inner coprocessor writes buffer memory, runs up to the scheduled traffic data bag to end interface is sent read request, and sends to end interface the scheduled traffic data bag is disposable.
6. method as claimed in claim 5 is characterized in that, different components adopts high speed parallel bus to connect, and step (a) further comprises:
(a1) this end interface interrupts to end interface is sent the request write;
(a2) after this end interface is received end interface replied, begin to receive and data cached bag, the sense data bag is given inner Co-processor Module simultaneously;
(a3) when this end interface buffer memory was sky, repeating step (a1) was to (a2), up to receiving the scheduled traffic data bag;
Step (b) further comprises:
(b1) data pack buffer after this end interface will be handled is up to receiving all packets;
(b2) this end interface interrupts to end interface being sent read request, receive end interface replied after, with disposable the sending to of all packets of buffer memory to end interface.
7. method as claimed in claim 6 is characterized in that: the cached data packet counting is received in the butt joint of this end interface in the step (a2); This end interface, is thought to receive all packets when the data packet number before handling the back cached data packet and handling equates to handling back cached data packet counting in the step (b2).
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| CN102685077B (en) * | 2011-03-16 | 2015-04-29 | 腾讯科技（深圳）有限公司 | Method and device for processing network packets |
| CN103064898B (en) * | 2012-12-17 | 2016-12-28 | 华为技术有限公司 | Affairs locking, unlocking method and device |
| CN106302372A (en) * | 2015-06-12 | 2017-01-04 | 中兴通讯股份有限公司 | Network media stream packet receiving method, Apparatus and system |
| CN107766268A (en) * | 2017-10-27 | 2018-03-06 | 郑州云海信息技术有限公司 | Interruption sending method, device, system, equipment and the storage medium of storage device |
| CN108303669B (en) * | 2018-03-09 | 2020-08-14 | 宁波三星医疗电气股份有限公司 | Method for improving meter calibration efficiency of intelligent electric meter |
| CN109086232A (en) * | 2018-07-26 | 2018-12-25 | 郑州云海信息技术有限公司 | A kind of method and device of issued transaction |
| CN112054923B (en) * | 2020-08-24 | 2023-08-18 | 腾讯科技（深圳）有限公司 | Service request detection method, equipment and medium |
| CN112949247B (en) * | 2021-02-01 | 2022-05-20 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN115150218A (en) * | 2021-03-30 | 2022-10-04 | 广东博智林机器人有限公司 | Serial communication method, device and system for upper computer and driver |
| CN115361347A (en) * | 2022-08-18 | 2022-11-18 | 山东新华医疗器械股份有限公司 | Communication method, device and medium of CT (computed tomography) equipment |
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| CN1407768A (en) * | 2001-09-02 | 2003-04-02 | 深圳市中兴通讯股份有限公司上海第二研究所 | Device and method for group continuous transfer of multi-team data |
| CN101101699A (en) * | 2007-07-30 | 2008-01-09 | 当代天启技术（北京）有限公司 | Method and apparatus for data collection and transmission |
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