CN101489053B - Video image rotating system - Google Patents
Video image rotating system Download PDFInfo
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- CN101489053B CN101489053B CN2008100704841A CN200810070484A CN101489053B CN 101489053 B CN101489053 B CN 101489053B CN 2008100704841 A CN2008100704841 A CN 2008100704841A CN 200810070484 A CN200810070484 A CN 200810070484A CN 101489053 B CN101489053 B CN 101489053B
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Abstract
A video image rotating system includes an analog video input interface and an analog video output interface, and an image processing device connecting the analog video input interface and the analog video output interface. An original video input signal is accessed to the analog video input interface. A video signal output from the analog video output interface is accessed to a display device. The input analog video signal is transferred by the image processing device to a standard ITU-656 digital video signal, stored in an outer static memory through some transformation logic, read by the outer static memory according to a certain order, and converted to an orthogonal rotated standard ITU-656 digital video signal after passing a main chip and stacking a synchronizing signal of the digital video, finally output after a video coder converts the signal to the analog video signal. The invention has advantages that the system of the invention effectively expands the display application of the existing graphic display, employs the prior display at the market without customizing a special purpose display to satisfy a specified environment and a specified application demand.
Description
[technical field]
The invention relates to the method for a kind of display device or shows signal, be meant a kind of video image rotating system especially.
[background technology]
FPGA (Field Programmable Gate Array) is a field programmable gate array, occur as a kind of semi-custom circuit in application-specific integrated circuit (ASIC) (ASIC) field, both solve the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.The use of FPGA is very flexible, can produce different circuit functions with a slice FPGA by different programming datas.FPGA has obtained extensive use in various fields such as communication, data processing, network, instrument, Industry Control, military affairs and Aero-Space.
As shown in Figure 1, the internal data of the existing image that shows on display flows to directly directly importing analog video output interface 10 from analog video input interface 1.In some special application field, in order to obtain better display effect, the rotation of display quadrature need be shown sometimes.For example: former horizontal vertical ratio is 16: 9 a display, in order vertically can to show more information, with this display clockwise or be rotated counterclockwise 90 °, becomes 9: 16 display modes.When display clockwise or after being rotated counterclockwise demonstration, if the picture signal of input is still followed original data flow mode, promptly remain unchanged, we saw so is exactly clockwise or is rotated counterclockwise 90 ° image, can't satisfy the demand of watching like this.
[summary of the invention]
Technical problem to be solved by this invention is to provide a kind of video image rotating system, and the video image of former input is rotated back output accordingly according to the direction of display rotation, to adapt to the needs that final display shows.
The present invention solves the problems of the technologies described above by the following technical programs: a kind of video image rotating system, comprise analog video input interface and analog video output interface, the original video input signal inserts described analog video input interface, the vision signal of analog video output interface output inserts display device, comprise that also one is connected in the image processing apparatus between analog video input interface and the analog video output interface, described image processing apparatus comprises Video Decoder, field programmable gate array chip, first static memory, second static memory, and video encoder
The analog video input interface is converted into analog signal through Video Decoder the data image signal input field programmable gate array chip of ITU656 form, field programmable gate array chip deposits the digital video signal content of input respectively in chip outer first static memory and second static memory according to the content of parity field, at the scene under the effect of the inner synchronizing signal that produces of programmable gate array chip, field programmable gate array chip is mapped to corresponding address with graph data according to postrotational coordinate by first static memory outside the chip and second static memory again and reads, the ITU-656 data format that is packaged as standard in the interpolation behind the synchronous head signal exports video encoder to, video encoder changes into analog video signal with the ITU-656 digital video signal that receives again and exports to the analog video output interface, finish the rotation processing process of a video image
Described field programmable gate array chip software module comprises the phase-locked loop clock module; The synchronizing signal separation module; The main logic module; The static memory control module,
Described phase-locked loop clock module: the hardware module that carries for field programmable gate array chip inside, 2 clock outputs will be produced after the phase-locked conversion of 27MHz system clock of input, one is the synchronous points clock synchronous with output image data, and it two is that 108MHz clock after the 27MHz quadruple is as the input of the clock of static memory control module;
Described synchronizing signal separation module: the analog video input interface is embedded with capable field sync signal through the data image signal of the ITU656 form that Video Decoder transforms, this module with this row field sync signal by separating in the packet, offer the main logic module then as synchronizing datum signal, and count at the capable field sync signal in each two field picture simultaneously, the standard of differentiating input picture this moment by counting is pal or ntsc system, and this signal provided gives the main logic module;
The main logic module: the synchronizing signal separation module is notified current signal for pal or ntsc standard, the main logic module is corresponding pattern (pal or ntsc) with the output signal format configuration, while is down synchronous the parity field signal, and the output signal form is alignd with input signal format.Carry out map addresses according to the postrotational coordinate of image when reading, what read is exactly through postrotational view data.The main logic module is carried out read-write operation by operation static memory control module to the outer static memory chip of sheet,
The static memory control module generates the read-write operation sequential of first static memory and second static memory outside the sheet under the control of 108MHz master clock.
The present invention further is specially:
Described main logic module is output as the pal standard if receive the pal standard signal, if receive the ntsc standard signal, then exports the ntsc standard.
Described main logic module writes first static memory with the field picture data of input when the odd field signal, simultaneously by reads image data in second static memory, view data with input when the even field signal writes second static memory, simultaneously read view data, and so forth operation by first static memory.
The advantage of video image rotating system of the present invention is: the video image rotation technique that the present invention is based on general fpga chip, between inputted video image and output video image, insert an image processing module, adopt the vhdl language to carry out the design of FPGA conversion logic, the standard I TU-656 digital video signal of input is deposited in the outer sram cache of sheet by certain converter logic, again in a certain order by reading in the outer sram cache of sheet, again through being superimposed with the synchronizing signal of digital video in the sheet, the postrotational standard I TU-656 digital video signal of output orthogonal,, video coding chip rotates back output accordingly according to the direction of display rotation after being converted into the video image that analog video signal output is about to former input, to adapt to the needs that final display shows, image can normally be watched.
This video image rotating system has effectively been expanded the display application of existing graphic alphanumeric display, need not customize special-purpose display, adopt existing on the market display, just can satisfy the demand of specific environment application-specific, adopt the scheme flexibility and reliability of fpga chip, be convenient to the upgrading expansion.
[description of drawings]
The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is existing video transmission process block diagram.
Fig. 2 is the hardware connection layout of video image rotating system of the present invention.
Fig. 3 is the software module block diagram of video image rotating system of the present invention.
[embodiment]
Seeing also Fig. 1, is the hardware connection layout of video image rotating system of the present invention, is to insert an image processing apparatus 20 between original analog video input interface 1 and analog video output interface 10.Image processing apparatus 20 comprises Video Decoder 22, FPGA (field programmable gate array) chip 23, flash memory (FLASH) 24, data buffering chip 25, debug port 26, first static memory (SRAM) 27, second static memory 28, and video encoder 29.
The original video input signal inserts described analog video input interface 1 place, the vision signal of analog video output interface 10 outputs inserts display device, analog video input interface 1 is connected to fpga chip 23 by Video Decoder 22, fpga chip 23 is connected to analog video output interface 10 by video encoder 29 again, wherein fpga chip 23 is by I2C1 and I2C2 bus difference control of video decoder 22 and video encoder 29, in addition, the exchanges data between fpga chip 23 and Video Decoder 22 and the video encoder 29 is undertaken by ITU656_IN and ITU656_OUT data channel.Also be connected with first static memory 27, second static memory 28 and data buffering chip 25 on this fpga chip 23, this data buffering chip 25 connects debug port 26 simultaneously.Wherein I2C (Inter-Integrated Circuit) is an internal integrate circuit bus.
Behind the hardware that adopts this video image rotating system, data flow is, analog video input interface 1 is converted into analog signal through Video Decoder 22 the data image signal input fpga chip 23 of ITU656 form, fpga chip 23 deposits the digital video signal content of input respectively in chip outer first static memory 27 and second static memory 28 according to the content of parity field, under the effect of the fpga chip 23 inner synchronizing signals that produce, fpga chip 23 is mapped to corresponding address with graph data according to postrotational coordinate by first static memory 27 outside the chip and second static memory 28 again and reads, the ITU-656 data format that is packaged as standard in the interpolation behind the synchronous head signal exports video encoder 29 to, video encoder 29 changes into analog video signal with the ITU-656 digital video signal that receives again and exports to analog video output interface 10, finishes the rotation processing process of a video image.
Wherein flash memory 24, data buffering chip 25, and debug port 26 is configuration modules of fpga chip 23, because fpga chip 23 is based on the chip that SRAM technology is made, therefore after power down, can not keep the program of programming, need chip is reconfigured after powering at every turn, wherein serial flash 24 is used for preserving the configuration file of FPGA, and data buffering chip 25 is used for debug port 26 and fpga chip are kept apart, and prevents that debug port 26 chance failures from causing fpga chip 23 to burn.In the present embodiment, it is the data buffering chip of 74hc244 that data buffering chip 25 adopts model.
See also Fig. 3, be the concrete software module block diagram that comprises in the fpga chip 23, comprise 4 part: PLL (phase-locked loop) clock module; The synchronizing signal separation module; The main logic module; The SRAM control module.
Pll clock module: the hardware module that carries for fpga chip inside, be mainly used to and produce 2 clock outputs after the phase-locked conversion of 27MHz system clock of input, one is the synchronous points clock synchronous with output image data, and it two is that 108MHz clock after the 27MHz quadruple is as the input of the clock of SRAM control module.
The synchronizing signal separation module: analog video input interface 1 is embedded with capable field sync signal through the data image signal of the ITU656 form that Video Decoder 22 transforms, the function of this module is by separating in the packet, to offer the main logic module as synchronizing datum signal with this row field sync signal (odd parity field signal).And count at the capable field sync signal in each two field picture simultaneously, differentiate at this moment by counting that the standard of input picture is pal or ntsc system, and this signal provided give the main logic module.
The main logic module: the synchronizing signal separation module is notified current pal (the Phase Alternating Line that is, the quadrature amplitude balance line-by-line inversion) or ntsc (National Television System Committee, NTSC) signal of standard, the main logic module is corresponding pattern with the output signal format configuration, if receive the pal standard signal, be output as the pal standard,, then export the ntsc standard if receive the ntsc standard signal.While is down synchronous synchronizing signal odd's (parity field signal), the output signal form is alignd with input signal format, when odd field signal (odd=1), these field picture data are write first static memory 27, be reads image data in second static memory 28 by other a slice simultaneously, view data is write second static memory 28 when even field signal (odd=0), simultaneously read view data, and so forth operation by first static memory 27.Carry out map addresses according to the postrotational coordinate of image when reading, what so read is exactly through postrotational view data.The main logic module is carried out read-write operation by operation SRAM control module to the outer static memory chip of sheet.
The SRAM control module generates the read-write operation sequential of first static memory 27 and second static memory 28 outside the sheet under the control of 108MHz master clock.
By above-mentioned hardware plan and software scenario, during operation, only need the original video input signal is inserted analog video input interface 1 place, and the outputting video signal of video output interface 10 is inserted display device, just can be at the video pictures of watching on the display device after rotating through.
Though more than described the specific embodiment of the present invention; but being familiar with those skilled in the art is to be understood that; our described specific embodiment is illustrative; rather than be used for qualification to scope of the present invention; those of ordinary skill in the art are in the modification and the variation of the equivalence of doing according to spirit of the present invention, all should be encompassed in the scope that claim of the present invention protects.
Claims (3)
1. video image rotating system, comprise analog video input interface and analog video output interface, the original video input signal inserts described analog video input interface, the vision signal of analog video output interface output inserts display device, it is characterized in that: comprise that one is connected in the image processing apparatus between analog video input interface and the analog video output interface, described image processing apparatus comprises Video Decoder, field programmable gate array chip, first static memory, second static memory, and video encoder
The analog video input interface is converted into analog signal through Video Decoder the data image signal input field programmable gate array chip of ITU656 form, field programmable gate array chip deposits the digital video signal content of input respectively in chip outer first static memory and second static memory according to the content of parity field, under the effect of the synchronizing signal that chip internal produces, field programmable gate array chip is mapped to corresponding address with graph data according to postrotational coordinate by first static memory outside the chip and second static memory again and reads, the ITU-656 data format that is packaged as standard in the interpolation behind the synchronous head signal exports video encoder to, video encoder changes into analog video signal with the ITU-656 digital video signal that receives again and exports to the analog video output interface, finish the rotation processing process of a video image
Described field programmable gate array chip software module comprises the phase-locked loop clock module; The synchronizing signal separation module; The main logic module; The static memory control module,
Described phase-locked loop clock module: the hardware module that carries for field programmable gate array chip inside, 2 clock outputs will be produced after the phase-locked conversion of 27MHz system clock of input, one is the synchronous points clock synchronous with output image data, and it two is that 108MHz clock after the 27MHz quadruple is as the input of the clock of static memory control module;
Described synchronizing signal separation module: the analog video input interface is embedded with capable field sync signal through the data image signal of the ITU656 form that Video Decoder transforms, this module with this row field sync signal by separating in the packet, offer the main logic module then as synchronizing datum signal, and count at the capable field sync signal in each two field picture simultaneously, the standard of differentiating input picture this moment by counting is pal or ntsc system, and this signal provided gives the main logic module;
The main logic module: the synchronizing signal separation module is notified current signal for pal or ntsc standard, the main logic module is corresponding pattern with the output signal format configuration, while is down synchronous the parity field signal, the output signal form is alignd with input signal format, carry out map addresses according to the postrotational coordinate of image when reading, what read is exactly through postrotational view data, and the main logic module is carried out read-write operation by operation static memory control module to the outer static memory chip of sheet
The static memory control module generates the read-write operation sequential of first static memory and second static memory outside the sheet under the control of 108MHz master clock.
2. video image rotating system as claimed in claim 1 is characterized in that: described main logic module is output as the pal standard if receive the pal standard signal, if receive the ntsc standard signal, then exports the ntsc standard.
3. video image rotating system as claimed in claim 1, it is characterized in that: described main logic module writes first static memory with the field picture data of input when the odd field signal, simultaneously by reads image data in second static memory, view data with input when the even field signal writes second static memory, simultaneously read view data, and so forth operation by first static memory.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102148927B (en) * | 2010-12-16 | 2012-10-03 | 四川川大智胜软件股份有限公司 | Method of designing video camera capable of rotating pictures |
| CN105719616B (en) * | 2014-12-05 | 2018-08-17 | 南京视威电子科技股份有限公司 | A kind of vertical screen drive system and vertical screen driving method |
| CN106326141A (en) * | 2015-06-16 | 2017-01-11 | 中兴通讯股份有限公司 | Data caching method and device |
| CN105007152A (en) * | 2015-07-23 | 2015-10-28 | 柳州一合科技有限公司 | Distributing method of synchronizing signal |
| CN105141875A (en) * | 2015-08-24 | 2015-12-09 | 中国航空无线电电子研究所 | Universal television signal generation device |
| CN106371790A (en) * | 2016-10-12 | 2017-02-01 | 深圳市捷视飞通科技股份有限公司 | FPGA-based double-channel video multi-image segmentation display method and device |
| CN111414282B (en) * | 2019-01-04 | 2023-11-21 | 致茂电子(苏州)有限公司 | Data ordering conversion device and display testing system and testing method applying same |
| CN111064880A (en) * | 2020-03-17 | 2020-04-24 | 深圳市中科先见医疗科技有限公司 | Image acquisition device and artificial retina in-vitro device |
| CN113691741A (en) * | 2021-07-20 | 2021-11-23 | 上海安路信息科技股份有限公司 | Display method and device for video image rotation |
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