CN101482841B - Debugging apparatus and method for embedded system - Google Patents
Debugging apparatus and method for embedded system Download PDFInfo
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- CN101482841B CN101482841B CN2008100024481A CN200810002448A CN101482841B CN 101482841 B CN101482841 B CN 101482841B CN 2008100024481 A CN2008100024481 A CN 2008100024481A CN 200810002448 A CN200810002448 A CN 200810002448A CN 101482841 B CN101482841 B CN 101482841B
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Abstract
The present invention provides a debugging device of embedded system and a debugging method thereof. The embedded system reads an opening program from a flash memory by an embedded processor through a flash memory interface. The debugging device comprises a memory transmission interface, a data storing module, a data control module and a display module. The memory transmission interface is connected with the flash memory interface for storing the data received by the memory transmission interface in the data storing module. The data control module determines whether the data transmitted in the data bus of flash memory interface is stored in the data storing module according to whether the data control signal in the flash memory interface is triggered. The display module is used for displaying the data stored in the data storing module. The data generated by the opening state of embedded system can be outputted and displayed for detecting the reason of problem in the embedded system and debugging according to the invention.
Description
Technical field
The present invention relates to a kind of apparatus for debugging, particularly a kind of apparatus for debugging of embedded system and debug method.
Background technology
Computer system is inner owing to be provided with a Basic Input or Output System (BIOS) (BIOS), this BIOS have to computer system hardware carry out one the start self test program (Power-on self-test:POST), and this test procedure can be at all designated code of each test point exporting specific I/O port (as I/OPORT 80h) to, and this code all has its corresponding failure cause.
Therefore for the debug of the BIOS of computer system, the present practice is PPCI or the ISA interface that is connected in computer plate by Debug Card, this Debug Card provides display circuit, and when BIOS carries out the start self test program and hardware when making a mistake, Debug Card can be obtained the code of the corresponding test point of this faulty hardware in the self test program by the interface that connects, and this code is presented at the display circuit of Debug Card, so that the related personnel can learn the computer hardware fault by the code that Debug Card shows, to carry out debug.
But for embedded system (Embedded System), its inner structure has BIOS unlike computer system, thus embedded system remove stagger the time the method that there is no as described above the mode of computer debug carry out.Moreover the processor in the embedded system, can be inconsistent because of the interface that each tame processor uses, so for being full of difficulty and challenge in the performance history of whole embedded system.
Though and the applied embedded system of Marvell PXA320 processor can be carried out step-by-step debugging by the RS-232 transmission manner at present, but this mode only be with present embedded system performed to instruction be shown in a display interface, yet for debug and can't learn the position that embedded system hardware breaks down by the instruction that shows.
Summary of the invention
Technical matters to be solved by this invention, be to provide a kind of apparatus for debugging and debug method of embedded system, the data that the embedded system open state can be produced are exported demonstration, to learn the former of the inner generation problem of embedded system thereby to carry out debug.
In order to solve the problems of the technologies described above, according to a kind of scheme of the present invention, a kind of apparatus for debugging of embedded system is provided, embedded system reads a boot program to carry out a boot program by a flash interface (data flashinterface) from a flash memory (flash memory) by a flush bonding processor, this flash interface belongs to serial transmission interface (serial interface), and this serial transmission interface comprises a control bus of transmission of control signals and a data bus of transmission memory address and memory data, this apparatus for debugging comprises: be connected in a memory transmission interface of this flash interface, and be used for receiving the data that this flash interface transmits; Be connected in a data memory module of this memory transmission interface, in order to store the data that this memory transmission interface receives; Be connected in a Data Control module of this memory transmission interface, and the data controlling signal in this flash interface is when triggering, store the data transmitted in this data bus of this flash interface in this data memory module, and to identify the data of being transmitted in this data bus be storage address or memory data; And a display module that is connected in this Data Control module, export the data that show in this data memory module in order to the control that receives this Data Control module.
In order to solve the problems of the technologies described above, according to another kind of scheme of the present invention, a kind of debug method of embedded system is provided, this embedded system reads a boot program to carry out a boot program by a flash interface (data flashinterface) from a flash memory (flash memory) by a flush bonding processor, this flash interface belongs to serial transmission interface (serial interface), this debug method comprises: when this embedded system is carried out this boot program, provide an apparatus for debugging to judge whether the data controlling signal in this flash interface triggers; When being judged as when triggering, store data that the data bus in this flash interface transmitted in a data memory module by this apparatus for debugging; Next the data that this data memory module stores of encoding; Then output through coded data to a display module to show.
In order to solve the problems of the technologies described above, according to another scheme of the present invention, a kind of debug method of embedded system is provided, this embedded system reads a boot program to carry out a boot program by a flash interface (data flashinterface) from a flash memory (flash memory) by a flush bonding processor, this flash interface belongs to serial transmission interface (serial interface), and this serial transmission interface comprises a control bus of transmission of control signals and a data bus of transmission memory address and memory data, and this debug method comprises: provide an apparatus for debugging to be connected in this flash interface and to judge whether this flash interface is idle; When this flash interface was idle, this apparatus for debugging triggered a Debug Card program detection signal and gives this embedded system; The data bus of this apparatus for debugging output storage address to this flash interface; This apparatus for debugging judges that the memory data in this flash interface reads control signal and whether triggers; When this memory data read control signal and triggers, this apparatus for debugging was stored data on the data bus of this flash interface in a data memory module, and to identify the data of being transmitted in this data bus be storage address or memory data; Next the data that this data memory module stores of encoding; Output shows to a display module through coded data then.
Therefore by above-mentioned embodiment, whether the present invention can read data that data bus transmits on the flash interface of embedded system by apparatus for debugging, and can have the mode of triggering to confirm whether data that data bus transmitted on the flash interface can be used to storage and use to carry out debug by data controlling signal.
Above general introduction and ensuing detailed description and accompanying drawing all are to reach mode, means and the effect that predetermined purpose is taked in order to further specify the present invention.And relevant other purpose of the present invention and advantage will be set forth in follow-up explanation and accompanying drawing.
Description of drawings
Fig. 1 is the functional-block diagram of apparatus for debugging of the embedded system of a preferred embodiment of the present invention;
Fig. 2 is the process flow diagram of debug method of the present invention;
Fig. 3 is the debug process flow diagram when the present invention is directed to the embedded system start; And
Fig. 4 is the debug process flow diagram that the present invention initiatively reads the embedded system internal data.
Wherein, description of reference numerals is as follows:
10 embedded systems
11 flush bonding processors
13 flash memories
15 peripheral devices
17 flash interfaces
20 apparatus for debugging
21 memory transmission interface
23 Data Control modules
25 data memory modules
27 debug output interfaces
29 display modules
Embodiment
The invention provides an apparatus for debugging comes an embedded system is carried out debug, so that embedded system on stream can be by the debug mode, with the correlated results of data, address and the condition of hardware of learning embedded system when start, and solve the problem that is met with in the hardware development process by these data.The present invention reads the inner result of starting shooting and carrying out of embedded system by apparatus for debugging, and shows this processing result by output, and allows the debug personnel be carried out debug.
See also Fig. 1, this embodiment is the functional-block diagram of the apparatus for debugging of embedded system of the present invention.The described apparatus for debugging 20 of present embodiment is connected in an embedded system 10, relevant execution result when allowing apparatus for debugging 20 can read embedded system 10 start smoothly, when having at least one test point, the main usefulness of test point to mean embedded system 10 starts, the boot program design of this embedded system 10 is recorded in the memory location of embedded system 10 inner settings at the execution result of wanting the debug part.For example embedded system 10 is in start process, boot program can be set the value of a memory location with each peripheral device execution result of special record in flash memory when carrying out test point so that in the flash memory particular memory address be used for storing the hardware state (as whether normal) of corresponding peripheral device.Therefore apparatus for debugging 20 can read institute's memory storing data in these embedded system 10 inner particular memory address by the interface that is compatible to embedded system 10, and the data that read promptly can be used to the debug use.
Embedded system 10 of the present invention is by flush bonding processor 11, flash memory 13, peripheral device 15 and flash interface (Data Flash Interface; DFI) 17 main members such as grade are formed, and only illustrate at this, because according to the different designs demand of embedded system 10, embedded system 10 still may comprise other hardware component.Use flash interface 17 to be connected so that the data transmission channel of internal system to be provided in the embedded system 10 with flush bonding processor 11, flash memory 13, peripheral device 15.And this flash interface 17 uses the technology of serial transmission interface (serial interface) to transmit data, comprise the control bus that transmits data controlling signal and the data bus (Data Bus) of transmission memory address and memory data, wherein control bus is meant storage address control line (LLA, LUA) in order to the transmission memory address control signal, memory data reads control line (DF_OE), memory data writes control line (DF_WE) in order to transmission memory data read-write control signal, and a Debug Card program detection line (Debug_Card_Detect) is given embedded system 10 in order to allow apparatus for debugging 20 can export a Debug Card program detection signal; Data bus then comprises a data line and a time clock line at least.Data line in the data bus is that transmission memory address or memory data then are according to having or not signal triggering to do difference in the control bus.
And in embedded system 10, flash memory 13 storage boot programs, flush bonding processor 11 reads to carry out a boot program by the boot program in 17 pairs of flash memories 13 of flash interface, whether flush bonding processor 11 carries out initialized action to peripheral device 15 in the start implementation, normal to learn present condition of hardware.And boot program can return the execution result of specific start project implementation when carrying out to test point and be stored in the particular memory address place that sets in the flash memory 13 in implementation.
Consult Fig. 1 once more, apparatus for debugging 20 comprises a memory transmission interface 21, a Data Control module 23, a data memory module 25, a debug output interface 27 and a display module 29.Memory transmission interface 21 is compatible to the flash interface (DFI) 17 of embedded system 10, can be used to receive and transmits control bus in the flash interface 17 and the data on the data bus; Data memory module 25 is connected in memory transmission interface 21, can be for storing the data that received by memory transmission interface 21; Data Control module 23 is connected in memory transmission interface 21, data memory module 25 and debug output interface 27, and the relevant treatment computing of data read, data transmission, data storage, digital coding, data decode and data presentation etc. is provided; Debug output interface 27 can be used to the result of Data Control module 23 is exported to computer system in order to external connection one computer system (figure is slightly), and by the further analyzing and processing of computer system powerful operation capacity; Display module 29 is connected in Data Control module 23 by debug output interface 27, is used for the result output of Data Control module 23 is shown that display module 29 can be the seven-segment display module of long number demonstration.
Because the flash memory 13 of embedded system 10 stores the execution result of the test point of boot program, as long as therefore for apparatus for debugging 20, can read the start execution result of being stored in the flash memory 13, the data that read can be handled for debug and be used.And mainly be by flash interface 17 for the data transmission of embedded system 10 inside, also be that the start execution result stored in the flash memory 13 is by flash interface 17 transmission, so the data that can be transmitted by the flash interface 17 that reads embedded system 10 of the described apparatus for debugging 20 of present embodiment obtain the related data for the debug use.
See also Fig. 2, and simultaneously with reference to figure 1, Fig. 2 is the process flow diagram of debug method of the present invention, execution in step is as follows:
Apparatus for debugging 20 reads the data that flash interface 17 is transmitted by memory transmission interface 21, as step S201, the data that apparatus for debugging 20 storages are read are in data memory module 25, as step S203, follow the data in the Data Control module 23 deal with data memory modules 25, as step S205, this step process mode mainly be the mode by decoding data in the data memory module 25 can be reduced into can be for the raw data of debug interpretation, and this raw data encoded for the output data of the brain system interpretation that can show and power; The output data that output was at last handled through Data Control module 23, as step S207, this output data can export display module 29 to and show or export to the computer system analysis by debug output interface 27, therefore the treatment effect that promptly can reach debug of the demonstration or the analysis of computer system by display module 29.
Next further specify, when embedded system 10 was carried out in start, how apparatus for debugging 20 carried out a debug program, saw also Fig. 3 also in the lump with reference to figure 1, and wherein Fig. 3 is the debug process flow diagram when the present invention is directed to the embedded system start, and execution in step is as follows:
At first open apparatus for debugging 20 and carry out initialization action, apparatus for debugging 20 enters idle standby mode afterwards, as step S301, and when embedded system 10 is carried out boot program, the Data Control module 23 of apparatus for debugging 20 judges whether the data controlling signal of flash interface 17 is triggered, as step S303, then getting back to step S301 when being judged as not continues to carry out, and when being judged as when being, then further judge it is the storage address control signal (LLA that belongs in the data controlling signal, LUA) trigger, as step S305, or belong to memory data read-write control signal (DF_OE in the data controlling signal, DF_WE) trigger, as step S313.
When step S305 is judged as when being, then represent on the data bus of flash interface 17 this moment to transmit data be to belong to storage address, 23 meetings of Data Control module are storage address with the transmission data identification of the data bus of flash interface 17, and be stored in data memory module 25, as step S307.
When step S313 is judged as when being, then represent on the data bus of flash interface 17 this moment to transmit data be to belong to memory data, 23 meetings of Data Control module are memory data with the transmission data identification of the data bus of flash interface 17, and be stored in data memory module 25, as step S315.
After step S307 and S315, storage address and data in the Data Control module 23 reading of data memory modules 25, and these digital coding are become can be for the output data of output demonstration, as step S309, to output to display module 29 through coded data afterwards shows, as step S311, Data Control module 23 output data that brain is handled that also storage address in the data memory module 25 can be become with digital coding to power in addition, and export to computer system by debug output interface 27.
Wherein Fig. 3 is when step S307 and S315 execution end, this moment, apparatus for debugging stored a partial data (including storage address and memory data) of embedded system 10 transmission flash memories 13, and present embodiment can judge also when execution in step S307 and S315 whether these data are can be for removing the data that misinterpretation is used, for example the storage address of these data is judged and the test point of boot program is specified is stored in storage address in the flash memory 13 when identical through Data Control module 23, can assert then that these data belong to can also just can be stored in these data in the data memory module 25 for the useful data of debug.
And when also having other to supply the data of debug, then get back to step S303 and repeat aforesaid steps flow chart, till all can all be stored in the data memory module 25 for the data of debug.
The embodiment of earlier figures 3 is when embedded system 10 is carried out the boot program process, from the flash interface 17 of embedded system 10, obtain can interpretation the start related data carry out debug, yet the present invention also can be after embedded system 10 be finished start, the related data (as the hardware state value) that initiatively reads embedded system 10 inside is to carry out the debug interpretation, as shown in Figure 4 and in the lump with reference to figure 1, wherein Fig. 4 is the debug process flow diagram that the present invention initiatively reads the embedded system internal data, and execution in step is as follows:
When apparatus for debugging 20 is in standby mode, apparatus for debugging 20 judges whether the flash interface 17 of embedded system 10 is idle, as step S401, this step judgment mode can judge that the data bus of flash interfaces 17 have or not data transmission by Data Control module 23, when there is no data transmission, can assert flash interface 17 be in idle.
When step S401 is judged as when being, apparatus for debugging 20 is sent signal with the Debug Card program detection signal in the flip-flop storage interface, as step S403, so that can preparing to carry out memory data according to the Debug Card program detection signal that receives, embedded system 10 reads action, the storage address that the obtains data bus to the flash interface 17 is wanted in apparatus for debugging 20 output afterwards, as step S405, this storage address of wanting to obtain be in the embedded system 10 in the address of flash memory 13 stored hardware state values, and this moment, embedded system 10 can obtain the storage address that apparatus for debugging 20 provides by the data bus in the flash interface 17.
Apparatus for debugging 20 judges that the memory data of the flash interface 17 of embedded system 10 reads control signal and whether triggers then, as step S407, when being judged as when being, represent that promptly the memory data that embedded system 10 has received storage address and triggered flash interface 17 reads control signal, embedded system 10 reads the data of this storage address in flash memory 13 by the data bus of flash interface 17, and the apparatus for debugging 20 of this moment reads the data in the data bus of flash interface 17, and be stored in the data memory module 25, as step S409, the data that this step S409 is stored are and export the hardware state Value Data of wanting to obtain in the storage address among the step S405.
Next the Data Control module 23 of apparatus for debugging 20 is by the hardware state Value Data in the reading of data memory module 25 and to its coding, and as step S411, and the data that output encoder is crossed show to display module 29, as step S413.Same Data Control module 23 also can be encoded into the hardware state Value Data in the data memory module 25 output data that the brain of can powering is handled, and exports to computer system by debug output interface 27.
In sum, the apparatus for debugging 20 that previous embodiment provided can carry out debug for embedded system 10, and because the flash interface 17 of embedded system 10 belongs to serial transmission interface, there is no special-purpose address wire and data line but take the mode of common transmission line to transmit, so for the certain degree of difficulty of having of debug.Therefore present embodiment is by a judgment mechanism, the signal kinds that the data controlling signal of judging earlier flash interface 17 has triggerless and a triggering is (storage address control signal or memory read write control signal) why, and then obtain and discern Gong debug data on the data bus in the flash interface 17 smoothly according to this judged result, and this can be contained storage address or the memory datas of embedded system 10 start flow processs for the debug data, or the present condition of hardware of embedded system 10.
And the apparatus for debugging 20 of present embodiment is in that obtain can be for after the debug data, be these data of codified and exported and be shown in display module 29 or export to the interpretation analysis that computer system is done the rear end, therefore by debug mode of the present invention can solve in the performance history of embedded system 10 can't normal boot-strap problem.
Yet, the above-mentioned accompanying drawing that discloses, explanation, only be embodiments of the invention, the those skilled in the art can do other all improvement according to above-mentioned explanation, and these changes still belong in the scope of invention spirit of the present invention and appending claims.
Claims (20)
1. the apparatus for debugging of an embedded system, it is characterized in that, this embedded system reads a boot program to carry out a boot program by a flash interface from a flash memory by a flush bonding processor, this flash interface belongs to serial transmission interface, and this serial transmission interface comprises the control bus that transmits data controlling signal and a data bus of transmission memory address and memory data, and this apparatus for debugging comprises:
One memory transmission interface is connected in this flash interface, receives the data that this flash interface transmits;
One data memory module is connected in this memory transmission interface, in order to store the data that this memory transmission interface receives;
One Data Control module, be connected in this memory transmission interface, and the data controlling signal in this flash interface is when triggering, store the data transmitted in this data bus of this flash interface in this data memory module, and to identify the data of being transmitted in this data bus be storage address or memory data; And
One display module is connected in this Data Control module, exports the data that show in this data memory module in order to the control that receives this Data Control module.
2. the apparatus for debugging of embedded system as claimed in claim 1 is characterized in that, this memory transmission interface is compatible to this flash interface.
3. the apparatus for debugging of embedded system as claimed in claim 2, it is characterized in that, this Data Control module judges whether the storage address control signal in this data controlling signal triggers, if be judged as is that then this Data Control module becomes the data of storage address with the data identification of being transmitted in this data bus, and this storage address is stored in this data memory module.
4. the apparatus for debugging of embedded system as claimed in claim 3, it is characterized in that, this Data Control module judges whether the memory data read-write control signal in this data controlling signal triggers, if being judged as is that then this Data Control module becomes memory data with the data identification of being transmitted in this data bus, and this memory data is stored in this data memory module.
5. the apparatus for debugging of embedded system as claimed in claim 4, it is characterized in that, this Data Control module becomes this storage address of being stored in this data memory module and this memory data decoding processing can be for the raw data of debug interpretation, and this raw data is encoded into meets this display module data presented.
6. the apparatus for debugging of embedded system as claimed in claim 5 is characterized in that, this boot program is set with a test point at least, for the initialized execution result of this boot program of record.
7. the apparatus for debugging of embedded system as claimed in claim 6 is characterized in that, whether the initialized execution result of this boot program is tested normally for the peripheral device in this embedded system.
8. the apparatus for debugging of embedded system as claimed in claim 6 is characterized in that, this raw data is the initialized execution result of this boot program that this test point write down.
9. the apparatus for debugging of embedded system as claimed in claim 1 is characterized in that, also comprises:
One debug output interface is connected in this Data Control module, gives a computer system in order to the data that the control that receives this Data Control module is exported in this data memory module.
10. the debug method of an embedded system, it is characterized in that, this embedded system reads a boot program to carry out a boot program by a flash interface from a flash memory by a flush bonding processor, this flash interface belongs to serial transmission interface, and this serial transmission interface comprises the control bus that transmits data controlling signal and a data bus of transmission memory address and memory data, and this debug method comprises:
When this embedded system is carried out this boot program, provide an apparatus for debugging to be connected in this flash interface and to judge whether the data controlling signal in this flash interface triggers;
When being judged as when triggering, store data that this data bus transmitted in this flash interface in a data memory module by this apparatus for debugging, and to identify the data of being transmitted in this data bus be storage address or memory data;
The data that this data memory module stores of encoding; And
Output shows to a display module through coded data.
11. the debug method of embedded system as claimed in claim 10, it is characterized in that, judge that whether data controlling signal in this flash interface triggers is by judging whether the storage address control signal in this data controlling signal triggers, if being judged as is then the data identification of being transmitted in this data bus to be become storage address, and this storage address is stored in this data memory module.
12. the debug method of embedded system as claimed in claim 11, it is characterized in that, judge that whether data controlling signal in this flash interface triggers is by judging whether the memory data read-write control signal in this data controlling signal triggers, if being judged as is then the data identification of being transmitted in this data bus to be become memory data, and this memory data is stored in this data memory module.
13. the debug method of embedded system as claimed in claim 12, it is characterized in that, before the data that this data memory module stores of encoding, be that earlier this storage address of being stored in this data memory module and this memory data are decoded into can be for the raw data of debug interpretation.
14. the debug method of embedded system as claimed in claim 13 is characterized in that, coding is this raw data to be encoded into meet this display module data presented.
15. the debug method of embedded system as claimed in claim 14 is characterized in that, this boot program is set with a test point at least, for the initialized execution result of this boot program of record.
16. the debug method of embedded system as claimed in claim 15 is characterized in that, whether the initialized execution result of this boot program is tested normally for the peripheral device in this embedded system.
17. the debug method of embedded system as claimed in claim 16 is characterized in that, this raw data is the initialized execution result of this boot program that this test point write down.
18. the debug method of embedded system as claimed in claim 10 is characterized in that, also comprises:
Export data to a computer system that this data memory module is stored by a debug output interface.
19. the debug method of an embedded system, it is characterized in that, this embedded system reads a boot program to carry out a boot program by a flash interface from a flash memory by a flush bonding processor, and this flash interface belongs to serial transmission interface, and this debug method comprises:
Provide an apparatus for debugging to judge whether this flash interface is idle;
When this flash interface was idle, the Debug Card program detection signal that this apparatus for debugging triggers in this flash interface was given this embedded system, reads action so that this embedded system is carried out memory data according to this Debug Card program detection signal;
This apparatus for debugging output storage address is to a data bus of this flash interface;
This apparatus for debugging judges that the memory data in this flash interface reads control signal and whether triggers;
When this memory data read control signal and triggers, this apparatus for debugging was stored data on the data bus of this flash interface in a data memory module;
The data that this data memory module stores of encoding; And
Output shows to a display module through coded data.
20. the debug method of embedded system as claimed in claim 19 is characterized in that, also comprises:
Export data to a computer system that this data memory module is stored by a debug output interface.
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| CN103186431B (en) * | 2011-12-28 | 2015-11-25 | 英业达股份有限公司 | The aided analysis method of system mistake and device thereof |
| CN104991801A (en) * | 2015-07-06 | 2015-10-21 | 青岛海信宽带多媒体技术有限公司 | Bootloader debugging information acquisition method, device and system |
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| CN2681220Y (en) * | 2004-01-19 | 2005-02-23 | 上海环达计算机科技有限公司 | System starting and testing board for embedded system |
| CN1713142A (en) * | 2004-06-15 | 2005-12-28 | 华为技术有限公司 | Outputting method of starting information for embedded computer system |
| CN101095119A (en) * | 2004-02-09 | 2007-12-26 | 大陆-特韦斯贸易合伙股份公司及两合公司 | Device and method for analyzing embedded systems for safety-critical computer systems in motor vehicles |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2681220Y (en) * | 2004-01-19 | 2005-02-23 | 上海环达计算机科技有限公司 | System starting and testing board for embedded system |
| CN101095119A (en) * | 2004-02-09 | 2007-12-26 | 大陆-特韦斯贸易合伙股份公司及两合公司 | Device and method for analyzing embedded systems for safety-critical computer systems in motor vehicles |
| CN1713142A (en) * | 2004-06-15 | 2005-12-28 | 华为技术有限公司 | Outputting method of starting information for embedded computer system |
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