CN101471744B

CN101471744B - Method, device and system for implementing HSPA channel encoding and decoding

Info

Publication number: CN101471744B
Application number: CN2007103043780A
Authority: CN
Inventors: 耿贵杰
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2007-12-27
Filing date: 2007-12-27
Publication date: 2011-08-31
Anticipated expiration: 2027-12-27
Also published as: CN101471744A

Abstract

The invention provides a method for implementing the high-speed packet access (HSPA) channel encoding/decoding operation, and a device and a system thereof. By storing the processed data in the same Buffer, the method, the device and the system can increase the processing cycle of bit scrambling/descrambling operation and reduce the storage space required for the (HSPA) channel encoding/decoding operation in the prior art. By altering the bit scrambling and interleaving operation and the bit descrambling and de-interleaving operation, the method, the device and the system achieve the effect of reducing the storage space required for the (HSPA) channel encoding/decoding operation in the prior art; and ensure the optimized use of the required space and time resources.

Description

Method, device and system for realizing HSPA channel coding and decoding

Technical Field

The present invention relates to the field of mobile communications technologies, and in particular, to a method, an apparatus, and a system for implementing HSPA channel coding and decoding.

Background

HSPA (High-Speed Packet Access) is a technology proposed by 3GPP that can provide a data rate much higher than that which can be supported by existing 3GPP Release99 WCDMA (Wideband Code division multiple Access, Wideband CDMA, Wideband Code division multiple Access), including HSDPA (High Speed downlink Packet Access) and HSUPA (High Speed uplink Packet Access); the HSDPA can realize the speed as high as 14.4Mbit/s on a downlink, and realizes more efficient scheduling and faster retransmission by new adaptive modulation and coding and transferring part of the wireless interface control function from a wireless network controller to a base station; HSUPA can achieve rates up to 5.76Mbit/s in the uplink.

HSDPA is taken as an example for explanation, and certainly, HSUPA is the same as the principle thereof, and is not described herein again. HSDPA is an important technology for improving downlink capacity and data traffic rate in third generation mobile communications, and is a major breakthrough of 3GPP Release5 to R99/R4, and performance such as high throughput, small delay, and high peak data rate of downlink data traffic can be achieved by using the HSDPA technology. The HSDPA is backward compatible with R99 and R4, and an operator can smoothly upgrade according to the requirement of network construction development without influencing the existing user. HSDPA is applicable to three different modes, WCDMA FDD (Frequency Division Duplex), UTRA TDD (Terrestrial Radio Access, Time Division Duplex) and TD-SCDMA (Time Division synchronous code Division multiple Access).

In order to support HSDPA, in WCDMA FDD, UTRA TDD, and TD-SCDMA systems, an HS-DSCH (high speed downlink shared channel) channel is added to carry high speed downlink service data. The processing flow of HS-DSCH of WCDMA FDD, UTRA TDD and TD-SCDMA is basically similar. The following description will take the HS-DSCH processing of TD-SCDMA system as an example.

In TD-SCDMA system, HS-DSCH adopts Turbo coding, there is only one transport block in one Transmission Time Interval (TTI), the coding process is shown in fig. 1, and the detailed description of the coding step can refer to 3GPP TS25.222, which is not described herein again; while the implementation of bit collection and interleaving of the physical layer HARQ (hybrid automatic repeat request) part in fig. 1 is based on the implementation process of the TS25.222 standard flow as shown in fig. 2:

the following takes a partial receiving end processing procedure as an example: firstly, the received physical channel data is subjected to de-channel mapping and de-constellation rearrangement and then enters de-interleaving processing; the deinterleaving part, the Buffer2 and the control module 2 in fig. 2 complete the deinterleaving process together; the specific implementation of the deinterleaving process is performed by controlling the generation of the write and read addresses of Buffer2, and the specific address generation mechanism is as follows: address jump write Buffer2, where the address sequence is read from Buffer2, and taking the deinterleaving process of QPSK (Quadrature Phase Shift Keying) as an example, the data structure/organization of Buffer2 is as shown in fig. 3, where the reading of the address sequence from Buffer2 means that the output data sequence of the deinterleaving process is read from address 0 (0 row and 0 column of the interleaving matrix), address 1 (0 row and 1 column of the interleaving matrix), and address 2 (0 row and 2 column of the interleaving matrix) of Buffer2, and correspondingly, the address jump write Buffer2 means that the address x (m row and n column of the interleaving matrix) of Buffer2 is sequentially written in the interleaving permutation mode; the data which completes the de-interleaving processing enters the de-bit collection processing after the bit descrambling; the Buffer1, the decoding bit collecting part and the control module 1 in the figure together complete the decoding bit collecting process, similar to the realization of the deinterleaving process, the decoding bit collecting is completed by controlling the writing-in and reading-out address generation of the Buffer1, and mainly comprises two address generating mechanisms of address sequence writing-in Buffer1, address jump reading-out from Buffer1 and address jump writing-in Buffer1, and address sequence reading-out from Buffer 1; and finally, the data which completes the bit decoding collection process is sent to the subsequent HARQ process.

The address generating mechanisms of the de-interleaving process and the de-bit collecting process are completely independent from each other, so that the independent serial completion of the bit descrambling process is ensured. Obviously, in the above processing procedure from deinterleaving to bit de-interleaving, since the deinterleaving, bit descrambling and bit de-scrambling are controlled, processed and stored independently, 2 buffers are required to complete the deinterleaving and bit de-scrambling respectively before and after the bit de-scrambling, the bit de-scrambling between 2 buffers can be completed at one time, when the HSDPA reaches the maximum transmission capacity, the data amount required to be stored is 2 TTIs (14043 × 2 is 28086 bits), and the maximum number of processing cycles of the bit de-scrambling is 1 TTI (14043 clock cycles). This results in that the transmitting end needs to store a large amount of data before and after bit scrambling, while the receiving end needs to store a large amount of data before and after bit descrambling. Specifically, hard bits (0 or 1) are needed to be stored at the transmitting end, so that the needed storage amount is 28086/8 ≈ 3511 byte; in order to improve the decoding quality, soft bits (i.e. one soft bit occupies a plurality of bit spaces) are used at the receiving end, so that the required storage capacity is larger, and the design and operation cost of the system is increased virtually.

Disclosure of Invention

In view of this, the present invention provides a method, an apparatus and a system for implementing HSPA channel coding and decoding, which can reduce the requirement of the HSPA channel coding and decoding process on the storage space, thereby effectively reducing the system cost.

In order to solve the above problems, the technical scheme provided by the invention is as follows:

a method of implementing HSPA channel coding, the method comprising:

the bit collection processing is completed by controlling the generation of the write address and the read address of the cache, and data is written into the cache according to the generated write address;

controlling the data to be read out from the cache by using a read-out address generated by bit collection processing, and then carrying out bit scrambling processing;

the interleaving processing is completed by controlling the generation of the write address and the read address of the cache, and the data subjected to the bit scrambling processing is written back to the cache according to the generated write address;

and controlling the data to be read out from the buffer by using a read address generated by the interleaving processing, and then sending the interleaved data out.

Correspondingly, the writing and reading of the data of the bit collection process specifically includes:

writing the data into the cache according to the address jump rule, and reading the data from the cache according to the address sequence rule before scrambling the bits.

Correspondingly, the writing and reading of the data by the interleaving process specifically includes:

after bit scrambling processing, the processed data is written back to the cache according to the address sequence rule, and then the data is read out from the cache according to the address hopping rule.

Correspondingly, the bit scrambling process further includes:

expanding a processing period of bit scrambling;

and allocating the expanded periodic interval to the operation of reading out data from the cache and the operation of writing the data subjected to the bit scrambling processing back to the cache.

Correspondingly, the processing period of the bit scrambling is expanded to be twice of the original processing period, and the expanded period is divided into two parts;

reading out data from the cache for bit scrambling in the first part period after the expansion;

and temporarily storing the data after bit scrambling and writing the data back to the cache in the second part period after the expansion.

Correspondingly, the temporary storage specifically comprises:

after bit scrambling is carried out on the data, whether the previous group of data which is subjected to bit scrambling and stored is written back to the cache or not is judged, if yes, the previous group of data is covered and stored by the group of data which is subjected to bit scrambling, and then bit scrambling is carried out on the next group of data continuously; otherwise, pausing bit scrambling and repeating the judging steps.

An apparatus for implementing HSPA channel coding, comprising a first control module, a second control module and a bit scrambling module, the apparatus further comprising: a third control module and a cache; wherein,

the first control module is used for controlling the generation of a write-in address of the cache and writing data into the cache according to the generated write-in address;

the third control module is used for controlling the generation of a read address of the cache, controlling the read data from the cache to complete bit collection processing by using the generated read address, controlling the bit scrambling module to complete bit scrambling, controlling the generation of a write address of the cache, and writing the data after the bit scrambling back to the cache;

the second control module is used for controlling the generation of the read address of the cache, reading data from the cache according to the generated read address to complete interleaving processing, and then sending the data out.

Correspondingly, the bit scrambling module further comprises: a first expansion module and a first distribution module; wherein,

the first spreading module is used for spreading a processing period of bit scrambling;

the first distribution module is used for distributing the cycle interval expanded by the first expansion module to the third control module to control the bit scrambling module to read out data from the cache, and distributing the cycle interval expanded by the first expansion module to the third control module to control the bit scrambling module to write back the data subjected to bit scrambling processing to the cache.

Correspondingly, the bit scrambling module is further used for judging whether the previous group of data subjected to bit scrambling and stored is written back to the cache after the data is subjected to bit scrambling, if so, covering the previous group of data with the group of data subjected to bit scrambling and storing, and then continuing to perform bit scrambling on the next group of data; otherwise, bit scrambling is suspended and the aforementioned determination operation is repeated.

A method of implementing HSPA channel decoding, the method comprising:

the de-interleaving processing of the received data is completed by controlling the generation of the write address and the read address of the cache, and the data is written into the cache according to the generated write address;

reading data from the cache by using a read address generated by the deinterleaving processing, and then performing bit descrambling processing;

the generation of the write address and the read address of the cache is controlled to complete bit decoding collection processing, and data subjected to bit descrambling processing is written back into the cache according to the generated write address;

and controlling the data to be read out from the buffer by using the read address generated by the bit decoding collection processing, and then sending out the data subjected to the bit decoding collection processing.

Correspondingly, the writing and reading of the deinterleaved data specifically includes:

writing the data into the cache according to the address jump rule, reading the data from the cache according to the address sequence rule before descrambling the bits.

Correspondingly, the writing and reading of the data of the solution bit collection process specifically includes:

after bit descrambling processing, writing the processed data back to the cache according to the address sequence rule, and then reading the data from the cache according to the address hopping rule.

Correspondingly, the bit descrambling process further comprises:

expanding the processing period of bit descrambling;

and allocating the expanded periodic interval to the operation of reading data from the cache and the operation of writing the data subjected to the bit descrambling back to the cache.

Correspondingly, the processing period of bit descrambling is expanded to be twice of the original processing period, and the expanded period is divided into two parts;

reading data from the cache for bit descrambling in the expanded first partial period;

and temporarily storing the data after the bit descrambling and writing the data back to the cache in the expanded second partial period.

Correspondingly, the temporary storage specifically comprises:

after bit descrambling is carried out on the data, whether the previous group of data which is subjected to bit descrambling and stored is written back to the cache is judged, if so, the previous group of data is covered by the group of data subjected to bit descrambling and stored, and then bit descrambling is continuously carried out on the next group of data; otherwise, descrambling the pause bit and repeating the judging steps.

An apparatus for implementing HSPA channel decoding, comprising a fourth control module, a sixth control module and a bit descrambling module, the apparatus further comprising: a fifth control module and a cache; wherein,

the fourth control module is used for controlling the generation of a write-in address of the cache and writing data into the cache according to the generated write-in address;

the fifth control module is used for controlling the generation of a read address of the cache, controlling the read data from the cache to complete de-interleaving processing by using the generated read address, controlling the bit descrambling module to complete bit descrambling, controlling the generation of a write address of the cache, and writing the data which completes the bit descrambling back to the cache;

the sixth control module is used for controlling the generation of the read address of the cache, reading data from the cache according to the generated read address to complete bit decoding collection processing, and then sending the data out.

Correspondingly, the bit descrambling module further comprises: a second expansion module and a second allocation module; wherein,

the second spreading module is used for spreading a processing period of bit scrambling;

the second distributing module is used for distributing the cycle interval expanded by the second expanding module to the fifth control module to control the bit descrambling module to read data from the cache, and distributing the cycle interval expanded by the second expanding module to the fifth control module to control the bit descrambling module to write the data subjected to bit descrambling back to the cache.

Correspondingly, the bit descrambling module is further used for judging whether the previous group of data subjected to bit descrambling and stored is written back to the cache after the data is subjected to bit descrambling, if so, covering the previous group of data with the group of data subjected to bit descrambling and stored, and continuing to perform bit descrambling on the next group of data; otherwise, descrambling the pause bit and repeating the judging steps.

A method of implementing HSPA channel coding comprising:

in the sending direction, the generation of the jump writing address and the jump reading address of the cache is controlled, and the received data is written into the cache according to the jump writing address rule to complete bit collection processing; reading data from the cache according to a jump reading address rule to complete interleaving processing, and then sending out; receiving the data processed by interleaving, carrying out bit scrambling processing and then sending out;

in the receiving direction, carrying out bit descrambling processing on the received signal; controlling the generation of jump write-in address and jump read-out address of the buffer memory, and writing the data processed by bit descrambling into the buffer memory according to the jump write-in address rule to complete de-interleaving processing; and reading data from the cache according to a jump reading address rule to complete bit decoding collection processing, and then sending out.

A system for implementing HSPA channel coding comprising: an encoding device and a decoding device; the encoding device is used for controlling the generation of jump write-in addresses and jump read-out addresses of the cache in the sending direction, and writing the received data into the cache according to a jump write-in address rule to finish bit collection processing; reading data from the cache according to a jump reading address rule to complete interleaving processing, and then sending out; receiving the data processed by interleaving, carrying out bit scrambling processing and then sending out;

the decoding device is used for carrying out bit descrambling processing on the received signal in the receiving direction; controlling the generation of jump write-in address and jump read-out address of the buffer memory, and writing the data processed by bit descrambling into the buffer memory according to the jump write-in address rule to complete de-interleaving processing; and reading data from the cache according to a jump reading address rule to complete bit decoding collection processing, and then sending out.

It can be seen that, by adopting the method, the device and the system of the invention, the processing period of bit scrambling/descrambling is increased by storing the processed data in the same Buffer, and the storage space required in the existing HSPA channel coding and decoding processing is reduced; the purpose of reducing the storage space required in the existing HSPA channel coding and decoding process is realized by changing the processing sequence of the bit scrambling and interleaving process and the bit descrambling and deinterleaving process, and the optimal use of the required space and time resources is realized.

Drawings

Fig. 1 is a schematic diagram of the encoding process of HS-DSCH in a TD-HSDPA system in the prior art;

fig. 2 is a schematic diagram of an implementation flow of bit collection to interleaving of a physical layer HARQ part of a conventional TS25.222 standard flow;

fig. 3 is a schematic diagram of a data structure of a Buffer in a conventional QPSK deinterleaving process;

FIG. 4 is a schematic flow chart of the method of example 1 of the present invention;

FIG. 5 is a schematic block diagram of an apparatus of embodiment 2 of the present invention;

FIG. 6 is a schematic flow chart of the method of embodiment 3 of the present invention;

FIG. 7 is a schematic block diagram of an apparatus of embodiment 4 of the present invention;

FIG. 8 is a schematic block diagram of a system in which

embodiments

1 and 2 of the present invention are combined;

FIG. 9 is a schematic flow chart of the method of example 5 of the present invention;

FIG. 10 is a schematic block diagram of a system of embodiment 6 of the present invention;

fig. 11 is a schematic block diagram of the inside of the system of embodiment 6 of the present invention.

Detailed Description

The basic idea of the invention is to use a time-to-space method to reduce the storage space required in the existing HSPA channel coding and decoding process by increasing the processing period of bit scrambling/descrambling; the purpose of reducing the storage space required in the prior HSPA channel coding and decoding processing is realized by changing the processing sequence of bit scrambling and interleaving and bit descrambling and deinterleaving.

In order that those skilled in the art will better understand the present invention, the method, apparatus and system of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in fig. 4, the method for implementing HSPA channel coding provided in embodiment 1 of the present invention takes HSDPA as an example, and the method includes:

step 401: the bit collection processing is completed by controlling the generation of the write address and the read address of the cache, and data is written into the cache according to the generated write address;

step 402: controlling the data to be read out from the cache by using a read-out address generated by bit collection processing, and then carrying out bit scrambling processing;

step 403: the interleaving processing is completed by controlling the generation of the write address and the read address of the cache, and the data subjected to the bit scrambling processing is written into the cache according to the generated write address;

step 404: and controlling the data to be read out from the buffer by using a read address generated by the interleaving processing, and then sending the interleaved data out.

Specifically, the data processed by the HARQ process is sent to a bit collection process part; the bit collection process is completed by controlling the generation of the write-in and read-out addresses of the Buffer, and the received data processed by the HARQ is written into the Buffer according to the generated write-in address rule, namely, the write-in part of the bit collection process is completed; the bit collection process is followed by a bit scrambling process part, data is read from the Buffer by utilizing a read address rule generated by the bit collection (namely, the read part for the bit collection is completed, the bit collection process is completed), and the data is written into the Buffer after the processing of the bit scrambling process part, and is also a data writing part for the interleaving process; the bit scrambling process is followed by an interleaving process part, namely, the interleaving process is completed by controlling the generation of read addresses of the buffers; specifically, the interleaving processing is completed by using the generated read address of the Buffer to control the read-out of the bit-scrambled data from the Buffer, and then the data is sent out to execute the subsequent operation.

It is noted that, in the above embodiment, the specific mechanism for writing and reading data in the bit collection process is: writing the received data into a cache according to an address hopping rule, and reading the data from the cache according to an address sequence rule before scrambling bits; correspondingly, the data writing and reading mechanism of the interleaving process is as follows: after bit scrambling processing, the processed data is written into a buffer memory (also an address writing part of interleaving processing) according to an address sequence rule, and then the data is read out from the buffer memory according to an address jumping rule.

In addition, the invention also provides a stop mechanism introduced in the processing part of bit scrambling; the read address generation and the write address generation of the Buffer are controlled, and a bit scrambling stop mechanism and the like are cooperatively controlled, so that bit scrambling read data and bit scrambling write data can be displayed in the same Buffer without mutual interference; in particular, the method comprises the following steps of,

firstly, expanding the processing period of bit scrambling by two times, then dividing the processing period of two times into two, and distributing the two processing periods to a control part and a bit scrambling processing part of bit scrambling at intervals, wherein the two processing periods are respectively used for generating Buffer read-out addresses of bit scrambling input data, generating Buffer write-in addresses of bit scrambling output data and processing periods and stop-wait periods of the bit scrambling processing part: reading data from the Buffer and then carrying out bit scrambling on the data in a first part of the expanded period; temporarily storing the data after bit scrambling in a second part of the extended period and then writing the data back to the Buffer; the embodiment of the invention proposes that only one address is adopted to store a group of data, namely after the current data is subjected to bit scrambling, whether the data which is subjected to bit scrambling and stored in the address at the previous time is written back to a Buffer is judged, if so, the data subjected to the bit scrambling at the current time is stored in the address and covers the data stored at the previous time to wait for being written back to the Buffer, and then the data read out next time is subjected to bit scrambling; otherwise, pausing bit scrambling for the data read next time, and repeating the judging process until the bit scrambling for the data can be continued. Finally, the generating cycle of the Buffer reading address of the bit scrambling input data is corresponding to the processing cycle of the bit scrambling processing part, and the generating cycle of the writing address of the bit scrambling output data is corresponding to the stop waiting cycle of the bit scrambling processing part, thereby finishing the bit scrambling process at intervals.

The encoding processing method of this embodiment is mainly used for processing a part of transmitting ends of data in the base station, and is not described herein again.

Obviously, in the processing procedure of the above embodiment, only one Buffer is needed before and after bit scrambling to complete the bit collection, bit scrambling and interleaving procedures in sequence, and the bit scrambling procedure in the period needs to complete the bit collection, bit scrambling and interleaving procedures with the Buffer twice; in this way, in HSDPA2.8Mbps, the maximum transmission capacity allows the amount of data to be stored for one TTI (14043 bits), and the maximum number of processing cycles of the bit scrambling process for two TTIs (14053 × 2: 28083 clock cycles), i.e., the amount of memory required for the processing side of the prior art is reduced by half.

Based on the above thought, as shown in fig. 5, embodiment 2 of the present invention further provides a device for implementing HSPA channel coding, which also takes HSDPA as an example; the apparatus comprises a first control module 501, a second control module 502 and a bit scrambling module 503, and further comprises: a third control module 504 and a cache 505; wherein,

the first control module 501 is configured to control generation of a write address of the cache 505, and write data into the cache 505 according to the generated write address; the third control module 504 is configured to control generation of a read address of the cache, control reading of data from the cache 505 by using the generated read address to complete bit collection processing, control the bit scrambling module 503 to complete bit scrambling, control generation of a write address of the cache, and write the data subjected to bit scrambling into the cache 505; the second control module 502 is configured to control generation of a read address of the buffer 505, read data from the buffer 505 according to the generated read address to complete interleaving, and then send the data.

In addition, the bit scrambling module may further include: a first expansion module and a first distribution module; wherein, the first spreading module is used for spreading the processing period of bit scrambling; the first distribution module is used for distributing the cycle interval expanded by the first expansion module to the third control module to control the bit scrambling module to read out data from the cache, and distributing the cycle interval expanded by the first expansion module to the third control module to control the bit scrambling module to write back the data subjected to bit scrambling processing to the cache.

Of course, the bit scrambling module is further configured to determine whether a previous group of data subjected to bit scrambling and stored has been written back to the cache after performing bit scrambling on the data, and if so, to overwrite the previous group of data with the group of data subjected to bit scrambling and store the previous group of data, and then continue to perform bit scrambling on a next group of data; otherwise, bit scrambling is suspended and the aforementioned determination operation is repeated.

Of course, those skilled in the art will readily understand that the apparatus for implementing HSPA coding in embodiment 2 of the present invention can implement HSPA coding by the method operations in embodiment 1, and details thereof are not repeated herein.

It will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by hardware associated with program instructions, and the program is stored in a specific storage medium.

It can be seen that the method and apparatus of the present invention reduce the memory space requirement of the prior art by half by increasing the number of processing cycles of bit scrambling, and provide the system performance well.

Correspondingly, as shown in fig. 6, embodiment 3 of the present invention further provides a method for implementing HSPA channel decoding, which also takes HSDPA as an example, and includes:

step 601: the de-interleaving processing of the received data is completed by controlling the generation of the write address and the read address of the cache, and the data is written into the cache according to the generated write address;

step 602: reading data from the cache by using a read address generated by the deinterleaving processing, and then performing bit descrambling processing;

step 603: the generation of the write address and the read address of the cache is controlled to complete bit decoding collection processing, and data subjected to bit descrambling processing is written into the cache according to the generated write address;

step 604: and controlling the data to be read out from the buffer by using the read address generated by the bit decoding collection processing, and then sending out the data subjected to the bit decoding collection processing.

Specifically, the received physical channel data enters into deinterleaving processing after being subjected to preceding processing; the de-interleaving process is completed through the generation of the write-in address and the read-out address of the Buffer, and data is written into the cache according to the generated write-in address rule; reading data from the Buffer by using a read address rule (completing a bit descrambling process), then performing bit descrambling processing, and writing the processed data into the Buffer (completing a write address part of a bit decoding collection process); the read-out part of the bit decoding collection process is completed by controlling the generation of the read-out address of the Buffer, and then the bit decoding collection process is completed; and finally, the data which completes the bit decoding collection processing is sent to the HARQ processing after the processing, and the subsequent operation is executed.

In addition, in the above embodiment 3, the specific mechanism of writing and reading the deinterleaved data is: writing data into a cache according to an address hopping rule, reading the data from the cache according to an address sequence rule before bit descrambling; correspondingly, the specific mechanism for writing and reading data in the process of solving bit collection is as follows: after bit descrambling, the received data is written into a cache according to an address sequence rule (also a written address part of bit decoding collection processing), and then the data is read out from the cache according to an address jump rule.

In the embodiment, in the processing part of bit descrambling, through the introduction of a stall mechanism and the like, the read address of the Buffer is generated (data read part of the deinterleaving process), the write address of the Buffer is generated (data write part of the debt collecting process), and the stall mechanism of bit descrambling is cooperatively controlled, so that the input data and the output data of bit descrambling can use the same Buffer without mutual interference; the specific implementation mechanism is that firstly, the processing period of bit descrambling is expanded twice, then the interval of twice processing period is allocated to the bit descrambling control part and the bit descrambling processing part, the Buffer read address generation (data read part of the deinterleaving process) for bit descrambling input data and the Buffer write address generation (data write part of the deinterleaving process) for bit descrambling output data are respectively used, and the processing period and the stop-waiting period of the bit descrambling processing part are as follows: wherein the extended period is divided into two parts; reading data from the cache for bit descrambling in the expanded first partial period; and temporarily storing the data after the bit descrambling and writing the data back to the cache in the expanded second partial period. The temporary storage mode also has multiple modes, wherein one of the comparative optimization specifically comprises: after bit descrambling is carried out on the data, whether the previous group of data which is subjected to bit descrambling and stored is written back to the cache is judged, if so, the previous group of data is covered by the group of data subjected to bit descrambling and stored, and then bit descrambling is continuously carried out on the next group of data; otherwise, descrambling the pause bit and repeating the judging steps. (the specific period allocation is similar to the temporary storage operation before writing and the bit scrambling in the encoding process, and is not described again), finally, the Buffer read address generation period of the bit descrambling input data corresponds to the processing period of the bit descrambling processing part, and the Buffer write address generation period of the bit descrambling output data corresponds to the stop-wait period of the bit descrambling processing part, so that the processing of the bit descrambling part can be completed at intervals.

The decoding processing method of this embodiment is mainly used for processing of a part of receiving ends of data in a terminal, and the corresponding processing idea is similar to the processing of a part of sending in the above embodiment.

Obviously, in the above processing procedure, only 1 Buffer is needed before and after bit descrambling to complete the deinterleaving, bit descrambling and bit collecting procedures in sequence, and the bit descrambling process therebetween needs to be completed by two interactions. When the maximum transmission capacity of the hsdpa2.8mbps is high, the data amount to be stored is 1 TTI (14043 bits), and the number of processing cycles of the bit descrambling process is 2 TTIs (14043 × 2 — 28086 clock cycles) at maximum.

Also, based on the above thought, as shown in fig. 7, embodiment 4 of the present invention further provides a device for implementing HSPA channel decoding, taking HSDPA as an example; the apparatus includes a fourth control module 701, a sixth control module 702, and a bit descrambling module 703, and the apparatus further includes: a fifth control module 704 and a buffer 705; wherein,

the fourth control module 701 is configured to control generation of a write address of the cache 705, and write data into the cache 705 according to the generated write address; the fifth control module 704 is configured to control generation of a read address of the buffer, control reading of data from the buffer 705 by using the generated read address to complete de-interleaving processing, control the bit descrambling module 703 to complete bit descrambling, control generation of a write address of the buffer, and write data with the bit descrambling into the buffer 705; the sixth control module 702 is configured to control generation of a read address of the buffer 705, and read data from the buffer 705 according to the generated read address to complete bit decoding collection processing, and then send the data out.

In addition, the bit descrambling module may further include: a second expansion module and a second allocation module; wherein the second spreading module is configured to spread a processing period of bit scrambling; the second distributing module is used for distributing the cycle interval expanded by the second expanding module to the fifth control module to control the bit descrambling module to read the data subjected to the de-interleaving processing from the cache, and distributing the cycle interval expanded by the second expanding module to the fifth control module to control the bit descrambling module to write the data subjected to the bit descrambling processing into the cache.

Of course, the bit descrambling module may further be configured to determine whether a previous group of data subjected to bit descrambling and stored has been written back to the cache after performing bit descrambling on the data, if so, cover the previous group of data with the group of data subjected to bit descrambling and stored, and then continue to perform bit descrambling on a next group of data; otherwise, the pause bit is descrambled and the above judgment operation is repeated.

Of course, those skilled in the art will readily understand that the apparatus for implementing HSPA decoding in embodiment 4 of the present invention can implement HSPA decoding by the method operations in embodiment 3 described above, and details thereof are not repeated herein.

Of course, the methods and apparatuses applied to part of the transmitting end in the

embodiments

1 and 2 and the methods and apparatuses applied to part of the receiving end in the embodiments 3 and 4 are all based on the idea of using time to change space, and the purpose of reducing the storage space is achieved by increasing the number of processing cycles of bit scrambling or bit descrambling, so that the methods and apparatuses can be used independently respectively, or can be combined together to form a whole method or system for implementing HSPA coding and decoding, as shown in fig. 8, and are not described herein again.

In addition, as shown in fig. 9, embodiment 5 of the present invention further provides a method for implementing HSPA channel coding and decoding, which takes HSDPA as an example and includes:

step 901: in the sending direction, the generation of the jump writing address and the jump reading address of the cache is controlled, and the received data is written into the cache according to the jump writing address rule to complete bit collection processing; reading data from the cache according to a jump reading address rule to complete interleaving processing, and then sending out; receiving the data processed by interleaving, carrying out bit scrambling processing and then sending out;

step 902: in the receiving direction, carrying out bit descrambling processing on the received signal; controlling the generation of jump write-in address and jump read-out address of the buffer memory, and writing the data processed by bit descrambling into the buffer memory according to the jump write-in address rule to complete de-interleaving processing; and reading data from the cache according to a jump reading address rule to complete bit decoding collection processing, and then sending out.

Specifically, in the transmitting direction of the transmitting end, the data processed by the HARQ is transmitted to the bit collection processing part; the processing of bit collection is completed by controlling the generation of jump write address of Buffer, namely, data is written into Buffer by adopting an address jump mechanism, namely, the write-in part of the bit collection process is completed; it should be noted that, since the subsequent bit scrambling has been performed with a backward shift process, the data sequentially stored in the Buffer can be directly used for the subsequent interleaving process; the bit collection process is followed by the interleaving process, which is mainly completed by controlling the generation of the jumping read address of the Buffer; because the bit scrambling process which should be carried out at this point is carried out with backward shift, the interleaving process can directly process the data stored in the Buffer in the bit collecting process, thereby limiting the read address of the Buffer to be generated by adopting a hopping mechanism; the interleaving process is followed by a bit scrambling process, and the data processed by the interleaving process can be directly subjected to the bit scrambling process and then sent out to execute the subsequent operation because the processing is subjected to the post-shift processing;

in the receiving direction of the receiving end, the received physical channel data enters a bit descrambling process after being processed correspondingly in the previous process, and enters a de-interleaving process after completing the bit descrambling at one time; the specific realization of the de-interleaving process is completed by controlling the generation of the jumping write address of the Buffer, and because the subsequent bit descrambling part is moved forward, the data stored in the Buffer in sequence can be directly used for the subsequent de-bit collecting process (namely after the de-interleaving process of jumping write Buffer, the obtained sequentially stored Buffer data comprises the de-interleaving process of reading the Buffer in sequence and the de-bit collecting process of writing the Buffer in sequence in the previous scheme, so that the two processes can be omitted); the bit de-collection process is similar to the realization of the de-interleaving process, the bit de-collection is completed by controlling the generation of the jumping read address of the Buffer, here, the bit de-scrambling part is processed in advance, the bit de-collection is to directly understand the data stored in the Buffer in sequence after interleaving, thereby limiting the jumping generation mechanism of the Buffer read address; and finally, the data which completes the bit decoding collection processing is sent to the HARQ processing after the processing, and the corresponding operation is completed.

Obviously, in the above processing procedure, only 1 Buffer is needed to complete the encoding and decoding procedure in sequence. At the maximum transmission capacity of 2.8Mbps, the data amount required to be stored is 1 TTI (14043 bits), and the maximum number of processing cycles of the bit scrambling and descrambling process is 1 TTI (14043 clock cycles).

It should be noted that, in embodiment 5 of the present invention, only the processing sequence of bit scrambling and descrambling is changed, and the processing method is not changed, so that the transmitting end and the receiving end need to be used together.

Based on the above thought, as shown in fig. 10, embodiment 6 of the present invention further provides a system for implementing HSPA channel coding and decoding, taking HSDPA as an example; the system comprises: encoding means 901 and decoding means 902;

the encoding device 1001 is configured to control generation of a jump write address and a jump read address of a cache in a sending direction, and write received data into the cache according to a jump write address rule; reading out data from the buffer according to a jump reading address rule to carry out interleaving processing, and then sending out; receiving the data processed by interleaving, carrying out bit scrambling processing and then sending out;

the decoding device 1002 is configured to control generation of a buffered jump write address and a jump read address in a receiving direction, and perform bit descrambling on the received jump write address and jump read address; writing the data subjected to bit descrambling into a cache according to a jump write address rule; and reading data from the cache according to a jump reading address rule, and sending out the data after completing bit decoding collection processing.

Specifically, as shown in fig. 11, the encoding apparatus 1001 includes a control module 1, a control module 2, a Buffer, and a bit scrambling module; the control module 1 controls the bit collection processing of the data processed in the previous process, namely, the processed data is written into the Buffer by adopting a jump address mechanism; then, the control module 2 controls the address hopping mechanism to read data from the Buffer for interleaving processing; the bit scrambling module carries out bit scrambling processing on the data subjected to the interleaving processing and then sends out the data to execute subsequent operation;

the decoding device 1002 comprises, for example, a descramble module, a Buffer, a control module 3 and a control module 4; firstly, a bit descrambling module carries out bit descrambling processing on received data which is processed in advance; under the control of the control module 3, deinterleave the data subjected to the special descrambling, that is, write the data into the Buffer by adopting an address hopping mechanism; and then, under the control of the control module 4, reading data from the Buffer by adopting an address hopping mechanism, and sending the data to a subsequent module for corresponding processing after bit decoding and collecting processing.

It can be seen that, by using the methods and systems of embodiments 5 and 6 of the present invention, the processing order of bit scrambling/descrambling and interleaving is changed, so that the memory space requirement of the existing scheme is also reduced by half on the premise of not increasing the number of processing cycles of bit descrambling, and the optimal use of the required space and time resources is realized.

The disclosed embodiments are provided to enable those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope or spirit of the invention. The above-described embodiments are merely preferred embodiments of the present invention, which should not be construed as limiting the invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method for performing HSPA channel coding, the method comprising:

completing bit collection processing by controlling generation of a write address and a read address of a cache, and writing data into the cache according to the generated write address;

finishing interleaving processing by controlling the generation of the write address and the read address of the cache, and writing the data subjected to bit scrambling processing back to the cache according to the generated write address;

and controlling the data to be read out from the cache by using a read address generated by the interleaving processing, and then sending the data subjected to the interleaving processing.

2. The method according to claim 1, wherein the writing and reading of data by the bit collection process specifically comprises:

3. The method according to claim 1, wherein the interleaving data writing and reading specifically comprises:

4. The method of any of claims 1-3, wherein the bit scrambling process further comprises:

expanding a processing period of bit scrambling;

5. The method of claim 4, wherein:

expanding the processing period of bit scrambling to twice of the original processing period, and dividing the expanded period into two parts;

6. The method according to claim 5, wherein the staging specifically comprises:

7. An apparatus for implementing HSPA channel coding, comprising a first control module, a second control module and a bit scrambling module, characterized in that the apparatus further comprises: a third control module and a cache; wherein,

8. The apparatus of claim 7, wherein the bit scrambling module further comprises: a first expansion module and a first distribution module; wherein,

9. The apparatus of claim 8, wherein:

the bit scrambling module is further used for judging whether the previous group of data which is subjected to bit scrambling and stored is written back to the cache or not after the data is subjected to bit scrambling, if so, covering the previous group of data with the group of data which is subjected to bit scrambling and storing, and then continuing to perform bit scrambling on the next group of data; otherwise, bit scrambling is suspended and the aforementioned determination operation is repeated.

10. A method for performing HSPA channel decoding, the method comprising:

completing bit decoding collection processing by controlling the generation of the write address and the read address of the cache, and writing data subjected to bit descrambling back into the cache according to the generated write address;

and controlling the data to be read out from the cache by using a read address generated by the bit decoding collection processing, and then sending out the data subjected to the bit decoding collection processing.

11. The method according to claim 10, wherein the deinterleaved data writing and reading specifically comprises:

12. The method according to claim 10, wherein the writing and reading of data by the solution bit collection process specifically comprises:

13. The method of any of claims 10 to 12, wherein the bit descrambling process further comprises:

expanding the processing period of bit descrambling;

14. The method of claim 13, wherein:

expanding the processing period of bit descrambling to be twice of the original processing period, and dividing the expanded period into two parts;

15. The method according to claim 14, wherein the staging specifically comprises:

16. An apparatus for decoding HSPA channel, comprising a fourth control module, a sixth control module and a bit descrambling module, characterized in that the apparatus further comprises: a fifth control module and a cache; wherein,

17. The apparatus of claim 16, wherein the bit descrambling module further comprises: a second expansion module and a second allocation module; wherein,

18. The apparatus of claim 17, wherein:

the bit descrambling module is further used for judging whether the previous group of data subjected to bit descrambling and stored is written back to the cache or not after the data is subjected to bit descrambling, if so, covering the previous group of data with the group of data subjected to bit descrambling and stored, and continuing to perform bit descrambling on the next group of data; otherwise, descrambling the pause bit and repeating the judging steps.

19. A method for implementing HSPA channel coding and decoding, the method comprising:

HSPA channel coding using the method of any of the preceding claims 1 to 6;

HSPA channel decoding using the method of any of the preceding claims 10 to 15.

20. A system for implementing HSPA channel coding and decoding, the system comprising:

a device for performing HSPA channel coding according to any of the preceding claims 7 to 9 and a device for performing HSPA channel decoding according to any of the preceding claims 16 to 18.