CN101471744A - Method, device and system for implementing HSPA channel encode and decode - Google Patents
Method, device and system for implementing HSPA channel encode and decode Download PDFInfo
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- CN101471744A CN101471744A CNA2007103043780A CN200710304378A CN101471744A CN 101471744 A CN101471744 A CN 101471744A CN A2007103043780 A CNA2007103043780 A CN A2007103043780A CN 200710304378 A CN200710304378 A CN 200710304378A CN 101471744 A CN101471744 A CN 101471744A
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Abstract
The invention provides a method for implementing the high-speed packet access (HSPA) channel encoding/decoding operation, and a device and a system thereof. By storing the processed data in the same Buffer, the method, the device and the system can increase the processing cycle of bit scrambling/descrambling operation and reduce the storage space required for the (HSPA) channel encoding/decoding operation in the prior art. By altering the bit scrambling and interleaving operation and the bit descrambling and de-interleaving operation, the method, the device and the system achieve the effect of reducing the storage space required for the (HSPA) channel encoding/decoding operation in the prior art; and ensure the optimized use of the required space and time resources.
Description
Technical field
The present invention relates to the mobile communication technology field, relate in particular to method, the Apparatus and system of realizing HSPA channel coding and decoding.
Background technology
HSPA (High-Speed Packet Access, high-speed packet inserts) be that can providing of 3GPP proposition is higher than existing 3GPP Release99WCDMA (Wideband Code DivisionMultiple Access far away, Wideband CDMA, broadband demal multiplex (MUX) access) technology of the data rate that can support, it comprises HSDPA (high speed downlink packet access) and HSUPA (high speed uplink packet access); Wherein, HSDPA can realize the speed up to 14.4Mbit/s on down link, transfer to the base station from radio network controller by new adaptive modulation and coding and with part wave point controlled function, realized scheduling more efficiently and re-transmission more efficiently; HSUPA can realize the speed up to 5.76Mbit/s in up link.
Now be that example describes with HSDPA, HSUPA is identical with its principle certainly, does not repeat them here.HSDPA is a kind of important technology that 3G (Third Generation) Moblie improves downlink capacity and data service rate, be the key breakthrough of 3GPP Release5, utilize the HSDPA technology can realize performances such as the high-throughput of downstream data traffic, little delay and peak data rates for R99/R4.HSDPA backward compatibility R99 and R4, operator can carry out smooth upgrade according to the needs of networking development, can not impact existing user.HSDPA is applicable to WCDMA FDD (Frequency Division Duplex simultaneously, Frequency Division Duplexing (FDD)), (Terrestrial Radio Access terrestrial wireless inserts UTRA TDD, TimeDivision Duplex time division duplex) and three kinds of different modes of TD-SCDMA (Time Division SynchronousCDMA, Time Division-Synchronous Code Division Multiple Access).
In order to support HSDPA, WCDMA FDD, UTRA TDD and TD-SCDMA system have increased HS-DSCH (high speed downlink shared channel, high speed descending sharing channel) channel with carrying high-speed downstream business datum.And the handling process of the HS-DSCH of WCDMA FDD, UTRA TDD and TD-SCDMA is similar substantially.The example that is treated to the HS-DSCH of TD-SCDMA system describes below.
In the TD-SCDMA system, HS-DSCH adopts the Turbo coding, has only a transmission block in the Transmission Time Interval (TTI), and its cataloged procedure and about the detailed description of coding step, can not repeat them here referring to 3GPP TS25.222 as shown in Figure 1; And the bit collection of the physical layer HARQ among Fig. 1 (mixing automatic request retransmission) part and the realization that interweaves are based on the implementation procedure of TS25.222 normal process as shown in Figure 2:
Be described as example with part receiving terminal processing procedure below: the physical channel data that at first receives is conciliate constellation rearrangement through separating channel Mapping, enters deinterleaving then and handles; Deinterleaving part, (buffer memory) 2 of Buffer thereafter and control module 2 among Fig. 2 are finished the deinterleaving process jointly; Wherein, the specific implementation of deinterleaving process is to finish by the generation that writes and read the address of control Buffer2, concrete address generation mechanism is: the address saltus step writes Buffer2, sequence of addresses is read from Buffer2, with QPSK (Quadrature Phase Shift Keying, quarternary phase-shift keying (QPSK)) deinterleaving process is an example, data structure/organizational form of Buffer2 as shown in Figure 3, sequence of addresses is read the dateout order that is meant the deinterleaving process address 0 (0 row, 0 row of interleaver matrix) from Buffer2 from Buffer2, address 1 (0 row, 1 row of interleaver matrix), read address 2 (0 row, 2 row of interleaver matrix), corresponding therewith, the address saltus step writes Buffer2 and is meant the address x (the capable n row of the m of interleaver matrix) that writes Buffer2 according to the displacement patterns that interweaves successively; The data of finishing the deinterleaving processing enter through bit descrambling separates the bit collection processing; Buffer1 among the figure, separate bit collection part and control module 1 is finished the bit collection process of separating jointly, similar with the realization of deinterleaving process, separate bit collection and be by the generation that writes and read the address of control Buffer1 and finish, mainly contain sequence of addresses write Buffer1, address saltus step read with the address saltus step from Buffer1 write Buffer1, sequence of addresses is read two kinds of address generation mechanisms from Buffer1; Finish at last and separate the HARQ that data that bit collection handles are admitted to thereafter and handle.
The address generation mechanism that above-mentioned deinterleaving process is conciliate the bit collection process is fully separate, so just guaranteed the bit descrambling process independently serial once finish.Obviously, in above-mentioned deinterleaving in the processing procedure of separating bit collection, because deinterleaving, it is independently to control respectively that bit descrambling is conciliate the bit collection process, handle and store, therefore need 2 Buffer to finish deinterleaving respectively before and after the bit descrambling and conciliate the bit collection process, bit descrambling process between 2 Buffer then can once be finished, when HSDPA reaches maximum transfer capacity, realize that required data quantity stored is the data volume (14043 x 2=28086 bit) of 2 TTI, the processing periodicity of bit descrambling process is the data volume (14043 clock cycle) of 1 TTI to the maximum.So just make transmitting terminal need before and after bit scramble, carry out the storage of mass data, and receiving terminal need be stored lot of data before and after bit descrambling.Concrete, what need store at transmitting terminal is hard bit (0 or 1), and therefore the memory space that needs is 28086/8 ≈ 3511byte; And at receiving terminal for improving the quality of decoding, use be soft bit (i.e. a plurality of bit space of soft bit stealing), therefore need memory space is bigger, has improved the design and running cost of system virtually.
Summary of the invention
In view of this, the problem that the present invention solves provides a kind of method, Apparatus and system of the HSPA of realization channel coding and decoding, can reduce the demand of HSPA channel coding/decoding processing to memory space, thereby effectively reduce system cost.
For addressing the above problem, technical scheme provided by the invention is as follows:
A kind of method that realizes the HSPA chnnel coding, this method comprises:
Finish bit collection and handle by the generation that writes the address and read the address of buffer memory is controlled, and data are write in the buffer memory by the address that writes that produces;
Sense data from buffer memory is controlled in the address of reading that utilizes bit collection to handle generation, carries out bit scramble then and handles;
Finish interleaving treatment by the generation that writes the address and read the address of buffer memory is controlled, and the bit scramble data processed is write back in the buffer memory by the address that writes that produces;
Sense data from buffer memory is controlled in the address of reading that utilizes interleaving treatment to produce, and then the data after the interleaving treatment is sent.
Accordingly, the data of described bit collection processing write and read specifically and comprise:
By address saltus step rule data are write before buffer memory, the bit scramble again by sequence of addresses rule sense data from buffer memory.
Accordingly, the data of described interleaving treatment write and read specifically and comprise:
Bit scramble handle the back by the sequence of addresses rule with data processed write back buffer memory, again by address saltus step rule sense data from buffer memory.
Accordingly, described bit scramble is handled and is further comprised:
The processing cycle of extended bit scrambling;
All period interval after the described expansion are distributed to the operation that data after handling from the operation of buffer memory sense data with bit scramble write back buffer memory.
Accordingly, processing cycle of bit scramble is expanded to the twice in former processing cycle, and the cycle after the described expansion is divided into two parts;
First after described expansion is in the cycle, and sense data is carried out bit scramble from buffer memory;
Second portion after described expansion is in the cycle, and the data behind the temporary bit scramble also write back buffer memory with it.
Accordingly, described keeping in specifically comprises:
Data are carried out judging earlier whether the last group of data through bit scramble and preservation have been write back buffer memory behind the bit scramble, if, then cover last group of data and preservation with the data of this group behind bit scramble, continue then next group data is carried out bit scramble; Otherwise, suspend bit scramble and repeat aforementioned determining step.
A kind of device of realizing the HSPA chnnel coding comprises first control module, second control module and bit scramble module, and this device also comprises: the 3rd control module and a buffer memory; Wherein,
The address that writes that described first control module is used to control buffer memory produces, and by the address that writes that produces data is write in the buffer memory;
The address of reading that described the 3rd control module is used to control buffer memory produces, and utilize the address control sense data from buffer memory of reading that produces to finish the bit collection processing, control described bit scramble module and finish bit scramble, the address that writes of control buffer memory produces, and the data that will finish bit scramble write back buffer memory;
Described second control module is used to control the generation of reading the address of buffer memory, and finishes interleaving treatment by the address sense data from buffer memory of reading that produces, and then data is sent.
Accordingly, described bit scramble module further comprises: first expansion module and first distribution module; Wherein,
Described first expansion module is used for the processing cycle of extended bit scrambling;
Described first distribution module be used for all period interval after the expansion of described first expansion module distribute to the 3rd control module in order to the control bit scrambling module from the buffer memory sense data, and the data of distributing to after the 3rd control module is handled bit scramble in order to the control bit scrambling module write back buffer memory.
Accordingly, described bit scramble module is further used for judging earlier whether the last group of data through bit scramble and preservation are write back buffer memory after data are carried out bit scramble, if, then cover last group of data and preservation, continue then next group data is carried out bit scramble with the data of this group behind bit scramble; Otherwise, suspend bit scramble and repeat aforementioned decision operation.
A kind of method that realizes the HSPA channel-decoding, this method comprises:
Handle by the deinterleaving of finishing receiving data is controlled in the generation that writes the address and read the address of buffer memory, and data are write buffer memory by the address that writes that produces;
Sense data from buffer memory is controlled in the address of reading that utilizes deinterleaving to handle generation, carries out bit descrambling then and handles;
Separate bit collection and handle by the generation that writes the address and read the address of buffer memory being controlled finish, and the bit descrambling data processed is write back in the buffer memory by the address that writes that produces;
Utilization is separated the address of reading of bit collection processing generation and is controlled sense data from buffer memory, and the data that will separate then after bit collection is handled send.
Accordingly, the data of described deinterleaving write and read specifically and comprise:
By address saltus step rule data are write before buffer memory, the bit descrambling again by sequence of addresses rule sense data from buffer memory.
Accordingly, described data of separating the bit collection processing write and read specifically and comprise:
Bit descrambling handle the back by the sequence of addresses rule with data processed write back buffer memory, again by address saltus step rule sense data from buffer memory.
Accordingly, described bit descrambling is handled and is further comprised:
The processing cycle of extended bit descrambling;
All period interval after the described expansion are distributed to the operation that data after handling from the operation of buffer memory sense data with bit descrambling write back buffer memory.
Accordingly, processing cycle of bit descrambling is expanded to the twice in former processing cycle, and the cycle after the described expansion is divided into two parts;
First after described expansion is in the cycle, and sense data is carried out bit descrambling from buffer memory;
Second portion after described expansion is in the cycle, and the data behind the temporary bit descrambling also write back buffer memory with it.
Accordingly, described keeping in specifically comprises:
Data are carried out judging earlier whether the last group of data through bit descrambling and preservation have been write back buffer memory behind the bit descrambling, if, then cover last group of data and preservation with the data of this group behind bit descrambling, continue then next group data is carried out bit descrambling; Otherwise, suspend bit descrambling and repeat aforementioned determining step.
A kind of device of realizing the HSPA channel-decoding comprises the 4th control module, the 6th control module and bit descrambling module, and this device also comprises: the 5th control module and a buffer memory; Wherein,
The address that writes that described the 4th control module is used to control buffer memory produces, and by the address that writes that produces data is write in the buffer memory;
The address of reading that described the 5th control module is used to control buffer memory produces, and utilize the address control sense data from buffer memory of reading that produces to finish the deinterleaving processing, control described bit descrambling module and finish bit descrambling, the address that writes of control buffer memory produces, and the data that will finish bit descrambling write back buffer memory;
Described the 6th control module is used to control the generation of reading the address of buffer memory, and finishes and separate bit collection and handle by the address sense data from buffer memory of reading that produces, and then data is sent.
Accordingly, described bit descrambling module further comprises: second expansion module and second distribution module; Wherein,
Described second expansion module is used for the processing cycle of extended bit scrambling;
Described second distribution module be used for all period interval after the expansion of described second expansion module distribute to the 5th control module in order to the control bit descrambling module from the buffer memory sense data, and distribute to the data that the 5th control module is used for after the control bit descrambling module is handled bit descrambling and write back buffer memory.
Accordingly, described bit descrambling module is further used for judging earlier whether the last group of data through bit descrambling and preservation are write back buffer memory after data are carried out bit descrambling, if, then cover last group of data and preservation, continue then next group data is carried out bit descrambling with the data of this group behind bit descrambling; Otherwise, suspend bit descrambling and repeat aforementioned determining step.
A kind of method that realizes the HSPA channel coding/decoding, this method comprises:
On sending direction, the saltus step of control buffer memory writes the generation that the address is read in address and saltus step, and the data that receive are write the address rule by saltus step writes buffer memory and finish bit collection and handle; From buffer memory, read address rule sense data again and finish interleaving treatment, send then by saltus step; The data that the reception interleaving treatment is crossed carry out sending after bit scramble is handled;
On receive direction, the bit descrambling that carries out that receives is handled; The saltus step of control buffer memory writes the generation that the address is read in address and saltus step, the bit descrambling data processed is write the address rule by saltus step write buffer memory and finish deinterleaving and handle; From buffer memory, read address rule sense data again and finish and separate bit collection and handle, send then by saltus step.
A kind of system that realizes the HSPA channel coding/decoding, this system comprises: encoding apparatus and decoding apparatus; Wherein, the saltus step that described code device is used on sending direction the control buffer memory writes the generation that the address is read in address and saltus step, and the data that receive are write the address rule by saltus step writes buffer memory and finish bit collection and handle; From buffer memory, read address rule sense data again and finish interleaving treatment, send then by saltus step; The data that the reception interleaving treatment is crossed carry out sending after bit scramble is handled;
Described decoding device is used on receive direction the bit descrambling that carries out that receives being handled; The saltus step of control buffer memory writes the generation that the address is read in address and saltus step, the bit descrambling data processed is write the address rule by saltus step write buffer memory and finish deinterleaving and handle; From buffer memory, read address rule sense data again and finish and separate bit collection and handle, send then by saltus step.
As can be seen, adopt methods, devices and systems of the present invention, by the data of stores processor in same Buffer, and then increase bit and add/processing cycle of descrambling, reduce existing HSPA channel coding/decoding handle in required memory space; By the processing sequence of change bit scramble and interleaving process and bit descrambling reconciliation interleaving process, realize the purpose of memory space required during reducing existing HSPA channel coding/decoding handles, realize the optimization use of required room and time resource.
Description of drawings
Fig. 1 is the cataloged procedure schematic diagram of HS-DSCH in the TD-HSDPA system in the prior art;
Fig. 2 is that the bit collection of existing physical layer HARQ part based on the TS25.222 normal process is to the realization flow schematic diagram that interweaves;
Fig. 3 is the data structure schematic diagram of Buffer in the deinterleaving process of existing QPSK;
Fig. 4 is the method flow schematic diagram of the embodiment of the invention 1;
Fig. 5 is the schematic block diagram of the device of the embodiment of the invention 2;
Fig. 6 is the method flow schematic diagram of the embodiment of the invention 3;
Fig. 7 is the schematic block diagram of the device of the embodiment of the invention 4;
Fig. 8 is the schematic block diagram of the system that combines of the embodiment of the invention 1 and 2;
Fig. 9 is the method flow schematic diagram of the embodiment of the invention 5;
Figure 10 is the schematic block diagram of the system of the embodiment of the invention 6;
Figure 11 is the schematic block diagram of inside of the system of the embodiment of the invention 6.
Embodiment
Basic thought of the present invention is to change service time the method in space, adds by increasing bit/processing cycle of descrambling, reduce existing HSPA channel coding/decoding handle in required memory space; By the change bit scramble with interweave and the processing sequence of bit descrambling and deinterleaving, realize the purpose of memory space required during reducing existing HSPA channel coding/decoding handles.
In order to make those skilled in the art better understand the present invention, methods, devices and systems of the present invention are elaborated below in conjunction with the drawings and specific embodiments.
As shown in Figure 4, the method for the realization HSPA chnnel coding that the embodiment of the invention 1 provides is example with HSDPA, and this method comprises:
Step 401: finish bit collection and handle by the generation that writes the address and read the address of buffer memory is controlled, and data are write in the buffer memory by the address that writes that produces;
Step 402: sense data from buffer memory is controlled in the address of reading that utilizes bit collection to handle generation, carries out bit scramble then and handles;
Step 403: finish interleaving treatment by the generation that writes the address and read the address of buffer memory is controlled, and bit scramble was handled data write in the buffer memory by the address that writes that produces;
Step 404: sense data from buffer memory is controlled in the address of reading that utilizes interleaving treatment to produce, and then the data after the interleaving treatment is sent.
Concrete, will pass through the data of HARQ processing and send into the bit collection processing section; The processing of bit collection is to finish by the generation that writes and read the address of control Buffer, writes Buffer with receiving the process HARQ data processed of coming by the address rule that writes that produces, and has promptly finished the part that writes of bit collection process; After the bit collection process is the bit scramble processing section, (promptly finished the part of reading of bit collection by the address rule sense data from Buffer of reading of utilizing bit collection to produce, finished the bit collection process), after the processing through the bit scramble processing section data being write Buffer more again, also is that the data of having finished interleaving process write part simultaneously; After the bit scramble process is the interleaving treatment part, promptly finishes interleaving process by the generation of reading the address of control Buffer; Concrete, from Buffer, read the bit scramble data processed and finish interleaving treatment by the address control of reading that utilizes the Buffer that produces, then data are sent the execution subsequent operation.
It should be noted that in the above-described embodiments the data of bit collection process write and read concrete mechanism and are: the data that receive are write before buffer memory, the bit scramble again by sequence of addresses rule sense data from buffer memory by address saltus step rule; And corresponding, the data of interleaving treatment write and the mechanism of reading is: bit scramble handle the back by the sequence of addresses rule with data processed write buffer memory (address that also is interleaving treatment writes part), again by address saltus step rule sense data from buffer memory.
In addition, the present invention proposes again to have introduced Stop And Wait in the processing section of bit scramble; The address of reading by control Buffer produces and writes the address and produces, and the Stop And Wait of bit scramble carries out Collaborative Control, make bit scramble sense data and write data and be able in same Buffer, manifest, and do not disturb mutually; Concrete,
Processing cycle of twice extended bit scrambling at first, the processing cycle with twice is divided into two then, and the control section and the bit scramble processing section of bit scramble are distributed in the interval, the Buffer that is respectively applied for bit scramble input data reads the cycles such as the address produces, the Buffer of bit scramble dateout writes the processing cycle of address generation and bit scramble processing section and stop: wherein, the first in the cycle after expansion is in the cycle, and sense data is carried out bit scramble to these data then from Buffer; The second portion in the cycle after expansion is in the cycle, and the data behind the temporary bit scramble are gone in that it is write back among the Buffer then; This wherein temporary mode can have various ways, the embodiment of the invention proposes only to adopt an address to store one group of data, once whether write back among the Buffer before promptly after this carries out bit scramble to data, judging earlier through bit scramble and the data that are stored in the described address, if, the data that then storage behind this bit scramble also covered last time storage in this address write back Buffer with wait, continue then the data of reading next time are carried out bit scramble; Otherwise, suspend the data of next time reading are carried out bit scramble, repeat the process of aforementioned judgement, till can continuing that data are carried out bit scramble.It is corresponding with the processing cycle of bit scramble processing section that the Buffer that makes bit scramble import data at last reads the address generation cycle, making the address that writes of dateout of bit scramble, to produce the cycle corresponding with the cycle such as grade that stops of bit scramble processing section, can finish the bit scramble process at interval thus.
The code processing method of this embodiment is mainly used in the processing of the section data transmitting terminal in the base station, does not repeat them here.
Obviously, in the processing procedure of the foregoing description, only need before and after the bit scramble Buffer can finish bit collection, bit scramble and interleaving process in proper order, during the bit scramble process then need to finish alternately for twice with Buffer; Like this, make in the HSDPA2.8Mbps maximum transfer capacity, realize that required data quantity stored is the data volume (14043 bit) of a TTI, the processing periodicity of bit scramble process is the data volume (14053 * 2=28083 clock cycle) of two TTI to the maximum, and the processing side that is about to prior art has reduced half by required memory space.
Based on above-mentioned thought, as shown in Figure 5, the embodiment of the invention 2 provides a kind of device of the HSPA of realization chnnel coding again, is example equally with HSDPA; This device comprises first control module 501, second control module 502 and bit scramble module 503, and this device also comprises: the 3rd control module 504 and a buffer memory 505; Wherein,
The address that writes that described first control module 501 is used to control buffer memory 505 produces, and by the address that writes that produces data is write in the buffer memory 505; The address of reading that described the 3rd control module 504 is used to control buffer memory produces, and utilize the address control sense data from buffer memory 505 of reading that produces to finish the bit collection processing, control described bit scramble module 503 and finish bit scramble, the address that writes of control buffer memory produces, and the data that will finish bit scramble write buffer memory 505; Described second control module 502 is used to control the generation of reading the address of buffer memory 505, and finishes interleaving treatment by the address sense data from buffer memory 505 of reading that produces, and then data is sent.
In addition, the bit scramble module also can comprise: first expansion module and first distribution module; Wherein, described first expansion module is used for the processing cycle of extended bit scrambling; Described first distribution module be used for all period interval after the expansion of described first expansion module distribute to the 3rd control module in order to the control bit scrambling module from the buffer memory sense data, and the data of distributing to after the 3rd control module is handled bit scramble in order to the control bit scrambling module write back buffer memory.
Certainly, described bit scramble module is further used for judging earlier whether the last group of data through bit scramble and preservation are write back buffer memory after data are carried out bit scramble, if, then cover last group of data and preservation, continue then next group data is carried out bit scramble with the data of this group behind bit scramble; Otherwise, suspend bit scramble and repeat aforementioned decision operation.
Certainly, those skilled in the art understand easily, and realization HSPA apparatus for encoding can be operated by the method for the foregoing description 1 and be realized the HSPA coding in the embodiment of the invention 2, does not specifically repeat them here.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to finish by the relevant hardware of program command, and described procedure stores is in the particular memory medium.
As can be seen, adopt method and apparatus of the present invention,, memory space requirements of the prior art has been reduced half, the performance of system well is provided by increasing the processing periodicity of bit scramble.
Accordingly, as shown in Figure 6, the embodiment of the invention 3 has proposed a kind of method of the HSPA of realization channel-decoding again, also is example with HSDPA, and this method comprises:
Step 601: handle by the deinterleaving of finishing receiving data is controlled in the generation that writes the address and read the address of buffer memory, and data are write buffer memory by the address that writes that produces;
Step 602: sense data from buffer memory is controlled in the address of reading that utilizes deinterleaving to handle generation, carries out bit descrambling then and handles;
Step 603: separate bit collection and handle by the generation that writes the address and read the address of buffer memory being controlled finish, and the bit descrambling data processed is write in the buffer memory by the address that writes that produces;
Step 604: utilize the address of reading of separating bit collection processing generation to control sense data from buffer memory, the data that will separate then after bit collection is handled send.
Concrete, the physical channel data that receives enters deinterleaving and handles through after the preceding continuous processing; Wherein, finish the deinterleaving process with the generation of reading the address, data are write buffer memory by the address rule that writes that produces by the address that writes of Buffer; Address rule sense data (finishing the bit descrambling process), process bit descrambling processing then from Buffer are read in utilization, and the data after will handling again write Buffer (finishing the address part that writes of separating the bit collection process); Finish the part of reading of separating the bit collection process by the generation of reading the address of control Buffer again, and then finish the bit collection process of separating; Finish at last and separate the HARQ that data that bit collection handles are admitted to thereafter and handle, carry out subsequent operation.
In addition, in the foregoing description 3, the data of deinterleaving write and read concrete mechanism and are: by address saltus step rule data are write before buffer memory, the bit descrambling again by sequence of addresses rule sense data from buffer memory; And corresponding, the data of separating the bit collection process write and read concrete mechanism and are: behind the bit descrambling by the sequence of addresses rule with the data that receive write buffer memory (also being to separate the address part that writes that bit collection handles), again by address saltus step rule sense data from buffer memory.
In this embodiment, processing section at bit descrambling, introducing by Stop And Wait, produce (data of deinterleaving process are read part) by the address of reading simultaneously with Buffer, the address that writes of Buffer produces (data of separating the bit collection process write part), and the Stop And Wait of bit descrambling carries out Collaborative Control, makes the input data of bit descrambling and dateout be used same Buffer, and do not disturb mutually; Concrete realization mechanism is, processing cycle of twice extended bit descrambling at first, then twice is handled all period interval and distributed to bit descrambling control section and bit descrambling processing section, the Buffer that is respectively applied for bit descrambling input data reads the Buffer that the address produces (data of deinterleaving process are read part) and bit descrambling dateout and writes address generation (data of separating the bit collection process write part), and bit descrambling is handled the processing cycle of processing section and the cycle such as is stopped: wherein, the cycle after the described expansion is divided into two parts; First after described expansion is in the cycle, and sense data is carried out bit descrambling from buffer memory; Second portion after described expansion is in the cycle, and the data behind the temporary bit descrambling also write back buffer memory with it.Wherein, temporary mode also has multiple, wherein relatively a kind of of optimization specifically comprises: data are carried out judging earlier whether the last group of data through bit descrambling and preservation are write back buffer memory behind the bit descrambling, if, then cover last group of data and preservation, continue then next group data is carried out bit descrambling with the data of this group behind bit descrambling; Otherwise, suspend bit descrambling and repeat aforementioned determining step.(concrete period allocated with write before temporary operation and the bit scramble in the cataloged procedure similar, repeat no more inferior), it is corresponding with the processing cycle of bit descrambling processing section that the Buffer that makes bit descrambling import data at last reads the address generation cycle, make the Buffer of bit descrambling dateout write the address produce cycle and bit descrambling processing section stop wait the cycle corresponding, can finish bit descrambling processing partly thus at interval.
The decoding processing method of this embodiment is mainly used in the processing of the section data receiving terminal in the terminal, and it is similar to handle the processing that part sends in thinking and the foregoing description accordingly.
Obviously, in above-mentioned processing procedure, only need that 1 Buffer can finish deinterleaving in proper order, bit descrambling is conciliate the bit collection process before and after the bit descrambling, bit descrambling process therebetween then needs to finish alternately for twice.When the HSDPA2.8Mbps maximum transfer capacity, realize that required data quantity stored is the data volume (14043 bit) of 1 TTI, the processing periodicity of bit descrambling process is the data volume (14043 an x 2=28086 clock cycle) of 2 TTI to the maximum.
Equally, based on above-mentioned thought, as shown in Figure 7, the embodiment of the invention 4 provides a kind of device of the HSPA of realization channel-decoding again, is example with HSDPA; This device comprises the 4th control module 701, the 6th control module 702 and bit descrambling module 703, and its this device also comprises: the 5th control module 704 and a buffer memory 705; Wherein,
The address that writes that described the 4th control module 701 is used to control buffer memory 705 produces, and by the address that writes that produces data is write in the buffer memory 705; The address of reading that described the 5th control module 704 is used to control buffer memory produces, and utilize the address control sense data from buffer memory 705 of reading that produces to finish the deinterleaving processing, control described bit descrambling module 703 and finish bit descrambling, the address that writes of control buffer memory produces, and the data that will finish bit descrambling write buffer memory 705; Described the 6th control module 702 is used to control the generation of reading the address of buffer memory 705, and finishes and separate bit collection and handle by the address sense data from buffer memory 705 of reading that produces, and then data is sent.
In addition, the bit descrambling module also can comprise: second expansion module and second distribution module; Wherein, described second expansion module is used for the processing cycle of extended bit scrambling; Described second distribution module is used for that all period interval after the expansion of described second expansion module are distributed to the 5th control module and reads the deinterleaving data processed in order to the control bit descrambling module from buffer memory, and distributes to the data that the 5th control module is used for after the control bit descrambling module is handled bit descrambling and write buffer memory.
Certainly, described bit descrambling module further also is used in carries out judging earlier whether the last group of data through bit descrambling and preservation are write back buffer memory behind the bit descrambling to data, if, then cover last group of data and preservation, continue then next group data is carried out bit descrambling with the data of this group behind bit descrambling; Otherwise, suspend bit descrambling and repeat aforementioned decision operation.
Certainly, those skilled in the art understand easily, and the device of realization HSPA decoding can be operated by the method for the foregoing description 3 and realize the HSPA decoding in the embodiment of the invention 4, does not specifically repeat them here.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to finish by the relevant hardware of program command, and described procedure stores is in the particular memory medium.
Certainly, the foregoing description 1,2 is applied to the method and apparatus of part transmitting terminal and method and apparatus that embodiment 3,4 is applied to the part receiving terminal all is based on the thinking of changing the space service time, realize reducing the purpose of memory space by the processing periodicity that increases bit scramble or bit descrambling, therefore, can distinguish independent use, the method or the system that also can combine the realization HSPA encoding and decoding that form an integral body use, and as shown in Figure 8, do not repeat them here.
In addition, as shown in Figure 9, the embodiment of the invention 5 has proposed a kind of method of the HSPA of realization channel coding/decoding again, is that this method of example comprises with HSDPA:
Step 901: on sending direction, the saltus step of control buffer memory writes the generation that the address is read in address and saltus step, and the data that receive are write the address rule by saltus step writes buffer memory and finish bit collection and handle; From buffer memory, read address rule sense data and finish interleaving treatment, send then by saltus step; The data that the reception interleaving treatment is crossed carry out sending after bit scramble is handled;
Step 902: on receive direction, the bit descrambling that carries out that receives is handled; The saltus step of control buffer memory writes the generation that the address is read in address and saltus step, the bit descrambling data processed is write the address rule by saltus step write buffer memory and finish deinterleaving and handle; From buffer memory, read address rule sense data again and finish and separate bit collection and handle, send then by saltus step.
Concrete, on the sending direction of transmitting terminal, will pass through the data of HARQ processing and send into the bit collection processing section; The processing of bit collection is that the generation that the saltus step by control Buffer writes the address is finished, and promptly writes Buffer by the mechanism with the saltus step of The data address, has promptly finished the part that writes of bit collection process; It should be noted that here that because bit scramble thereafter moves processing therefore the data of sequential storage can be directly used in thereafter interleaving treatment in Buffer; Be interleaving process after the bit collection process, the generation that the address is read in main saltus step by control Buffer is finished; Because of the bit scramble process that should carry out is herein moved processing, so can directly handling the bit collection process, interleaving process is stored in data among the Buffer, read the address and adopt saltus step mechanism to produce thereby define Buffer; Promptly is the bit scramble process after the interleaving process,, therefore can directly carries out the bit scramble processing, send the execution subsequent operation then the interleaving process data processed because of this processings moves processing after having done;
On the receive direction of receiving terminal, the physical channel data that receives enters the bit descrambling process through after the preceding continuous respective handling, after once finishing bit descrambling, enters the deinterleaving processing procedure; The specific implementation of deinterleaving process is that the generation that the saltus step by control Buffer writes the address is finished, here the processing because the part of bit descrambling has subsequently moved forward, therefore the bit collection of separating that the data of sequential storage can be directly used in thereafter among the Buffer is handled (after promptly writing the deinterleaving process of Buffer through saltus step, the deinterleaving process that calls over Buffer of scheme and order write the bit collection process of separating of Buffer before the Buffer data of the sequential storage that obtains had comprised, and made these two processes to omit); And the realization of separating bit collection process and deinterleaving process is similar, separating bit collection and be the generation of reading the address by the saltus step of control Buffer finishes, here be processing equally because the bit descrambling part of front has moved forward, separate bit collection and be and directly handle the data of sequential storage in Buffer after the deinterleaving, thereby define the saltus step generation mechanism that Buffer reads the address; Finish at last and separate the HARQ that data that bit collection handles are admitted to thereafter and handle, finish corresponding operating.
Obviously, in above-mentioned processing procedure, only need 1 Buffer can finish the process of coding and decoding in proper order.When the 2.8Mbps maximum transfer capacity, realize that required data quantity stored is the data volume (14043 bit) of 1 TTI, the while bit adds, the processing periodicity maximum of descrambling process also is the data volume of 1 TTI (14043 clock cycle).
It should be noted that because the embodiment of the invention 5 has only changed bit and added the processing sequence of descrambling, and do not change its processing method, therefore need the supporting use simultaneously of transmitting terminal and receiving terminal.
Based on above-mentioned thought, as shown in figure 10, the embodiment of the invention 6 has proposed a kind of system of the HSPA of realization channel coding/decoding again, is example with HSDPA; This system comprises: code device 901 and decoding device 902;
The saltus step that described code device 1001 is used on sending direction the control buffer memory writes the address and the generation of address is read in saltus step, and the data that receive are write the address rule by saltus step writes buffer memory; From buffer memory, read address rule sense data again and carry out interleaving treatment, send then by saltus step; The data that the reception interleaving treatment is crossed carry out sending after bit scramble is handled;
The saltus step that described decoding device 1002 is used on receive direction the control buffer memory writes the generation that the address is read in address and saltus step, and the bit descrambling that carries out that receives is handled; The bit descrambling data processed is write the address rule by saltus step write buffer memory; From buffer memory, read address rule sense data again, finish to separate sending after bit collection is handled by saltus step.
Concrete, as shown in figure 11, described code device 1001 comprises control module 1, control module 2, Buffer and bit scramble module; By control module 1 control preceding continuous data processed is carried out bit collection and handle, promptly adopt the saltus step addressing mechanism that data processed is write among the Buffer; Adopt address saltus step mechanism reading of data from Buffer to carry out interleaving treatment by control module 2 controls then; The data that the bit scramble module is crossed interleaving treatment are again carried out the bit scramble processing, send the execution subsequent operation then;
Described decoding device 1002 comprises such as particular solution disturbs module, Buffer, control module 3 and control module 4; At first the bit descrambling module to the warp that receives before continuous data processed carry out bit descrambling and handle; Under the control of control module 3, the bit descrambling data processed is carried out deinterleaving handle, promptly adopt address saltus step mechanism that data are write among the Buffer; Under the control of control module 4, adopt address saltus step mechanism sense data from Buffer then, after separating the bit collection processing, send to subsequent module and carry out respective handling.
As can be seen, adopt the method and system of the embodiment of the invention 5,6, adding descrambling and the processing sequence that interweaves by the change bit makes under the prerequisite that does not increase than the processing periodicity of particular solution scrambling, the memory space requirements that will have scheme now reduces half equally, realizes that the optimization of required room and time resource is used.
According to described disclosed embodiment, can be so that those skilled in the art can realize or use the present invention.To those skilled in the art, the various modifications of these embodiment are conspicuous, and the general principles of definition here also can be applied to other embodiment on the basis that does not depart from the scope of the present invention with purport.Above-described embodiment only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (22)
1, a kind of method that realizes the HSPA chnnel coding is characterized in that, this method comprises:
Finish bit collection and handle by the generation that writes the address and read the address of buffer memory is controlled, and data are write in the buffer memory by the address that writes that produces;
Sense data from buffer memory is controlled in the address of reading that utilizes bit collection to handle generation, carries out bit scramble then and handles;
Finish interleaving treatment by the generation that writes the address and read the address of buffer memory is controlled, and the bit scramble data processed is write back in the buffer memory by the address that writes that produces;
Sense data from buffer memory is controlled in the address of reading that utilizes interleaving treatment to produce, and then the data after the interleaving treatment is sent.
2, method according to claim 1 is characterized in that, the data that described bit collection is handled write and read specifically and comprise:
By address saltus step rule data are write before buffer memory, the bit scramble again by sequence of addresses rule sense data from buffer memory.
3, method according to claim 1 is characterized in that, the data of described interleaving treatment write and read specifically and comprise:
Bit scramble handle the back by the sequence of addresses rule with data processed write back buffer memory, again by address saltus step rule sense data from buffer memory.
According to any described method of claim 1 to 3, it is characterized in that 4, described bit scramble is handled and further comprised:
The processing cycle of extended bit scrambling;
All period interval after the described expansion are distributed to the operation that data after handling from the operation of buffer memory sense data with bit scramble write back buffer memory.
5, method according to claim 4 is characterized in that:
Processing cycle of bit scramble is expanded to the twice in former processing cycle, and the cycle after the described expansion is divided into two parts;
First after described expansion is in the cycle, and sense data is carried out bit scramble from buffer memory;
Second portion after described expansion is in the cycle, and the data behind the temporary bit scramble also write back buffer memory with it.
6, method according to claim 5 is characterized in that, described keeping in specifically comprises:
Data are carried out judging earlier whether the last group of data through bit scramble and preservation have been write back buffer memory behind the bit scramble, if, then cover last group of data and preservation with the data of this group behind bit scramble, continue then next group data is carried out bit scramble; Otherwise, suspend bit scramble and repeat aforementioned determining step.
7, a kind of device of realizing the HSPA chnnel coding comprises first control module, second control module and bit scramble module, it is characterized in that this device also comprises: the 3rd control module and a buffer memory; Wherein,
The address that writes that described first control module is used to control buffer memory produces, and by the address that writes that produces data is write in the buffer memory;
The address of reading that described the 3rd control module is used to control buffer memory produces, and utilize the address control sense data from buffer memory of reading that produces to finish the bit collection processing, control described bit scramble module and finish bit scramble, the address that writes of control buffer memory produces, and the data that will finish bit scramble write back buffer memory;
Described second control module is used to control the generation of reading the address of buffer memory, and finishes interleaving treatment by the address sense data from buffer memory of reading that produces, and then data is sent.
8, device according to claim 7 is characterized in that, described bit scramble module further comprises: first expansion module and first distribution module; Wherein,
Described first expansion module is used for the processing cycle of extended bit scrambling;
Described first distribution module be used for all period interval after the expansion of described first expansion module distribute to the 3rd control module in order to the control bit scrambling module from the buffer memory sense data, and the data of distributing to after the 3rd control module is handled bit scramble in order to the control bit scrambling module write back buffer memory.
9, device according to claim 8 is characterized in that:
Described bit scramble module is further used for judging earlier whether the last group of data through bit scramble and preservation are write back buffer memory after data are carried out bit scramble, if, then cover last group of data and preservation, continue then next group data is carried out bit scramble with the data of this group behind bit scramble; Otherwise, suspend bit scramble and repeat aforementioned decision operation.
10, a kind of method that realizes the HSPA channel-decoding is characterized in that, this method comprises:
Handle by the deinterleaving of finishing receiving data is controlled in the generation that writes the address and read the address of buffer memory, and data are write buffer memory by the address that writes that produces;
Sense data from buffer memory is controlled in the address of reading that utilizes deinterleaving to handle generation, carries out bit descrambling then and handles;
Separate bit collection and handle by the generation that writes the address and read the address of buffer memory being controlled finish, and the bit descrambling data processed is write back in the buffer memory by the address that writes that produces;
Utilization is separated the address of reading of bit collection processing generation and is controlled sense data from buffer memory, and the data that will separate then after bit collection is handled send.
11, method according to claim 10 is characterized in that, the data of described deinterleaving write and read specifically and comprise:
By address saltus step rule data are write before buffer memory, the bit descrambling again by sequence of addresses rule sense data from buffer memory.
12, method according to claim 10 is characterized in that, described data of separating the bit collection processing write and read specifically and comprise:
Bit descrambling handle the back by the sequence of addresses rule with data processed write back buffer memory, again by address saltus step rule sense data from buffer memory.
According to any described method of claim 10 to 12, it is characterized in that 13, described bit descrambling is handled and further comprised:
The processing cycle of extended bit descrambling;
All period interval after the described expansion are distributed to the operation that data after handling from the operation of buffer memory sense data with bit descrambling write back buffer memory.
14, method according to claim 13 is characterized in that:
Processing cycle of bit descrambling is expanded to the twice in former processing cycle, and the cycle after the described expansion is divided into two parts;
First after described expansion is in the cycle, and sense data is carried out bit descrambling from buffer memory;
Second portion after described expansion is in the cycle, and the data behind the temporary bit descrambling also write back buffer memory with it.
15, method according to claim 14 is characterized in that, described keeping in specifically comprises:
Data are carried out judging earlier whether the last group of data through bit descrambling and preservation have been write back buffer memory behind the bit descrambling, if, then cover last group of data and preservation with the data of this group behind bit descrambling, continue then next group data is carried out bit descrambling; Otherwise, suspend bit descrambling and repeat aforementioned determining step.
16, a kind of device of realizing the HSPA channel-decoding comprises the 4th control module, the 6th control module and bit descrambling module, it is characterized in that this device also comprises: the 5th control module and a buffer memory; Wherein,
The address that writes that described the 4th control module is used to control buffer memory produces, and by the address that writes that produces data is write in the buffer memory;
The address of reading that described the 5th control module is used to control buffer memory produces, and utilize the address control sense data from buffer memory of reading that produces to finish the deinterleaving processing, control described bit descrambling module and finish bit descrambling, the address that writes of control buffer memory produces, and the data that will finish bit descrambling write back buffer memory;
Described the 6th control module is used to control the generation of reading the address of buffer memory, and finishes and separate bit collection and handle by the address sense data from buffer memory of reading that produces, and then data is sent.
17, device according to claim 16 is characterized in that, described bit descrambling module further comprises: second expansion module and second distribution module; Wherein,
Described second expansion module is used for the processing cycle of extended bit scrambling;
Described second distribution module be used for all period interval after the expansion of described second expansion module distribute to the 5th control module in order to the control bit descrambling module from the buffer memory sense data, and distribute to the data that the 5th control module is used for after the control bit descrambling module is handled bit descrambling and write back buffer memory.
18, device according to claim 17 is characterized in that:
Described bit descrambling module is further used for judging earlier whether the last group of data through bit descrambling and preservation are write back buffer memory after data are carried out bit descrambling, if, then cover last group of data and preservation, continue then next group data is carried out bit descrambling with the data of this group behind bit descrambling; Otherwise, suspend bit descrambling and repeat aforementioned determining step.
19, a kind of method that realizes the HSPA channel coding/decoding is characterized in that, this method comprises:
Adopt aforesaid right to require 1 to 6 any one method to carry out the HSPA chnnel coding;
Adopt aforesaid right to require 10 to 15 any one methods to carry out the HSPA channel-decoding.
20, a kind of system that realizes the HSPA channel coding/decoding is characterized in that, this system comprises:
Device and as any described device of realizing the HSPA channel-decoding of above-mentioned claim 16 to 18 as any described realization HSPA chnnel coding of above-mentioned claim 7 to 9.
21, a kind of method that realizes the HSPA channel coding/decoding is characterized in that, this method comprises:
On sending direction, the saltus step of control buffer memory writes the generation that the address is read in address and saltus step, and the data that receive are write the address rule by saltus step writes buffer memory and finish bit collection and handle; From buffer memory, read address rule sense data again and finish interleaving treatment, send then by saltus step; The data that the reception interleaving treatment is crossed carry out sending after bit scramble is handled;
On receive direction, the bit descrambling that carries out that receives is handled; The saltus step of control buffer memory writes the generation that the address is read in address and saltus step, the bit descrambling data processed is write the address rule by saltus step write buffer memory and finish deinterleaving and handle; From buffer memory, read address rule sense data again and finish and separate bit collection and handle, send then by saltus step.
22, a kind of system that realizes the HSPA channel coding/decoding is characterized in that, this system comprises: encoding apparatus and decoding apparatus; Wherein,
The saltus step that described code device is used on sending direction the control buffer memory writes the generation that the address is read in address and saltus step, and the data that receive are write the address rule by saltus step writes buffer memory and finish bit collection and handle; From buffer memory, read address rule sense data again and finish interleaving treatment, send then by saltus step; The data that the reception interleaving treatment is crossed carry out sending after bit scramble is handled;
Described decoding device is used on receive direction the bit descrambling that carries out that receives being handled; The saltus step of control buffer memory writes the generation that the address is read in address and saltus step, the bit descrambling data processed is write the address rule by saltus step write buffer memory and finish deinterleaving and handle; From buffer memory, read address rule sense data again and finish and separate bit collection and handle, send then by saltus step.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102790670A (en) * | 2011-05-20 | 2012-11-21 | 中兴通讯股份有限公司 | HS-DSCH (high-speed downlink shared channel) receiving method and device based on HSPA+ (high speed downlink packet access) |
| CN103401641A (en) * | 2013-07-29 | 2013-11-20 | 武汉邮电科学研究院 | Descrambling method of placeholder y in LTE UCI coding information and system |
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| CN1893342B (en) * | 2005-07-05 | 2010-06-09 | 上海原动力通信科技有限公司 | Multi-carrier-wave IISDPA business transmission channel coding method and coding apparatus |
| CN101022283A (en) * | 2007-03-15 | 2007-08-22 | 中兴通讯股份有限公司 | Bit scramble parallel processing method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790670A (en) * | 2011-05-20 | 2012-11-21 | 中兴通讯股份有限公司 | HS-DSCH (high-speed downlink shared channel) receiving method and device based on HSPA+ (high speed downlink packet access) |
| CN102790670B (en) * | 2011-05-20 | 2016-08-31 | 深圳市中兴微电子技术有限公司 | A kind of HS-DSCH method of reseptance based on HSPA+ and device |
| CN103401641A (en) * | 2013-07-29 | 2013-11-20 | 武汉邮电科学研究院 | Descrambling method of placeholder y in LTE UCI coding information and system |
| CN103401641B (en) * | 2013-07-29 | 2016-06-08 | 武汉邮电科学研究院 | Placeholder y de-scrambling method in LTE UCI coding information and system |
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