CN101471670A - Table-look-up type data weighting balance circuit and dynamic component matching method - Google Patents
Table-look-up type data weighting balance circuit and dynamic component matching method Download PDFInfo
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- CN101471670A CN101471670A CNA2007101601528A CN200710160152A CN101471670A CN 101471670 A CN101471670 A CN 101471670A CN A2007101601528 A CNA2007101601528 A CN A2007101601528A CN 200710160152 A CN200710160152 A CN 200710160152A CN 101471670 A CN101471670 A CN 101471670A
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Abstract
The invention provides a data weighted averaging circuit, which comprises a table lookup unit and a storage unit. By adopting the mode of the table lookup, the operating speed can be largely increased and the operating delay can't be affected by the degree of the data weighted averaging circuit and the different bit widths of input data.
Description
Technical field
The present invention is relevant for a kind of table-look-up type data weighting average circuit (look-up table type dataweighted average circuit, DWA), for being applied in the data conversion system (dataconversion system) of sigma-delta modulator (sigma-deltamodulator) and digital analog converter (digital analog converter) etc.
Background technology
In general, desire is promoted the resolution (resolution) of sigma-delta modulator, just if will reduce the interior quantizing noise (quantized noise) of signal frequency range, three kinds of methods commonly used is arranged: first, the raising over-sampling rate (over-sampling ratio, OSR); The second, the exponent number of increase sigma-delta modulator; The 3rd, the resolution of increase quantizer just increases position (bit) number.Be different from first, second kind method, the third method is directly to reduce whole quantizing noise to reach more high-resolution, the linearity of using multidigit (multi-bit) framework only need have this figure place concerning quantizer gets final product, but for digital analog converter, its linearity (linearity) must reach more than the level of sigma-delta modulator overall linearity.For example one has 14 signal to noise ratios (signal to noise ratio, SNR), 2 the sigma-delta modulators in three rank, though 2 frameworks just of digital analog converter wherein, its linearity must reach 14 level, even higher.
Digital analog converter with 3 (8 level) is an example, and it includes 7 D/A conversion units (DAC cell), and each D/A conversion unit all comprises a capacitor C
SReach the then capacitor C of each D/A conversion unit of high linearity
SBetween do not match (mismatch) must be extremely low, but this usually needs great capacitance, and is infeasible actually.Therefore, there is the document proposition to utilize the method for the electric capacity of Dynamic Selection D/A conversion unit, the interference that causes not matching is tuned to outside the signal frequency range, be referred to as dynamic assembly coupling (dynamic element matching), its detail operations principle, please refer to a kind of sigma-delta analog-digital converter circuit framework (" A 19-BitLow-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging that people such as Nys proposes; " IEEE Journal of Solid-State Circuits, vol.32, No.7, July 1997) and, a kind of method (" Linearity Enhancement of Multibit Δ ∑ A/D andD/A Converters Using Data Weighted Averaging that strengthens the linearity that people such as Baird propose; " IEEE Transactions on Circuitsand Systems II:Analog and Digital Signal Processing, vol.42, No.12, December1995).
Summary of the invention
Because the problems referred to above, one of purpose of the present invention provides a kind of data weighting average circuit, utilize lookup table mode, significantly improve arithmetic speed, and operating delay is not subjected to the exponent number of data weighting average circuit and the influence of importing the different bit widths (bit width) of data.
For reaching above-mentioned purpose, data weighting average circuit of the present invention comprises: a lookup unit, and a built-in truth table in order to receiving an input code and one second output code, and produces one first output code according to this truth table; And a memory cell receives this first output code, and according to a control signal, upgrades this second output code.
Another purpose of the present invention provides a kind of dynamic component matching method, for selecting a plurality of D/A conversion units according to an input code, the method includes the steps of: according to this input code and one second output code, the truth table that inquiry one is preset is to produce one first output code; And, receive this first output code, and, upgrade this second output code according to a control signal, wherein, second output code system is used for selecting these a plurality of D/A conversion units.
Characteristic of the present invention is to decide the output of data weighting average circuit via lookup table mode, so be applicable to the data weighting average circuit of any exponent number and bit width.When the bit width of the exponent number of data weighting average circuit or input data is different, other hardware configuration or complexity are all the same, the truth table that only needs to adjust in the lookup unit or the logical circuit of tabling look-up gets final product, and therefore can significantly promote arithmetic speed and reduce operating delay.
Description of drawings
Fig. 1 is the structural representation of the first embodiment of the present invention.
Fig. 2 is the structural representation of the second embodiment of the present invention.
Fig. 3 be table look-up among Fig. 2 logical circuit an example of built-in truth table.
The reference numeral explanation
100,200 data weighting average circuits
110 lookup unit 120,232D D-flip flop
210 table look-up, and logical circuit 230 pointers keep and generator
231 multiplexers, 233 pointer decoders
Embodiment
The present invention is pre-stored within all possible output of the data weighting average circuit of a specific exponent number and a certain bits width in the one built-in truth table, the lookup unit 110 or 210 need of logical circuit of tabling look-up are inquired about truth table according to two groups of input data, and select corresponding output to get final product.The present invention need not do conversion between thermometer-code and two ary codes, do not need the computing of adder yet, therefore not only can significantly promote on the speed, operating delay is can factor not influenced according to the different bit widths of the exponent number of weighted average circuit and input data simultaneously.
Below for convenience of description, from Fig. 1 to Fig. 3, the back-end circuit of table-look-up type data weighting average circuit of the present invention for arranging in pairs or groups one 3 (N=3) and having the digital analog converter of 7 D/A conversion units, note that the present invention is not as limit.
Fig. 1 is the structural representation of the first embodiment of the present invention.Table-look-up type data weighting average circuit 100 of the present invention comprises: a lookup unit 110 and a D flip-flop (D flip-flop) group 120.In the present embodiment, the number of the D flip-flop in the D flip-flop group 120 equals lookup unit 110 output M＜6:0〉bit width, with back-end circuit of the present invention serves as that one 3 of collocation and the digital analog converter with 7 D/A conversion units are example, and the D flip-flop number in the D flip-flop group 120 promptly equals 7.According to present embodiment, build table-look-up type data weighting average circuit 100 in the lookup unit 110 of one truth table (look-up table), each input is all according to the quantizer output Din＜6:0 of (figure does not show)〉the output Dout＜6:0 of (being a thermometer-code (thermometer code)) and the D flip-flop group 120 of last clock (clock)〉inquire about this built-in truth table, and determine corresponding one output M＜6:0 〉.Afterwards, each D flip-flop in the D flip-flop group 120 is more simultaneously according to a control signal (for example in a rising edge of clock signal), with the input M＜6:0 of D end〉content write the output Dout＜6:0 of Q end.
Fig. 2 is the structural representation of the second embodiment of the present invention.Fig. 3 be table look-up among Fig. 2 logical circuit an example of built-in truth table.With reference to figure 2, the table-look-up type data weighting average circuit 200 of present embodiment comprises: table look-up logical circuit 210, a D flip-flop group 120 and a pointer (pointer) keeps and generator 230.The difference of present embodiment and table-look-up type data weighting average circuit 100 is, adds to keep and generator 230 into a pointer.In the present embodiment, pointer keeps with generator 230 and comprises a multiplexer 231, a D flip-flop group 232 and a pointer decoder 233.
Similarly, the logical circuit 210 of tabling look-up has a built-in truth table (please refer to Fig. 3), each all according to the output Din＜6:0 of quantizer〉(being a thermometer-code) inquire about this built-in truth table with the pointer that pointer generator 230 produces, and determine corresponding one output M '＜6:0 〉; Structure as for D flip-flop group 120 is identical with work and Fig. 1, no longer repeats.With reference to the pointer in figure 3 truth tables, pointer value is represented the first digit analog-converted unit number (supposing from 1 to 7) that next time will begin to choose for the bit position of " 1 ".Equal " 0000100 " and input Din＜6:0 with pointer value〉to equal " 0000111 " be example, corresponding output the M '＜6:0 of the logical circuit 210 of tabling look-up〉equal " 0011100 ", so the D/A conversion unit number that is selected is 3,4,5.Have special circumstances to be: as Din＜6:0〉value when being zero entirely, to there be D/A conversion unit to be selected, so the value of pointer must be carried over into input next time at present, present embodiment is for to reach this function via a multiplexer 231 and a D flip-flop group 532.Multiplexer 231 is according to Din＜6:0〉content select the value of delivery channel 1 or channel 0, as Din＜6:0〉value when being zero entirely, the value of selector channel 1 (Y＜6:0 〉) (output of the last logical circuit 510 of tabling look-up) is output as X＜6:0 〉; And as Din＜6:0 value when not being zero entirely, the value of selector channel 0 (M＜6:0 〉) is output as X＜6:0 〉.As for, the work of D flip-flop group 232 is identical with D flip-flop group 120 with structure, no longer repeats.Please note, in the present embodiment, the number of the D flip-flop in the D flip-flop group 532 equals X＜6:0〉bit width (equaling 7), identical with D flip-flop group 120, each D flip-flop in the D flip-flop group 232 is also according to same control signal (for example in a rising edge of clock signal), with the input X＜6:0 of D end〉content write the output Y＜6:0 of Q end.At last, pointer decoder 233 is with the output Y＜6:0 of D flip-flop group 232〉be reduced to a pointer.Wherein, D flip-flop group 120,232 all can utilize 7 buffers to substitute.
All can utilize a read-only memory (ROM) or a combinational logic (combinational logic) circuit to implement though it should be noted that the lookup unit 110 and the logical circuit 210 of tabling look-up, in fact the circuit complexity of the two is different.Significantly, two are input as Din＜6:0〉with the logical circuit 210 of tabling look-up of pointer, the circuit complexity of enforcement can be lower, relatively, two are input as Din＜6:0〉with Dout＜6:0 lookup unit 110, the circuit complexity of enforcement is just than higher.In addition, the present invention's data weighting average circuit structure is applicable to any exponent number and bit width.For example, with the truth table of Fig. 3, value wherein is that the data weighting average circuit and the bit width that are applicable to single order equal 7; If will implement other exponent number and bit width, the content that the present invention only need change Fig. 3 truth table gets final product, and other hardware configuration or complexity are then constant, so can not influence arithmetic speed.Therefore, high more or bit width is wide more when the exponent number of data weighting average circuit, the arithmetic speed difference between the present invention and the known technology will be obvious more.
The specific embodiment that is proposed is only in order to the convenient technology contents that the present invention is described, but not with narrow sense of the present invention be limited to the foregoing description, under the situation of spirit that does not exceed the present invention and following claim, the many variations of being done is implemented, and all belongs to the present invention's scope.
Claims (13)
1. data weighting average circuit comprises:
One lookup unit, a built-in truth table in order to receiving an input code and one second output code, and produces one first output code according to this truth table; And
One memory cell receives this first output code, and according to a control signal, upgrades this second output code.
2. data weighting average circuit as claimed in claim 1, wherein this input code is a thermometer-code.
3. data weighting average circuit as claimed in claim 1, wherein the capacity of this memory cell is corresponding to the bit width of this first output code.
4. data weighting average circuit as claimed in claim 1, wherein the content of this truth table can be along with the difference of the exponent number of this data weighting average circuit and is changed.
5. data weighting average circuit as claimed in claim 1, wherein the content of this truth table can change with the different bit widths of this input code.
6. data weighting average circuit comprises:
One logical circuit of tabling look-up, a built-in truth table in order to receiving an input code and a pointer, and produces one first output code according to this truth table;
One first memory cell receives this first output code, and according to a control signal, to upgrade one second output code; And
One pointer keeps and generator, is used for receiving this first output code, to produce this pointer.
7. data weighting average circuit as claimed in claim 6, wherein when this input code equaled a default value, this pointer can be carried over into next frequency.
8. data weighting average circuit as claimed in claim 6, wherein this pointer reservation comprises with generator:
One multiplexer receives this first output code and one the 4th output code, when this first input code equals this default value, selects the 4th output code to be output as one the 3rd output code, otherwise, select this first output code to be output as the 3rd output code;
One second memory cell receives the 3rd output code, and according to this control signal, to upgrade the 4th output code; And
One pointer decoder is used for receiving the 4th output code, to produce this pointer.
9. data weighting average circuit as claimed in claim 8, wherein the capacity of this second memory cell is corresponding to the bit width of the 3rd output code.
10. a dynamic component matching method is selected a plurality of D/A conversion units according to an input code, and the method includes the steps of:
According to this input code and one second output code, behind the default truth table of inquiry one to produce one first output code; And
Receive this first output code, and according to a control signal, upgrade this second output code, wherein, second output code is used for selecting these a plurality of D/A conversion units.
11. method as claimed in claim 10, wherein this input code is a thermometer-code.
12. a dynamic component matching method is selected a plurality of D/A conversion units according to an input code, comprises:
According to this input code and a pointer, behind the truth table that inquiry one is preset, to produce one first output code; And
Receive this first output code,, produce this pointer and one second output code simultaneously according to a control signal;
Wherein, second output code is used for selecting these a plurality of D/A conversion units, and when this input code equaled a default value, this pointer was carried over into next frequency.
13. method as claimed in claim 12, wherein this receiving step also comprises:
When this first input code equals this default value, select the 4th output code to be output as one the 3rd output code, otherwise, select this first output code to be output as the 3rd output code;
According to this control signal, receive the 3rd output code, to produce the 4th output code; And
Receive the 4th output code, to produce this pointer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102857227A (en) * | 2012-09-21 | 2013-01-02 | 重庆电力高等专科学校 | Digital to analog (DA) conversion data bit expander circuit |
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| US6677875B2 (en) * | 2002-04-29 | 2004-01-13 | Motorola, Inc. | Sigma-delta analog-to-digital converter and method |
| JP4616067B2 (en) * | 2005-04-28 | 2011-01-19 | 株式会社リコー | Constant voltage power circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102857227A (en) * | 2012-09-21 | 2013-01-02 | 重庆电力高等专科学校 | Digital to analog (DA) conversion data bit expander circuit |
| CN102857227B (en) * | 2012-09-21 | 2015-06-17 | 重庆电力高等专科学校 | Digital to analog (DA) conversion data bit expander circuit |
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