CN101467499A

CN101467499A - Power distribution system for integrated circuits

Info

Publication number: CN101467499A
Application number: CN 200780020939
Authority: CN
Inventors: 史帝夫·威耳; 史考特·麦克莫若
Original assignee: Samtec Inc
Current assignee: Samtec Inc
Priority date: 2006-06-06
Filing date: 2007-06-05
Publication date: 2009-06-24

Abstract

Power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.

Description

The power distribution system that is used for integrated circuit

Technical field

The present invention is about being used for the power division of integrated circuit (IC).Clearer and more definite, the present invention is about the power division of the IC that is used to be connected to printed circuit board (PCB) (PCB).

Background technology

In recent years, need the high speed operation circuit arrangement, so conduct a research always in the above always.But the processing time that the circuit arrangement of high speed operation will take a long time before will realizing shortening sharp, allow the former processing that to carry out of thinking, and will use a device but not multiple arrangement is carried out considerable task and become possibility, thereby reduce the development of processing cost and contribution service, facility, function etc.

The supply voltage of one circuit should be not in time and substantial variations.Even if the current drain of circuit can not fluctuate in fact in cycle short period, but under the situation of supply voltage substantial variations, circuit (comprising IC) will break down.The prime power allocating task can simply be defined as: power division must be kept load voltage in the restriction accepted that is used for reliable operation simultaneously across load signal frequency spectrum holding load electric current.If supply voltage substantial variations, then circuit (comprising IC) possibly can't be kept normal running, and the output voltage of circuit may change, thereby makes it that normal output signal can't be provided.Output voltage changes the noise that can be considered in the output signal.If noise is bigger, circuit even may break down then.

At this reason, power distribution system and the design of system of power routes system are to have a Low ESR.Design these systems and not only hang down direct current (DC) resistance, and have a Low ESR with respect to alternating current (AC) or high-frequency signal in order to have one.

If the impedance of power distribution system and power routes system is lower, even if then when the circuitry consumes current fluctuation, the fluctuation of supply voltage is still less and circuit noise is also less.But the circuit normal running, therefore device (comprising circuit) normal running.

The impedance of supposing power distribution system and power routes system is that a fluctuation of Z and circuitry consumes electric current is Δ I, and then a supply voltage fluctuation Δ V is expressed as

ΔV＝Z·ΔI

Because the part of this fluctuation becomes a noise signal, so a noise voltage V _nBe expressed as (wherein k is one 0 to 1 coefficient):

V _noise＝k·ΔV＝kZ·ΔI

Can understand from these formula,, then supply voltage fluctuation Δ V and noise voltage V if the impedance Z of power distribution system and power routes system is less _NoiseAlso can be less.Therefore, circuit (comprising any IC) but normal running.

Great majority at present IC seldom attempt the damping between the electric capacity and these IC internal powers in these reactance component and the encapsulation in the control IC (IC crystal grain) is connected and use between the other parts of PCB level power delivery system than inductance path greatly.In addition, total inductance is a function of indivedual PCB designs.This point makes the cut-off frequency of intrinsic IC encapsulation low pass filter and damping factor depend on application PCB design.If the impedance of PCB power delivery system is an inductive and/or low excessively as if PCB power distribution system (being sometimes referred to as the power network wiring) resistive impedance, then in the IC encapsulation undesirable resonance can take place.

Used various technology to alleviate the impedance of power distribution system and power routes system (hereinafter will be called for short power distribution system).These technology comprise:

1. meticulous spaced filters zero;

2. high loss dielectric medium;

3. high skin dissipation interconnection;

4. use high equivalent series resistance (ESR) capacitor;

5. use by-pass capacitor;

6. the line section increases electric power; And

7. the distributed RC network is with the intrinsic limit of damping.

Use meticulous spaced filters zero discuss by Larry Smith and basically by Baudendistel in " power bus of decoupling zero on multilayer board " (University of Missouri-Electro Magnetic Compatibility laboratory, roller branch school, TR94-8-023, one embodiment of the technology of being discussed in May, 1994), as described below.

High loss dielectric medium is one to be used for the insulating material of power routes, and it rotates the merit that molecular dipole does by a changing electric field and absorbs energy in high loss dielectric material.It shows as a frequency dependence resistance across these power rails, under high frequency than absorbing more multipotency under the low frequency.This point is discussed in (for example) Novak ' 258 (United States Patent (USP) 6,104,258) and Novak ' 774 (United States Patent (USP) the 6th, 727, No. 774), as following.

High skin dissipation can increase the power routes impedance.On the one hand, this loss reduces the ability that power distribution system is sent electric current, increases noise amplitude partly.On the other hand, because high skin dissipation is consumptive, so it suppresses the resonance in the power routes network and suppresses noise transmission.

The impedance of high ESR capacitor straightened one given capacitor also provides consumptive shunting loss.For a signal spectrum with a straight peak swing, it is one to have half of network of identical high-frequency resistance that one network with a constant impedance causes peak to peak noise ideally, but wherein the impedance under centre or low-signal frequencies is than much lower under high frequency, for example 1: 1 ratio.More Low ESR relation to higher frequency under low frequency causes a noise high pass function.Applying pulse to a high pass filter influences the approximate differential of noise pulse, and wherein this filter time constant is longer than in this pulse in fact.This noise is formed in the pulse of trailing edge in the pulse and of leading edge by one, and each similar value is set by the high frequency shunting impedance.For a pulse of obviously being longer than filter time constant, costa is replied near zero before being punched in the phase back pulse.When this impedance was constant, this response only was scale response, returns back to zero during in this pulse duration offset from zero and at this end-of-pulsing.When the ESR of a capacitor is higher, this ESR one than broadband rate scope on domination condenser impedance and make the total high pass noise filter characteristic of filter be easier to avoid and use low ESR capacitor manufacturing.

Be extensive use of a technology of using the technology and of by-pass capacitor to increase electric power to connect up section in the prior art.

One bypass capacitor is that an essence electric capacity is connected in two capacitors between the power line.All the time power is supplied on two or more circuits, for example 5V (volt) and ground connection; This by-pass capacitor system is connected between these two circuits.If use three or more circuits, for example 5V, 3V and ground connection then are connected in this by-pass capacitor between two circuits, for example 5V circuit and ground connection or 3V circuit and ground connection.This by-pass capacitor is connected between ground connection and other circuit often, but not necessarily is used to provide the circuit combination.

One theoretical capacitor, it has in essence with frequency increases an impedance that reduces, and has the impedance effect that reduces power distribution system under alternating current or high-frequency signal situation.One theoretical inductor, it has an impedance that increases with frequency in essence, has the impedance effect that increases power distribution system under alternating current or high-frequency signal situation.Therefore, under equivalent cost and complexity, wish the structure power distribution system, so that in the load current frequency spectrum, do not represent any obvious inductance characteristic.

Under the normal condition, in a power distribution system, a voltage adjuster unit (a perhaps voltage regulator module (VRM)) is connected by power wiring with a circuit (comprising any IC).This power distribution system one Typical Disposition as shown in figure 11.One IC encapsulation, 10 and one voltage regulator module 13 is installed on the PCB 12.IC encapsulation 10 comprises a crystal grain 11.

The power distribution system impedance meeting of seeing from the circuit angle at an alternating current or high frequency situation increases because of the wiring inductance of connecting circuit and power distribution system.Then, when connecting a bypass capacitor near circuit, the power distribution system impedance meeting of seeing from the circuit angle reduces.Particular words it, for high speed circuit, the high frequency characteristics of power distribution system impedance must be lower.

One bypass capacitor is generally located near circuit very much, is used to reduce the inductance between circuit and this by-pass capacitor.When having a plurality of circuit, general abundant each group that provides or be used for an a small amount of circuit near each circuit ground of a bypass capacitor.Use this power distribution system impedance of by-pass capacitor to reduce technology and reduce the power distribution system impedance seen from the circuit angle, but the wiring impedance of connecting circuit and power distribution system remains unchanged and govern power distribution impedance in many cases at alternating current or high-frequency signal.

It is to increase power division to connect up a section so that reduce the power division wiring inductance and the power distribution system impedance that another power distribution system impedance reduces technology.In order to implement this technology effectively, often the power division wiring is made broad, clearly be to adopt a flat shape.For example,, adopt a sandwich construction so that a power division layer to be provided, and will make more straight in the wiring of the power division in this power division layer for printed circuit board (PCB) and other similar device.Often need through hole to be used for union piece and circuit, and with this punching of power division layer plane as a mesh.Generally speaking, because with at least one ground connection of these power division circuits, so in the power division wiring, also comprise ground connection.

If this power division wiring forms as a plane, then can sharply reduce interior power division wiring inductance of road plate and the power division wiring inductance between by-pass capacitor and the circuit, thereby realization reduces the power distribution system impedance at alternating current or high-frequency signal.

Another technology is in order to reducing interval (vertical separation under the situation of planar line) between these power division circuits to reduce inductance, and it is similar to the technology that reduces inductance by the width that increases these power division circuits.

Above-mentioned these two power distribution systems impedances reduce technology (increase the power routes section and reduce the interval of power division between connecting up) use capable of being combined and often are used in combination.These technology are compatible in order to reduce the power distribution system impedance.

Prior art also comprises rough application distribution R-L-C network, and it is attempted at realize the straight clear of a pair of lowpass noise transfer function according to the power distribution system of power planes.

Baudendistel (" power bus of decoupling zero on multilayer board ", TR94-8-023, University of Missouri-Electro Magnetic Compatibility laboratory, roller branch school, in May, 1994) discloses and how to determine in order to be suppressed at the damper assembly value of the power distribution system resonance that causes high impedance in the power division frequency range.For the impedance (L in these power planes chambeies wherein _PLN) resistance (R of lower and its midplane _PLN) also lower low frequency, Baudendistel use one simple one dimension is similar to estimates the power distribution system behavior, until the resonance between bypass capacitor networks and the arbitrary power planes chamber.

The model of Baudendistel is made up of n RLC in parallel branch, as shown in Figure 1.Based on the relation of this model between frequency and impedance Z as shown in Figure 2.Each branching representation is at the summation in parallel of a particular comparator value.Each parameters R _VALi, L _VALi, C _VALi(i=1 wherein ..., n) expression is from the equivalent in parallel of the individual values of each device.For example, given ten 1 μ F, 2m Ω, 1nH capacitor example, then branching representation is one 10 μ F, 0.2m Ω, 0.1nH capacitor.The also yoke plate capacitance meter in power/ground connection wiring chamber is shown a single capacitor CPLN.

In Fig. 3, find out, Baudendistel reduces the peak value of these resonance by the value that increases resistance R x with respect to corresponding inductance L x, and wherein x is 1 ..., one of n is so that straightened (has one and is approximately j ω L from the zone of its middle impedance by the domination of (n-1) inductor _VALn-1The zone of slope upwards) (has one and be approximately 1/ (j ω C to the zone of its middle impedance by the domination of n capacitor _VALn) the zone of downward slope) impedance transition.

Baudendistel enumerates the impedance equality that is used for each branch and parallel branch.Except voltage regulator module VRM, each branch represents a string vibration frequency SRF that allies the communists.This VRM is main to interact with the branch with minimum SRF.Under enough high-frequencies, induction reactance j ω L _VRMIntersection R _VRM, shown in Fig. 2 left side.This impedance increases to j ω L _VRM=1/j ω C _VAL1The point.Impedance then is decreased to zero, wherein 1/j ω C _VAL1=j ω L _VAL1Remaining impedance at this zero place is R _VAL1By at the following equation of a given component inspection, clearly understand this point:

Z _equivalent＝R _equivalent+j(ωL _equivalent-1/ωC _equivalent)

Z wherein _EquivalentBe total equiva lent impedance, R _EquivalentBe equivalent resistance, L _EquivalentBe equivalent inductance, C _EquivalentBe equivalent capacity, j is imaginary number √-1, and ω is the angular frequency of radian per second unit.Along with frequency increases, j ω L _VAL1Domination apace increases impedance up to j ω L wherein _VAL1 Intersection 1/j ω C _VAL2Limit.This impedance is at ω=(L _VALN* C _PLN) ^-0.5Descend modulation, to the last limit between zero and limit.Impedance modulation degree depends in relative quality factor zero and the limit place.This quality factor is indivedual limits or the induction reactance at zero place and the ratio of resistive impedance.One low quality factors causes less modulation, and one more high-quality cause more modulations.

The Baudendistel instruction suppresses the Impedance Peak at these limit places by one or more technology of following technology.

1. reduce the series inductance in one or more given branch;

2. increase the series resistance in one or more given branch; And

3. increase to form the electric capacity in the right higher frequency branch of one or two branch of a limit, thereby reduce the frequency of limit and j ω L.

People such as Lee (" modeling of multi-chip module power plane and analysis ", IEEE assembly, encapsulation and manufacturing technology journal, part B, the 18th volume, No. 4, November nineteen ninety-five) distributed effects by comprising these power planes chambeies and by these mode resonance (shown in Fig. 7 right-hand side) that are included in these caused these power planes chambeies of chamber boundary wave reflection Baudendistel model that becomes more meticulous.Clear and definite, people such as Lee change into a cell array with the power planes chamber from the enemy, shown in Fig. 4,5A to 5D and 6.The selected cell size is with the wavelength of the concern highest frequency in power distribution system littler (for example paying close attention to the wavelength 1/10 of highest frequency or following).Resistance, inductance and the capacitance network (shown in Fig. 5 A to 5D) or one that then cell list are shown an equivalence are by four intersection transmission lines formed square (as shown in Figure 6).People such as Lee further represent high capacitance by use and the thin-film material of the damping resistance (promptly with respect to comprising in a regional area or the discrete component, this resistance is scattered on the whole space latitude of emulsion of this structure) that obviously disperses suppresses resonance.

People such as Lee use the R-L-C equivalent that one model is provided earlier, as shown in Figure 4.People such as Lee are according to telegram equation derive inductance and capacitance.People such as Lee define three type units: inside, edge and corner, and shown in Fig. 5 A to 5C.

In order to save calculating, people such as Lee provide an icotype based on the mesh transmission line, as shown in Figure 6.

People such as Lee utilize externally peripheral inside to have an impedance Z _INT=√ 2* (L/C) ^0.5Transmission line with externally have a twice Z around the periphery _INT, 2* √ 2* (L/C) ^0.5Transmission line.

At each interior bonds place, four lines are from the outside Propagation of Energy in instantaneous source, thereby cause following impedance:

Z _{INT_JUNC}＝(L/(8C)) ^0.5＝H/X*(μ/(8ε)) ^0.5.

In each outside joint along an edge, impedance is Z _{INT_JUNC}Twice:

Z _{EDG_JUNC}＝2*Z _{INT_JUNC}＝H/X*(μ/(2ε)) ^0.5.

At each corner, impedance is Z _{INT_JUNC}Four times:

Z _CORNER＝4*Z _{INT_JUNC}＝H/X*(2μ/ε) ^0.5

These resistance values neither illustrate the caused load of any attachment assembly, the caused variable density of channel welding resistance pad array is not described yet, wherein the welding resistance pad is the perforation in these planes, and it provides these planes and passes but be not connected separating between the conductor channel on these planes.

Novak ' 285 (United States Patent (USP) 6,104,258) instruction is added along the periphery in the defined chamber of power routes and is stopped network as one in order to the member at these edges' coupling chamber internal drivings, so that suppress these reflections and generation mode resonance in power routes.Novak ' 258 instruction for efficient, stops 0.2 times of inductance that the network installation inductance should not surpass the zone that stops.

The impedance that Novak ' 258 discloses the geometry, permittivity and the permeability that depend on the chamber separately.Yet, the load of Novak ' 258 undeclared these bypasses and/or these driving components.Bearing power cavity impedance or frequency surpass under the situation of first mode resonance do not match this impedance and can allow the essence reflection of the method that Novak ' 258 is instructed in fact at these plate level assemblies.

Replace the edge termination method that Novak ' 258 is instructed, people such as Yamamura (United States Patent (USP) 5,844,762) disclose and reach the damper assembly 14 that whole printed circuit assembly parts disperse to be connected to transmission line 15 in fact partially, shown in Fig. 8 A and 8B.People such as Yamamura instruct an even dispersion more satisfactory.

Can find out branch's resonance that people such as Yamamura can be only successfully solve Baudendistel and instructed by the instruction of following Baudendistel.Can find out that from people such as Lee people such as Yamamura can't solve the basic reason of the mode resonance of these power/grounded chambers: the mispairing impedance at these [places.Can find out that also simultaneously in fact less than the characteristic impedance of mesh transmission line and come down under the ohmic situation, people such as Yamamura can successfully suppress mode resonance in the damper assembly impedance from people such as Lee.

By contrast, Novak ' 258 and Novak ' 744 (United States Patent (USP) the 6th, 727, No. 744) instruction be in order to suppress mode resonance, add along the PCB border in fact stop network be enough to mate peripheral impedance with should (etc.) internal driving of planar cavity.For this reason, Novak ' 258 and Novak ' 744 suppress mode resonance under than the assembly of people's much less such as Yamamura and expense.

Yet, be similar to people such as Yamamura, compare planar cavity self, Novak ' 258 and ' 774 depends on and realize a low inductance in these damper assembly.Novak is set out in these target inductance that stop in the network and is no more than:

0.2*μ ₀*μ _R*H

μ wherein ₀It is permeability of free space (about 31.9 * 10 ^-9Weber/ampere), μ _RBe the relative permeability (general 1.0 webers/ampere or extremely near 1.0 webers/ampere) of these conductors, and H is the dielectric medium thickness in the planar cavity.

For example, given one has a dielectric medium thickness 0.001 " the chamber, target inductance will need＜0.2*31.9 * 10 ^-90.001 inch=6.4pH of 1 weber of/ampere * of weber/ampere *.Capacitor is implemented and if use these planes of PCB near surface, then the installation inductance of each capacitor may be approximately 1nH if use is shared, and needs about 160 assemblies.For the situation of one power/grounded chamber further from the PCB surface, such as what occurred in many complicated assembly parts, the installation inductance of each capacitor may be up to twice, thereby need double number of capacitors.

Can understand that from people such as Lee one not in the load cavity periphery, impedance is closely followed fully:

Z _{INT_JUNC}＝H/X*(μ/(8ε)) ^0.5.

Fully away from these corners, impedance is closely followed along these edges:

Z _{EDG_JUNC}＝H/X*(μ/(2ε)) ^0.5＝2*Z _{INT_JUNC}.

At each corner, impedance is closely followed:

Z _CORNER＝H/X*(2μ/ε) ^0.5＝4*Z _{INT_JUNC}.

As shown in Figure 9, one has resistive impedance Z _{EDG_TERM}=Z _{EDG_JUNC}(Z wherein _{EDG_TERM}Be be positioned on the boundary edge but not in the impedance of the consumable components of corner) consumable components 17 be connected in the edge of these transmission lines 18 and the nominal and will reduce by half along the impedance of this boundary edge, and join Z by this _{INT_JUNC}Under a not load, rectangular cavity situation, this point only stays the reflection from these corner internal impedance mispairing, and the cavity impedance in these corners is the twice height at the center at a given edge.

In order to compensate these corners, as shown in Figure 9, loss component 16 is to be connected to the corner of these transmission lines 18 and must to suppose a value, and this value not only is lower than corner self characteristics impedance in fact, and is lower than the impedance of the center of each joining edge.Thereby, be positioned at the impedance (Z of the loss component 16 of corner _{CORNER_TERM}) should for:

Z _{CORNER_TERM}＝1/(X/H*(μ/8ε)) ^-0.5)-(X/H*(2μ/ε) ^-0.5))

＝4/3*Z _{INT_JUNC}

＝1/3*H/X*(2μ/ε) ^0.5

This equation is to derive by the parallel impedance that answer is kept in the required corner of a uniform impedance along the border.

When even dispersion, can find out that any bypass module produces the frequency dependence change of power distribution system impedance.For being lower than the frequency that its middle distance is these frequencies of a substantial portion of wavelength in effective dielectric medium, can be similar to the Baudendistel model, these distributed bypasses and routing network are modeled as simpler one dimension branch.

The resonance that bothers most ties up to the transformation between highest frequency R-L-C branch and the concentration power/grounded chamber electric capacity.For most of PCB, its model as shown in figure 10 (wherein modelling transmission line 19, bypass module 20 and IC load 21), power/grounded chamber electric capacity is very limited and be set at:

C=area * ε ₀* ε _R

Wherein C is electric capacity (a unit farad), and area is the planar cavity surface area, highly is planar cavity thickness, ε ₀Be the permittivity of free space, and ε _RIt is the relative permittivity of the dielectric material in the planar cavity.

Use typical PCB dielectric medium, under some frequencies, the exemplary electric capacity per square inch of a plate is as shown in the table with the impedance (typical case of the plate section that a quite big IC is occupied) that is used for Siping City side's inch:

For low-cost four or six layers of structure, a chamber height 0.040 is typical.For handling the PCB that composite glass fiber is strengthened, chamber height 0.040 " is typical.

Given one of the bypass capacitor network that spreads all over evenly or almost evenly disperses to represent a fixed installation inductance, and the change frequency between power/grounded chamber of this shunt capacitance network and this PCB depends on following parameters:

1.L _{ACP_MOUNTED}, the installation inductance of each by-pass capacitor;

2.P, the superficial density of bypass capacitor;

3.C _{PLN_SQ_IN}, the per unit area electric capacity of power/grounded chamber;

4.F _RES＝P ^0.5/2*π*L _{CAP_MOUNTED} ^0.5*C _{PLN_SQ_IN} ^0.5)；

5.Z _CHAR≈ L _{CAP_MOUNTED} ^0.5/ (C _{PLN_SQ_IN} ^0.5* P ^0.5); And

6.Z _RES≈L _{CAP_MOUNTED}/(R _{CAP_MOUNTED}*C _{PLN_SQ_IN})；

F wherein _RESBe resonance frequency, Z _CHARThe characteristic impedance of the reactive network of forming by these concentrated expressions that by-pass capacitors and power routes electric capacity are installed, and Z _RESBe in peak impedance by this bypass capacitor network and the formed limit of this concentration power wiring capacitance place.

Increase the characteristic impedance that this by-pass capacitor density increases resonance frequency and reduces formed limit between power/grounded chamber of this bypass capacitor networks and this PCB.Yet, increase capacitor density and also reduce the resistance of per unit area, thereby increase Impedance Peak with respect to this characteristic impedance, promptly increase the circuit quality factor.

These are once in order to restriction Z _RESOr Z _RESThe prior art approach of influence comprise:

1. a use series resistance increases the rough density of these by-pass capacitors, so that the restricting circuits quality factor, as described in people such as Baudendistel, Yamamura, Novak ' 258 and Novak ' 622, perhaps

2. increase the electric capacity in power planes chamber.

Each method of these methods has important disadvantages.In this first method, especially for thick printed circuit board (PCB) assembly parts, the required component number could vary gets bigger, wherein apart from the distance on the installation surface of these capacitors and these planes and be associated inductor loop is installed can be bigger.

This second method need be used high expense and reluctant sometimes thin thin and/or high-dielectric constant dielectric material.One delicate, the latent defect of this second method are that it reduces the resonance frequency between these by-pass capacitors and the power/grounded chamber.

People such as Lee enumerate the distributed component modeling of a power distribution system of the two-dimensional grid of using a discrete R-L-C-G assembly unit or mesh transmission line.Incorporate into simultaneously in people's such as Baudendistel and Lee the power distribution system model one, total bypass electrical equipment network can be gathered into a single R-L-C branch at employed each capacitor value.The value that is used for R be form this branch particular value all capacitors be installed in parallel ESR.The value that is used for L is to be installed in parallel the capacitor inductance equally.At last, C is the shunt capacitance of these capacitors in this branch.

From then on model can be found out, in order to make each damper assembly at L _PLNSignificantly effective under the frequency, the inductance L of damper assembly _DAMPAbout L _PLNMust be less.People such as Lee are presented at L _PLNMode resonance significantly appears under the frequency.

In the prior art, for machinery, space and modularity reason, used intermediary layer and module as assembly carrier.For example, interlayer among people such as Alexander (United States Patent (USP) the 6th, 961, No. 231) announcement one cooperation one IC uses.Yet people such as Alexander only provide electric capacity to replace the member of power system as one this intermediary layer.People such as Alexander do not use this intermediary layer to reduce the power system impedance, the resonance of detuning power system, and redistribute I/O (I/O) to reduce noise injection owing to the caused PCB of the entering power routes of discontinuous return path network.People's intermediary layers such as this Alexander of decoupling zero only provide some not electric capacity of specific quantity.The resonant resistance of two parallel branchs is not subjected to the influence of the electric capacity of lower frequency branch in theory.The electric capacity that increases this branch can not help to reduce the resonance of trouble.It is only favourable when the resonance that reduces between next lower frequency branch and this intermediary layer to intermediary layer to increase electric capacity.Form this next lower frequency branch depend on intermediary layer design and these attachment assemblies the two, for example encapsulate IC, discrete capacitor and/or do not encapsulate IC crystal grain.So, the extra capacitor that the people disclosed such as Alexander may be seldom or is not helped the power division impedance.

Do not recognize in the prior art or unsolved one final problem is shunting device and the IC load load effect to power distribution system.Prior art depends on a hypothesis, i.e. power distribution system impedance is lower compared to the device of being served.If if possible,, set up that this type of distribution system becomes and difficulty and expensive on frequency and power along with device usefulness increases.

Summary of the invention

In order to overcome the problems referred to above, these preferred embodiment of the present invention provide the isolation of the reactance impedance interdependence of a plurality of IC that are connected to a shared power distribution system, matched impedance is to the IC load, and across realizing that than at present available more broadband rate scope lower-wattage distributes impedance.

These preferred embodiment of the present invention are by in border, chamber load consumption assembly, make to keep in fact evenly coming extension Novak ' 258 and ' 774 in the impedance of this boundary and the impedance in this border just in time.This point mates the Novak ' 258 of average not load cavity impedance with service wear assembly wherein and wherein calculates cavity impedance based on planar separation, dielectric substance capacitance rate and cavity perimeter and do not consider that the Novak ' 774 of the load effect of these shunt capacitances and active circuits forms contrast.

These preferred embodiment of the present invention provide the method that resonates between one power/grounded chamber in order to damping one bypass capacitor network and PCB, this PCB:

1. bypass/the damper assembly that does not need excessive number; Or

2. do not need high planar cavity electric capacity or can guarantee one when this planar cavity impedance is handed over more less than about 1.4 quality being converted to from this bypass network for property ground.

These preferred embodiment of the present invention can realize following one or more persons:

1. the reactance impedance interdependence of isolating a plurality of integrated circuits that are connected to a shared power distribution system;

2. provide a matched impedance to the IC load; And

3. across realizing that than present available more broadband rate scope lower-wattage distributes impedance.

With reference to the accompanying drawings, following detailed description according to a preferred embodiment of the present invention will more clearly be understood further feature of the present invention, assembly, feature, step and advantage.

Description of drawings

The technology of Fig. 1 to 11 explanation prior art.

Figure 12 illustrates the intermediary layer according to the present invention's one preferred embodiment.

The various inductor loops of Figure 13 explanation in a PCB.

Figure 14 illustrates the intermediary layer according to the present invention's one preferred embodiment.

Figure 15 illustrates half wave resonator according to the present invention's one preferred embodiment.

Figure 16 illustrates the intermediary layer according to the present invention's one preferred embodiment.

Figure 17 A illustrates a known power distribution system.

One near-sighted sectional drawing of the signal traces of the known power distribution system shown in Figure 17 B key diagram 17A.

Figure 18 A explanation is according to a power distribution system of the present invention's one preferred embodiment.

One near-sighted sectional drawing of the signal traces of the known power distribution system of the present invention's one preferred embodiment shown in Figure 18 B key diagram 18A.

Figure 19 A explanation is according to a power distribution system of the present invention's one preferred embodiment.

One near-sighted sectional drawing of the signal traces of the known power distribution system of the present invention's one preferred embodiment shown in Figure 19 B key diagram 19A.

One known possible arrangement of Figure 20 A explanation z axle interconnection.

One circuit diagram of the configuration shown in Figure 20 B key diagram 20A.

Figure 20 C explanation is according to a feasible z axle interconnection of the present invention's one preferred embodiment.

Figure 20 D explanation is according to a circuit diagram of the configuration shown in the present invention's one preferred embodiment is in Figure 20 C.

Figure 21 A and 21B are respectively at the circuit diagram according to a configuration of an intermediary layer of the present invention's one preferred embodiment shown in Figure 21 C and the 21D.

Embodiment

The technology that is used for the optimized power distribution system

Shown in the power distribution system 100 of Figure 12,111 pairs of these power of PCB 110 and ground planes can match together to utilize mutual inductance and interplanar electric capacity.These power of PCB 110 and the phase mutual inductance of ground plane 111 reduce the inductance in power division path on the whole.The inductance that reduces the power division path can increase the power division frequency range.These power of PCB 110 and the interplanar electric capacity of ground plane 111 provide a small amount of energy to store, but interact with other shunt inductance in the power distribution system 100.This point ties up to the key parameter under the high frequency.

Capacitor 112 on PCB 110 is provided at the store energy in the power distribution system 100.Capacitor 112,122 and 132 can be installed on the substrate, and it comprises PCB 110, intermediary layer 120 and IC encapsulation 130, maybe can embed in the substrate.Capacitor 112,122 and 132 also can be installed in PCB 110, intermediary layer 120 or IC and encapsulate 130 tops or bottom.

Capacitor 112,122 and 132 has inductance and the resistance and the electric capacity of certain amount that is associated with its design inherently.When optimized power is divided timing, these must be installed the inherent inductance and the resistance of capacitor and take into account.Capacitor 112,122 and 132 has generally made metal gasket and passage and has been mounted to substrate.Capacitor 112,122 and 132 has the inductance that is associated with the method that is used to be attached to substrate.This inductance reduces the power division frequency range and causes and the interaction of other power division assembly, comprises other capacitor and plane capacitance.These interactions must be taken into account when optimized power distribution system 100.Also can use the planar substrates structure (embedded capacitor (not shown)) that is used for high-frequency tuning to produce capacitor.

Tuning planar metallic structure in one or more substrate of these substrates can be used for the frequency response of tune power distribution system.These structures can be used for extending the power system frequency range.These structures comprise embedded capacitor, embedded inductor device, embedded transmission line, embedded resonator (1/4th and half-wave) and embedded resistor.Can increase the extra resistance assembly,, be used to control the purposes of the damping attribute (quality factor) of resonant structure as damascene structures, the controlled attaching structure of material properties or outside discrete component.

Can encapsulate 130 at IC, optimization plan position approach in intermediary layer 120 or the PCB 110.Preferable is to come the optimization plan position approach across whole power distribution system 100.Also can encapsulate 130 at IC, optimization plane sizes in intermediary layer 120 or the PCB 110.Reducing plane sizes is the parallel resonance frequency (PRF) that is used to increase this power distribution system.

These planar metallic structure of tuning/demodulation of being used to resonate can be positioned at IC encapsulation 130, intermediary layer 120 or PCB 110.Can make interior metal structure (inductor, capacitor, transmission line, resonator) so that carry out electronic compensating, promptly, formation designs parasitic and/or 1/4th/half wave resonances structure of equivalent on-line file of assembly by way of compensation, and follows the trail of baseplate material and processing procedure automatically.By also comprise one compensated the 3rd structure is in addition more formed of a part of macrostructure represent the electrical properties identical as any structure of a compensation assembly responds manufacturing variation and operating environment and change with these three assemblies.For example, one by the formed capacitor of the part on a plane, and it will follow the trail of the electric capacity of this bigger planar section pro rata as a compensation assembly of the limit that resonates to one more most of formed one of this same level and discrete component.

The resistor (not shown) can be used for stopping, and promptly adopts any type of resistor assembly all to can be used for mating the impedance of a transmission structure and can be used for the resonance mass factor and reduces technology.Resistor can be placed in top or the bottom of IC encapsulation 130, intermediary layer 120 or PCB 110 as discrete device, maybe it can be embedded in IC encapsulation 130, intermediary layer 120 or the PCB 110.Utilize the embedded resistor program of standard, resistor can be formed embedded board unit.Can use other material to form resistor, for example controlled resistor attached solder and epoxy resin.These materials can comprise the epoxy resin sticker, are suspended in an interior conduction of colloid and/or a combination of semiconductive material before it is included in and solidifies.Exemplary material includes but not limited to: copper, aluminium, silver, iron, tin, nickel, gold, carbon, silicon, its combination and alloy.

As shown in figure 13, can come the optimization inductor loop by following.Can select and pad adheres to design or more come optimization to pass through the inductance of a capacitor 200 near power or ground plane 205 by the accompanying PCB 208 of location capacitor by device.Can be by the design of channel 204, by channel separation, by locating farther power or ground plane 205 or coming optimization to pass through the inductance of capacitor passage 201 by the use additional channels.Because scattering 202 caused inductance, ground connection and power planes can come optimization by 205 pairs of separating planes or by the distance between capacitor 207 and the IC encapsulation 206.Can be by the design of channel 204, by channel separation or by using additional channels to come optimization to adhere to 203 inductance by IC.

Also can use other technology to come this power distribution system of optimization.Key is to obtain Low ESR, wraps modal low induction reactance.More not only consider as recognize complicated impedance value in the prior art, but also consider complicated impedance phase, because the suitable management of this phase place reduces and/or get rid of the resonance that bothers fully.Any technology that can manage this phase place or value can cooperate above-mentioned these optimal methods to use.

The optimal method of power distribution system

The optimal method that is used for power distribution system comprises one or more that rough impedance reduces, planar inductor reduces and the delivered power inductance reduces.

Rough impedance reduces can be by increasing the electric capacity with respect to the inductance of discrete or inner plane capacitor, reduce to install the capacitor inductance and/or by optimization solution is installed, it comprises by impedance measurement, realizes by the electromagnetic-field simulation of power distribution system or by the optimization location and the optimized power wiring inductance of these assemblies.

Planar inductor reduces can be by reducing separation (chamber height) and/or the incompatible realization of a plurality of planar sets of use in parallel between power/ground plane.

Inductance between these by-pass capacitors and power routes can be by realizing with respect to these capacitor installation position selection Z axial plane position.In addition, the geometry of the Z axle between power routes structure (being generally the plane) and any given capacitor and/or capacitor group interconnection and the quantity effective inductance that can influence this type of interconnection.

Similarly, the inductance between power routes and any given IC is subjected to the influence of (these) power routes plane and IC intergranule distance.The same with these by-pass capacitors, in the geometry and the quantity decision total inductance of the interconnection of power routes structure and intergranule.In both cases, because need minimize inductance, so supposition has the material of minimum relative permeability 1.0.Has about 1.0 relative permeability such as the nonferrous metal of copper, silver and other suitable metal.Interconnection comprises PCB passage, trace, polygon filling and other suitable interconnection.

The optimal method that is used for power distribution system can comprise that these following impedances reduce one or more method of method;

1. limit/zero-compensation method;

2. limit/pole compensation method;

3. limit/many zero-compensations method;

4. signal harmonic compensation method; Or

5. quarter-wave resonance method.

1. limit-zero-compensation method

Have in the right power distribution system of a plurality of limits one, each limit is to producing the parallel resonance between the electric capacity of the inductance of one first network branches and one second network branches.One branch comprises one or more assembly.Generally speaking, this first network branches is formed as the equivalent transfer function of a voltage regulator module of one first fen flow branching by being connected to the power system wiring.Additional distributing branch generally comprises the monodrome capacitor of the quantity in each branch, and each branch also connects across this power routes network, as shown in Figure 1.Each N of branch represents a self-resonant frequency higher than the N-1 of front branch.Under idealized situation, all branches all equate with the defined characteristic impedance of the ratio of electric capacity by inductance is installed.Demonstrate as Baudendistal, have in each branch under the situation of enough resistive impedance, can suppress the impedance variation of power distribution system.

Each branch causes a complicated admittance (impedance converse) of shunting power routing network.Most of induction reactance interact and betide between the paired branch that self-resonant frequency determined by each branch.This point can adopt one to simplify the electric capacity interaction that viewpoint is expressed as inductance and the N of branch of the N-1 of branch, the C of branch for example shown in Figure 1 _Va11And C _Va12When the self-resonant frequency of each branch separated fully, this approximate viewpoint provided one to be similar to quite accurately.When the SRF of branch tight spacing, significantly interacting betides between the how different branches.

Until the resonance of the first half-wave mode, the extremely similar by-pass capacitor of these power routes networks ground represents self-impedance.From direct current to geometrical shapes, insulant effective capacitance rate (dielectric constant) and the defined frequency in position in network, this power routes network self-impedance increases along with frequency and reduces and still approaching-90 ° of phase place.Under this definition frequency, one zero singular points can occur.Along with phase place apace from almost-90 ° to 0 ° and almost to+90 ° of transformations, make minimum impedance arrive zero, wherein it keeps until the first half-wave mode resonance that is associated with an Impedance Peak.Near power routes network center position represents highest frequency zero, and represents low-limit frequency zero near these positions of these power routes network edges.For an even rectangular cavity, center zero is at about F _ZERO=2,400MHz/ (Width _INCHES* ε _R ^0.5) the following appearance, wherein Width _INCHESIt is the complete side width in plane (inches).Near these corners, zero frequency is at about F _ZERO=1600MHz (Inches* ε _R ^0.5) occur, its Inches is the height of plane one complete side.

For a ε _R4.0 and even to large-scale 16 ＂ * 16 ＂ structures, this frequency range near the 50MHz these power cloth network corners near the 75MHz this center.This frequency generally is higher than these self-resonant frequencies that by-pass capacitor is installed.For the by-pass capacitor of most of general types and configuration is installed, self-resonant frequency seldom surpasses 50 to 60MHz and the most common 20MHz or lower.Therefore, bypass capacitor networks manifests inductive traditionally over a range of frequencies, and the resonance certainly of arbitrary set point still manifests capacitive character in bearing power routing network not in this frequency range.The result is the equivalent electric circuit that shakes of allying the communists in the lump, and it is presented in an impedance maximum under the resonance frequency.This resonance can suppress by Several Methods, comprises as Baudendistal and instructing, and adds resistance to these by-pass capacitor branches.

This optimal method comprises that the net phase position characteristic by changing the bearing power wire structures suppresses and thoroughly get rid of the resonance behavior.Optimal varied is a real balance, and it depends on these zero frequencys of this power routes structure in fact.

In this optimal method, current-dividing network can design a series of branches, each branch have its oneself zero, make any point place of self-impedance in the power routes network of this composite network keep the power routes network from 135 ° of the phase place that resonates electrically in.Current-dividing network can comprise one or more plane container, its be formed at the identical or extra substrate of this power routes network in.In addition, this optimal method can comprise these following steps:

1. the maximum of decision power routes network can be held the high frequency self-impedance;

2. whether decide the power routes network must satisfy in the half-wave pattern according to the physical size of power demand routing network or surpass its specified impedance, this half-wave pattern has a nominal ε who is used for preferable dielectric housing material by one _R(general 4.0) structure is represented;

3. one of structure power routes network graph model outwardly;

4. the map that the equivalent parasitism of these being installed the input of IC power maps in the step 3 to be constructed; And

5. will map to the resolution that per 0.25 ＂ in the nominal is not less than a unit at the complicated self-impedance of step 3 and 4 maps of being constructed.

In this optimal method, configuration additional distributing network makes that the phase response between IC crystal grain and power distribution system is controlled by one the 3rd shunt assembly.The 3rd current-dividing network has and equals or near a string vibration frequency of allying the communists of the parallel resonance frequency of these first and second assembly/networks, has one about 2 or following quality factor, and has and be no more than about 2.0 * √ (L ₁/ C ₂) a characteristic impedance of these reactance component, L wherein ₁Be the inductance of this first assembly or network, and C ₂Be the electric capacity of this second assembly or network.

When the parallel resonance between the electric capacity of the inductance of this first network and this second network is not subjected to damping and has one when being less than or equal to about 1.4 quality factor, so the parallel resonance that forms can cause unfavorable result, for example:

1. the location peak value that shakes altogether in the power transfer frequency range between a PCB or PCB shape assembly parts and an assembled part (a for example encapsulation IC); And

2. adhere in the higher signal energy frequency spectrum of load (a for example IC) the location peak value that shakes altogether one.

The quality factor of the 3rd current-dividing network and SRF can set by arbitrary technology of using above-mentioned these technology.The 3rd current-dividing network can be configured in order to be included in PCB 110, intermediary layer or the IC encapsulation 130, and as shown in figure 12, more possible is that these the 3rd current-dividing networks can be configured in order on the many persons that are included in PCB 110, intermediary layer 120 and IC encapsulation 130.As shown in figure 14, intermediary layer 120 ' can be included in top layer 123a and bottom 123b on the wing 123, wherein bottom 123b raises top layer 123a and surpasses these assemblies 113, makes more large tracts of land of intermediary layer 120 ' can have compared to the intermediary layer 120 of the Figure 12 that does not have to raise bottom 123b one.The additional areas of top layer 123a allow to replace intermediary layer 120 ' on additional assemblies, comprise capacitor 122.

Use an intermediary layer 120,120 ' these benefits comprise following one or more:

1. be used for design improvement;

2. the 1:1 from PCB to IC ball grid array (BGA) connects;

3. provide straight, wider bandwidth power to IC;

4. suppress

Resonance;

5. filter the noise between IC and the PCB;

6. the low quality power division extremely tolerant to the PCB design;

7. use PCB and need only satisfy maximum L and maximum R specification;

8. rising head promotes intermediary layer structure 0.050 ＂ to remove the existing SMT assembly on the PCB; And

9. solve the power delivery problems in the existing design.

If the 3rd current-dividing network is included in the PCB 110, then can (for example) set the electric capacity of the 3rd current-dividing network by dividing these planes that embed in the PCB110.These of the 3rd current-dividing network are divided the plane can form an island, make the remainder unit on these planes center on these division planes of the 3rd current-dividing network entirely, or these strokes plane of the 3rd current-dividing network can comprise at least one edge of PCB 110, makes these plane remainders of PCB 110 not exclusively divide planes around these of the 3rd current-dividing network.

The 3rd current-dividing network also can comprise a resistor assembly, and it is formed by a planar structure that is formed in the PCB 110.

2. limit-limit optimal method

In this optimal method, the series connection of the 3rd current-dividing network is inserted between this first network and this second network.

When by this first offered load, the 3rd series network has under the parallel resonance frequency of these first and two networks or the vibration frequency of allying the communists in the lump in its vicinity, has one about 2 or following quality factor, and has and be no more than about 2.0 * √ (L ₁/ C ₂) a characteristic impedance of these reactance component, L wherein ₁Be the inductance of this first assembly or network and C ₂Be the electric capacity of this second assembly or network.

Described the 3rd series network can comprise a resistor assembly, and it is formed by a planar structure that forms in a printed circuit board arrangement.The electric capacity of the 3rd series network and inductive reactance can be formed by the combination of discrete surface installation capacitor and printed circuit etch features.This surface mount capacitor can be an X2Y

Design, feed through capacitor or line capacitor (NEC for example

Proadlizer

).

3. limit-many zero optimal methods

It is when these indivedual resonance networks are formed by network group that one of this limit-zero optimal method and this limit-limit optimal method becomes more meticulous, and wherein at least one of these networks can be made up of a plurality of capacitors, wherein:

1. these electric capacity in this at least one network can use a plurality of continuous E12 series value and cross over a narrow range.For example, use 1nF, 1.2nF and 1.5nF assembly; And

2. optionally use a plurality of mounting structures, it will effectively install inductance dislocation lesser amt, be generally less than 20%.This mounting structure can comprise channel vary in diameter, channel to channel spacing, and channel to the geometry of assembly pad etching.

Compare the network of being made up of a single discrete capacitor value, the network that produces has a quality factor that reduces greatly, and in many cases, the needs of eliminating a discrete resistance assembly respond so that obtain a low quality factors.

4. 1/4th/half wave resonances optimal method

One extra optimal method comprises provides one first serial quarter-wave resonator short-term 302, and it is derived from the power division passage 301 of each IC, as shown in figure 15.Passage 301 can be positioned at PCB 110, intermediary layer 120 or IC encapsulation 130.The frequency of these first serial quarter-wave resonator short-terms 302 system is selected with these half wave resonances corresponding to the power distribution system of this not compensated.These impedances of wave resonator short-terms 302 of four minutes of these first series are to select with the linear increment frequency values, to minimize the negative effect of these half wave resonances patterns that these each first serial quarter-wave resonator short-terms 302 are produced.These half-wave patterns that also can provide a second series quarter-wave resonator short-term (not shown) to be produced by these first series, 1/4th resonator short-terms with compensation, thereby lead rose one overall frequency response, it has than obtainable the much straight impedance of a similar area of plane and layer counting.These second series 1/4th resonator short-terms can be positioned at the plane identical with this first serial quarter-wave resonator short-term maybe can be positioned at a Different Plane.This second series quarter-wave resonator short-term can be positioned at the device that is different from these first series, 1/4th resonator short-terms 302.For example, these first series, 1/4th resonator short-terms 302 can be positioned at PCB 110, and this second series quarter-wave resonator short-term can be positioned at intermediary layer 120 or 120 '.

This optimal method is best suited for this collocation structure when tying up in IC encapsulation or the intermediary layer.Yet, when this optimal method also can be used for this collocation structure and ties up in the PCB.Can cooperate the thin thin dielectric substance of this optimal method use, because these materials represent the much lower built-in quality factor because of the more height ratio of resistance skin dissipation and inductance with or without high dielectric constant material.

In many geometries of generally using, require the combination of an inaccessible material dielectric constant and thickness to utilize the quarter-wave resonator to arrive one and be lower than about 2 quality factor.The result is under essence modulation situation, and the impedance of using a planar cavity of current material is to be limited to vicinity 60 * 10 in 1GHz to the 8GHz zone ^-3Nurse shunting impedance difficult to understand.By only two similar chambeies being linked together, these impedance drops can be low to moderate 30 * 10 ^-3Nurse scope difficult to understand.This optimal method is in fact more preferably utilized available actual resource and can be used two chambeies that total impedance is reduced to 10 * 10 on this same frequency range ^-3With 20 * 10 ^-3Between the nurse difficult to understand.

5. harmonic wave suppresses

Another optimal method by optimization in from these discrete PCB level by-pass capacitors to IC electric capacity or to the change frequency of these plane bypass modules (power planes), by setting this change frequency to one produces the source at the highest frequency noise of arbitrary substantial power about 1.8 times of non-return-to-zero (NRZ) bit frequency, but be no more than the value between about 2.2 times, come minimum power allocation component cost.

This change frequency is a function of following parameters:

1. the areal concentration of these discrete by-pass capacitors: P;

2. the installation inductance of individual other bypass capacitor: L _MOUNT

3. the dielectric constant of planar cavity insulating material: ε _R* ε ₀

4. the thickness of planar cavity insulating material: H;

5. the percentage of planar cavity perforation;

6. the space mark of discrete by-pass capacitor;

7. power space is disperseed and the power that is connected to the IC of power cavity returns connection; And

8. the store energy assembly disperses or the semiconductor grain in being connected to the IC of power cavity.

This optimal method minimizes the integration of the product of combined I C/PCB/ bypass network impedance and noise source energy.This NRZ energy represents one " comb " shape frequency spectrum, wherein these peak values from the subluxation repetition rate to about 0.5 divided by the highest odd number multiple subluxation repetition rate in the signal elevating time, have a down dip with a linear gradient, surpass this signal elevating time, signal energy then descends faster.Between these Impedance Peak is substantial impedance zero.This optimal method places a resonance these in one of zero above the third harmonic of this highest possible data speed, and is general between these the 3rd and the 5th harmonic waves under 1.8 to 2.2 times of frequency speed.This placement of this resonance guarantees for an arbitrary data pattern, and the 9th harmonic wave is the minimum first rate harmonic wave of this change frequency of can aliging.Be low to moderate 1.65 value and can cooperate infringement to use, make the 7th harmonic wave of a low frequency bit patterns excite 1.75 times maximum bit rate.

Generally speaking, the capacitor of a given installation inductance that is attached to a PCB is many more, and this change frequency is just high more, wherein the reactance of the reactance cross capacitor network installation inductance of this surface plate electric capacity.Yet, for a given capacitor inductance and ESR are installed, changing quality factor in fact whenever greater than 2, add more capacitors and can't change theoretical peak impedance when changing, because when the plate condenser impedance is followed in the characteristic impedance of composite network downwards, this quality factor rises by a same slope.An one required feature that increases quality factor is a narrower percentage frequency range.This point makes easier detuning network resonate.One Techniques of Optimum are made up of following institute: select a bypass capacitor surface density, make that the generation resonance between the bypass capacitor networks of the shunting impedance that makes up any other device (for example IC) in fact can use one of aforementioned compensation technique to come to take place under the frequency of damping one.

These above-mentioned optimal methods are used in single IC on the PCB or a plurality of IC on a PCB.These optimal methods are used separably or in combination with one another.Generally speaking, this separation or make up other optimal method and use this limit-zero optimal method.

Intermediary layer

Can an intermediary layer 120,120 of discrete by-pass capacitor 122 ' be positioned between IC encapsulation 130 and the one application PCB110 will can be comprised.Preferably intermediary layer 120,120 ' can comprise a series of metal layer planes 121 (for example copper), it is stacking between organic dielectric materials.Can adopt a normal reflow or stick together program curing one IC encapsulation 130 is installed in intermediary layer 120,120 ' top.Also can use any other proper method that IC encapsulation 130 is installed.Yet intermediary layer 120,120 ' profile are in fact greater than accompanying IC envelope 130, to allow to adhere to discrete by-pass capacitor 122 and other required discrete component of this application.Intermediary layer 120,120 ' can comprise one or more power supplying functional, it uses linearity or switch mode method to implement.

Intermediary layer 120,120 ' generally uses normal reflow or conduction to stick together program curing and is attached to application PCB 110.Also can use adhere to intermediary layer 120,120 ' other proper method.

These intermediary layer power division chambeies are general respectively to be made up of thin thin (being less than or equal to about 35 μ m or about 1 mil) dielectric housing.According to design for it intermediary layer 120,120 ' the needs of IC encapsulation 130 select the thickness and the dielectric constant in each chamber.Discrete by-pass capacitor 122 generally is attached to intermediary layer 120,120 ' upper surface (IC encapsulates 130 installation sides), but also can be attached to intermediary layer 120,120 ' lower surface.The power division that is used for a single power rail can be by following composition the (1) of the sub-segments in the chamber on intermediary layer 120,120 ' whole latitude of emulsion, (2) a plurality of these type of chambeies or (3) this type of chamber in fact, as being determined by the crystal grain 133 that intermediary layer 120,120 ' designed Jie connects and the power demand of IC encapsulation 130.

Intermediary layer 120,120 ' comprise adopts arbitrary and/or whole form to use resistor assembly, comprises discrete surface installation component, planar resistor device (for example Ohmega) and/or by one cured epoxy resin/carbon and/or copper or the formed vertical resistor contact of money base matter.

Resistor assembly can adopt following arbitrary combination occur (1) this (etc.) power cavity with adhere at the application PCB on the intermediary layer bottom side between connect, (2) and intermediary layer 120,120 ' on the discrete by-pass capacitor 122 installed connect, (3) and intermediary layer 120,120 ' on these thorax sections connect, reach (4) this (etc.) the intermediary layer power cavity with connect between IC encapsulates 130.

One or more limit of intermediary layer 120,120 ' can comprise-zero is eliminated network with the resonance between (these) power cavity that suppresses discrete by-pass capacitor 122 and intermediary layer 120,120 ' interior.One or more limit of intermediary layer 120,120 ' can comprise-zero eliminate network with refusal travel to and fro between use PCB 110 in adhering to IC encapsulation 130 resonance or near the energy transmission that is occurred it.

One or more limit of intermediary layer 120,120 ' can comprise-zero eliminate network with suppress to adhere to IC encapsulation 130 and be somebody's turn to do (etc.) resonance between intermediary layer power cavity and these the discrete by-pass capacitors 122.

One or more limit of intermediary layer 120,120 ' can comprise-limit eliminate network with suppress these discrete by-pass capacitors 122 and intermediary layer 120,120 ' interior this (etc.) resonance between the power cavity.

One or more limit of intermediary layer 120,120 ' can comprise-limit eliminate network with suppress intermediary layer 120,120 ' with adhere to IC and pack resonance between 130.

Can construct intermediary layer 120,120 ' make these discrete by-pass capacitors 122 and should (etc.) be positioned at about 1.8 times to about 2.2 times of clock frequency of the highest I/O frequency on the given power rail that adheres to IC encapsulation 130 between the intermediary layer power cavity in the resonance on the given Voltage rails.

Can construct intermediary layer 120,120 ' make at compound intermediary layer 120,120 ' and adhere between the IC encapsulation 130 about 1.8 times to about 2.2 times of clock frequency that are positioned at the highest I/O frequency on the given power rail that adheres to IC encapsulation 130 in the resonance on the given Voltage rails.

Intermediary layer 120,120 ' can comprise one or more quarter-wave resonant structure, as shown in figure 15, with the mode resonance of arbitrary given power cavity of being suppressed at intermediary layer 120,120 ' interior.

Intermediary layer 120,120 ' can comprise that one or more low pass filter structure is to limit the radio-frequency component of these IC I/O signals.

Intermediary layer 120,120 ' can comprise that one or more instantaneous restraining device connects pin so that protection to be provided to one or more IC.

Intermediary layer 120,120 ' can comprise that one or more linearity or Switching power supply circuit are to regulate the power of IC encapsulation 130.Intermediary layer 120,120 ' can comprise near a power cavity of intermediary layer 120,120 ' top surface and near the mesh power chamber intermediary layer 120,120 ' bottom, it connects by a plurality of perpendicular interconnections (being generally passage) so that minimize these bypass modules that are attached to intermediary layer 120,120 ' either side and adhere to IC and encapsulate 130 and PCB 110 inductance between the two.The benefit of this type of configuration is the IC crystal grain 133 that reduces to be present in IC encapsulation 130 and use the two power supply impedance of PCB 110.Reduce impedance on the both direction this and reduce the transmission path discontinuity in order to matter, its planed signal line in PCB 110 is according to one of indivedual I/O power rails or these other voltage nodes, and from PCB 110 to intermediary layer 120,120 ' these perpendicular interconnections and IC encapsulation 130 generation when making up with reference to one of these two voltage nodes of other individual voltages node or this indivedual I/O Voltage rails.This point is improved the I/O signal fidelity simultaneously, also reduces noise, comprise can be in addition by should (etc.) EMI that propagates of PCB I/O power cavity.

With by intermediary layer 120,120 ' thin thin dielectric layer provided tight rail-to-rail coupling, intermediary layer 120,120 ' improvement enters IC encapsulation 130 return path of (not showing among Figure 21 C or the 21D), no matter use the I/O voltage plane V of signal institute reference in the signal traces on the PCB110 114 _DdOr Vss, shown in Figure 21 A and 21C and Figure 21 B and the 21D.This point allows to reduce in using PCB 110 required plane layer number and allows to improve any known PCB to construct the signal usefulness that can't mate.

Intermediary layer 120,120 ' can remap to following arbitrary purposes or the combination of arbitrary purposes to the connection of using PCB 110 with encapsulate 130 from IC:

A. reduce crosstalking between the I/O signal by best configuration more than initial IC; And

B. simplify the power interconnection of using on the PCB.

Intermediary layer 120,120 ' can comprise adhering to interconnecting to the application PCB 110 that IC encapsulates 130 peripheral outer.These interconnection can be used for following any purposes combination:

Reduce " breakthrough " from compound intermediary layer 120,120 '/these signals of IC encapsulation 130 to PCB 110 connect initial IC are connected the required application PCB number of layers of pattern;

Reduce crosstalking between the I/O signal by best configuration more than initial IC encapsulation; And

Simplify the power interconnection of using on the PCB 110.

As shown in figure 16, intermediary layer 120 ' can comprise the wing 123, its extend intermediary layer 120 with IC package interconnect array that is connected to IC encapsulation 130 ' part outside, the wing 123 is provided for the position of by-pass capacitor 122.Intermediary layer 120 ' can comprise one or more wing.Because these by-pass capacitors 122 are positioned on these wings 123, thus these by-pass capacitors 122 or its indivedual perpendicular interconnection assemblies all can't with intermediary layer 120 ' substrate and PCB 110 (showing among Figure 16) between these vertical IC package interconnects or compete mutually in these vertical IC package interconnects and these horizontal interconnect between IC encapsulation 130 or the IC crystal grain (all demonstrations in Figure 16).The heat that the position of the by-pass capacitor 122 on these wings 123 also promotes these by-pass capacitors 122 and IC crystal grain 133 heat to remove between the infrastructure is isolated.Optionally, form these wings 123 with comprise a limited number of power and power return perpendicular interconnection 124 with engage intermediary layer 120 ' substrate and PCB 110.Thus, realize following benefit:

1. on high-order assembly parts (generally using PCB 110) more, do not need the by-pass capacitor 122 and the perpendicular interconnection that is associated thereof near substrate.On the contrary, signal traces 114 easily crosses these low-density power interconnection 124, is kept the roomy overlapping of signal traces 114 simultaneously by the plane of reflection that is associated.Relatively Figure 17 and 18 can understand this point.Prior art Figure 17 shows the traditional IC encapsulation 401 that is connected to a PCB 400.By-pass capacitor 402 is attached to two surfaces of PCB 400.These by-pass capacitor interconnection 404 perforation PCB400.Must routing between these by-pass capacitor interconnection 404 and these signal interconnections 406 at the signal traces on the plane of reflection 405 403.Figure 18 shows a subassembly 411 that is connected to a PCB410, and it can be according to an intermediary layer or the IC encapsulation of these preferred embodiment of the present invention.By-pass capacitor 412 is attached to subassembly 411.These by-pass capacitors interconnection PCB 410 that can not bore a hole is because it is positioned on the subassembly 411.Only routing around these signal interconnections 416 of signal traces 413 with reference to the plane of reflection 414.

Intermediary layer 120 ' on, these by-pass capacitors 122 are engaged to voltage node by planar interconnect.Vertical signal interconnection 125 is not competed with these by-pass capacitor positions or interconnection in fact mutually.

3. rely on these by-pass capacitors 122 and IC to encapsulate these carefully thin interconnection structures between 130/ crystal grain 133 and the continuous level zone of going up these capacitors of installation thereof, minimize IC and encapsulate 130/ crystal grain 133 to by-pass capacitor 122 inductance.Relatively go up and use, in the limited extent of this encapsulation, use a thin thin dielectric layer to reduce cost at whole more high-order assembly parts (being generally PCB 110).

4. rely on the continuous level zone of these by-pass capacitors 122 of top installation, can minimize by-pass capacitor 122, thereby reduce the parallel resonance effect between the by-pass capacitor 122 of quality factor and these different values to by-pass capacitor 122 inductance.

When intermediary layer 120,120 ' substrate and PCB 110 between use extra limited vertical power interconnection, these interconnection the assembling grid that interconnects is restricted much smaller fully than one to signal routing than low-density.So, in PCB 110, can use the more signal traces 114 of every plane routing layer, as shown in figure 19.Figure 19 shows a subassembly 421 that is connected to a PCB 420, and it can be according to an intermediary layer or the IC encapsulation of one of these preferred embodiment of the present invention.By-pass capacitor 422 is attached to subassembly 421.These by-pass capacitors interconnection PCB 420 that can not bore a hole is because it is positioned on the subassembly 421.Because these power interconnection 427 are positioned at subassembly 421 peripheries, so can make these power interconnection 427 more sparse.Must be at the signal traces on the plane of reflection 425 423 in these power interconnection 427 and these signal interconnections 426 routing between the two.Yet, because these power interconnection 427 are more sparse, so the routing of these signal traces 423 is more prone to.

For example, in the typical known package under common manufacturing rule, perpendicular interconnection is made up of 10 mils boring institute, has 20 mil diameters and catches pad and 28/one-inch aperture diameter (welding resistance pad) on interconnection layer not.Utilize one of 39.4 mils (1mm) interval to assemble signal grid clear 39.4 mils between welding resistance pad tangent line fully and deduct 28 mils=11.4 mils.Generally speaking, only can be adaptive in 11.4 mils at an online signal (general 50 nurses difficult to understand on 4 mil dielectric mediums) of 4 mil marks with 4 mil spaces.One second trace will minimumly need; 4 mil traces, 4 one thousandth traces, the 24 one thousandth trace amount to 12 mils, violate these welding resistance pads slightly, and emit an electrical short risk.In addition, this welding resistance pad improves trace impedance.Intermediary layer 120 ' these wings 123 can be assembled under a low-density, for example about 78.7 mils (2mm) spacing.Under above-mentioned identical manufacturing rule, about 78.7 mils in available routing zone deduct about 28 mils=about 50.7 mils.In about 50.7 mils, but six traces of routing are equivalent to these two three traces of each row of going.Six traces of all of on whole surface, walking in addition, and or the like be not subjected to owing to cross over the interconnect influence of caused obvious impedance modulation of extra vertical power.

6. when using the interconnection of extra vertical power at intermediary layer 120,120 ' periphery, bigger effective radius of clean-up of this interconnection improve in fact intermediary layer 120,120 ' and PCB 110 between perpendicular interconnection inductance and reduce intermediary layer 120,120 ' and PCB 110 between inductance, thereby improvement with respect to PCB 110 intermediary layer 120,120 ' on the noise filtering usefulness of included these capacitors 122.

7. when the vertical power interconnection was limited to IC encapsulation 130 peripheries, shown in comparison diagram 20A and 20B, the less inductance that can handle these encapsulation internal power chambeies injected with the high-frequency noise that raising IC encapsulates between 130/ crystal grain 133 and the PCB110.

Figure 20 A shows an interconnection array, and it comprises V _SsPower interconnection 501 and V _DdPower interconnection 502 and signal interconnection 503.At V _SsPower interconnection 501 and V _DdDistance between the power interconnection 502 is 1.4 times of spacing between about adjacent interconnection.Signal interconnection and nearest V _DdPower interconnection 502/V _SsPower interconnection 501 couplings 70% and with nearest V _SsPower interconnection 501/V _DdPower interconnection 502 couplings 30%.Since this interconnection configuration and shown in the circuit diagram of Figure 20 B, 70% or 30% energy still along path A with reference to Vss and 30% or 70% energy turns to by this power network wiring.

Figure 20 C also shows an interconnection array, and it comprises V _SsPower interconnection 501 and V _DdPower interconnection 502 and signal interconnection 503.Yet these signal interconnections 503 are with the array configuration, have a plurality of V _SsPower interconnection 502 intersperses among in signal interconnection 503 arrays, and these V _SsPower interconnection 501 and V _DdPower interconnection 502 is disposed at signal interconnection 503 array outsides.Be disposed at the adjacent Vss power interconnection 501 and the V of signal interconnection 503 arrays outside _DdDistance between the power interconnection approximately is the spacing between the adjacent interconnection.Signal interconnection 503 and nearest V _SsPower interconnection 501 couplings 70% and with next nearest V _SsPower interconnection 501 couplings 30%.Because this interconnection configuration and shown in Figure 20 D circuit diagram, in fact 100% energy still along path C with reference to V _SsAnd 0% energy turns to by this power network wiring.

8. when these vertical power interconnection were limited to IC encapsulation 130 peripheries, shown in comparison diagram 20A and 20B and Figure 20 C and 20D, all vertical signals returned and can be generally signal and share with reference to a signal reflex reference.Under these conditions, impedance, allow inductance and therefore intermediary layer 120,120 ' and PCB110 between the power number of interconnections by power send determine but not determined by signal cross-talk/power resilience demand.

The IC encapsulation

Shown in Figure 12 and 14, IC encapsulation 130 can comprise the discrete by-pass capacitor 132 that is positioned on the encapsulated integrated circuit periphery, wherein IC encapsulation 130 has been extended to its signal and power and has sent and connect outside the common required border of pin.IC encapsulation 130 generally is made up of a series of metals plane 131 (for example copper), and it is stacking between organic dielectric materials, as the part of an IC standard canned program.Can adopt a normal reflow or stick together program curing and one IC encapsulation 133 is installed in IC encapsulates 130 tops.IC crystal grain 133 can be mounted to IC encapsulation 130 by any proper method.IC encapsulation 130 defeated exterior features are required usually greater than IC crystal grain 133 in fact, to allow adhering to extra by-pass capacitor 132 and other discrete component (not shown) by application requirements.IC encapsulation 130 can comprise one or more switch mode power supplying functional.

IC encapsulation 130 can be attached to an intermediary layer 120,120 '; shown in Figure 12 and 14; maybe can use any proper method and directly be attached to application PCB 110, comprise and use normal reflow, conduction to stick together program curing, connect pin or platform grid structure of arrays, socket or other interpositioning.

These IC package power distribution cavity are general respectively to be made up of thin thin (being less than or equal to about 35 μ m or about 1 mil) dielectric housing.Need select each chamber thickness and dielectric constant according to the IC encapsulation that designs IC encapsulation 130 for it.The upper surface that by-pass capacitor 132 can be attached to IC encapsulation 130 maybe can embed in the IC encapsulation 130.The power division that is used for a single power rail can comprise: (1) encapsulates a chamber on the whole latitude of emulsion at this IC in fact; (2) a plurality of these type of chambeies; Or a sub-segments in (3) this type of chamber, such as the power of IC crystal grain 133 and IC encapsulation 130 need decision.

IC encapsulation 130 can comprise adopts arbitrary and/or whole form to use resistor assembly, comprises discrete surface installation component, planar resistor device (for example Ohmega) and/or by one cured epoxy resin/carbon and/or copper or the formed vertical resistor contact of money base matter.

Resistor assembly can adopt following arbitrary combination and occur: (1) in this (etc.) power cavity connects between the PCB 110 with using; (2) be installed in IC encapsulation 130 on these discrete by-pass capacitors 132 connect; (3) connect with these chamber away minor segment in the IC encapsulation 130; And (4) in this (etc.) package power chamber and IC connect between encapsulating 130.

IC encapsulation 130 can comprise one or more limit-zero eliminate network with suppress being somebody's turn to do in these discrete capacitors and the IC encapsulation 130 (etc.) resonance between the power cavity.IC encapsulation 130 can comprise that one or more limit-zero eliminates network and travel to and fro between with refusal and use PCB 110 at resonance or near occurred it energy transmission.

IC encapsulation 130 can comprise one or more limit-zero eliminate network with suppress to adhere to crystal grain 133 and be somebody's turn to do (etc.) resonance between IC package power chamber and these by-pass capacitors 132.

IC encapsulation 130 can comprise one or more limit-limit eliminate network with suppress being somebody's turn to do in these discrete by-pass capacitors 132 and the IC encapsulation 130 (etc.) resonance between the power cavity.

IC encapsulation 130 can comprise that one or more limit-limit eliminates network to suppress IC encapsulation 130 and to adhere to resonance between the IC crystal grain 133.

Can construct IC encapsulation 130 make these discrete by-pass capacitors 132 with this (etc.) be positioned at about 1.8 times to about 2.2 times of clock frequency of the highest I/O frequency on the given power rail that adheres to IC crystal grain 133 between the package power chamber in the resonance on the given Voltage rails.

Can construct IC encapsulation 130 makes and adheres to about 1.8 times to about 2.2 times of clock frequency that IC encapsulates the highest I/O frequency on 130 the given power rail in these compound IC encapsulation 130 with adhering between the IC crystal grain 133 to be positioned in the resonance on the given Voltage rails.

IC encapsulation 130 can comprise that one or more quarter-wave resonant structure is to suppress the mode resonance of the arbitrary given power cavity in the IC encapsulation 130.

IC encapsulation 130 can comprise that one or more low pass filter structure is to be limited in the radio-frequency component that comes and goes these IC I/O signals that transmit between the power routes of using PCB 110.

IC encapsulation 130 can comprise that one or more instantaneous restraining device connects pin so that protection to be provided to one or more IC.

IC encapsulation 130 can comprise that one or more linearity or power switched supply circuit are to regulate the power of IC encapsulation 130.IC encapsulation 130 can be included near IC and encapsulate a power cavity at 130 top surface places and near the mesh power chamber IC encapsulates 130 tops, and this mesh power chamber is attached to IC and encapsulates 130 these bypass modules and the inductance between the PCB 110 to minimize by a plurality of perpendicular interconnections (being generally passage) connection.The benefit of this type of configuration is to reduce to be present in IC crystal grain 133 and use the two power supply impedance of PCB 110.On both direction this reduces impedance in order to reduce the transmission path discontinuity in fact, it betides a planed signal line in the PCB 110 with reference to one of indivedual I/O power rails or these other voltage nodes, and from these perpendicular interconnections of PCB 110 to IC encapsulation 130 during with reference to the combination of one of these two voltage nodes of other individual voltages node or indivedual I/O Voltage rails.Thereupon, this point is improved the I/O signal fidelity simultaneously, and reduces noise, comprise in addition by should (etc.) use the EMI that PCB I/O power cavity is propagated.

With the tight rail-to-rail coupling that these thin thin dielectric layers provided, IC encapsulation 130 improvement enter the return path in the IC crystal grain 133, no matter use the I/O voltage plane of signal institute reference.This point allows can reduce to use required plane layer number in the PCB 110.

IC encapsulation 130 can will be remapped from IC crystal grain 133 to the common connection of using PCB 110 to arbitrary purposes or the combination of arbitrary purposes:

● reduce crosstalking between the I/O signal by best configuration more than known IC crystal grain; And

● simplify the power interconnection of using on the PCB 110.

IC encapsulation 130 can encapsulate known peripheral outer at this IC and comprise to the interconnection of adhering to of using PCB 110.These interconnection can be used for any purposes combination:

● reduce " breakthrough " and connect from these signals of IC encapsulation 130 to PCB 110 initial IC is connected the required application PCB number of layers of pattern;

● reduce crosstalking between the I/O signal by best configuration more than known IC encapsulation; And

● simplify the power interconnection of using on the PCB 110.

Therefore the applicant incorporates the subject content that U.S. patent application case is disclosed for the 60/804th, 089,60/887,148 and 60/887, No. 149 into reform.

Should understand only illustration the present invention of above stated specification.Known this operator can design and variously substitute and revise and do not break away from the present invention.Therefore, the invention is intended to contain all substitutes, revises and change and the category that do not break away from appended claims.

Claims

1. method that is used to supply power to one integrated circuit comprises:

This integrated circuit is provided;

One power routes network is provided, has one first assembly and second assembly, this first assembly has an inductance L ₁And this second assembly has a capacitor C ₂And

One current-dividing network is provided, has and equal or near a string vibration frequency of allying the communists of the vibration frequency of allying the communists in the lump of described first and second assembly.

2. the method for claim 1, wherein this current-dividing network has one 2 or following quality factor.

3. the method for claim 1, wherein this current-dividing network has one 1.4 or following quality factor.

4. the method for claim 1, wherein the reactance component of this current-dividing network has one and surpasses 2.0 * √ (L ₁/ C ₂) characteristic impedance.

5. the method for claim 1, it further comprises the resonance behavior that suppresses or get rid of this power routes network by a net phase position feature that changes this power routes network.

6. the method for claim 1, wherein this current-dividing network has a plurality of branches;

Each branch of these a plurality of branches have its oneself zero, make the self-impedance of this current-dividing network remain on 135 ° of power routes network self-impedance phase place of any point place in this power routes network electrically in.

7. the method for claim 1, wherein this current-dividing network series connection is inserted between this first assembly and this second assembly.

8. the method for claim 1, wherein when by this first assembly load, this current-dividing network has and equals or near the vibration frequency of allying the communists in the lump of the vibration frequency of allying the communists in the lump of this first assembly and this second assembly.

9. the method for claim 1, wherein this current-dividing network is made up of a network group; And

At least one network of this network group is made up of a plurality of capacitor.

10. method as claimed in claim 9, wherein the electric capacity of these a plurality of capacitors uses a plurality of continuous E12 series value and crosses over a narrow range.

11. the method for claim 1, wherein at least a portion of this current-dividing network be provided within the intermediary layer or on.

12. the method for claim 1, wherein at least a portion of this current-dividing network be provided in one have within the intermediary layer of the wing or on.

13. the method for claim 1, wherein at least a portion of this current-dividing network and this integrated circuit be provided within the single encapsulation or on.

14. the method for claim 1, wherein at least a portion of this current-dividing network be provided in to install within the circuit board of this integrated circuit or on.

15. a method that is used to supply power to one integrated circuit, it comprises:

This integrated circuit is provided;

The one power routes network with a channel is provided; And

Provide one first serial quarter-wave resonator short-term to this channel; Wherein

When this power routes network of uncompensation, the frequency of selecting this first serial quarter-wave resonator short-term is with the half wave resonances corresponding to this power routes network.

16. method as claimed in claim 15, wherein the impedance of selecting this first serial quarter-wave resonator short-term with the linear increment frequency values is with the negative effect of the half wave resonances that minimizes this each first serial quarter-wave resonator short-term and produced.

17. method as claimed in claim 15, it further comprises to this channel provides a second series quarter-wave resonator short-term, is to select to compensate the half wave resonances that this first serial quarter-wave resonator short-term is produced.

18. method as claimed in claim 15, wherein this first serial quarter-wave resonator short-term is provided in the intermediary layer.

19. method as claimed in claim 15, wherein this first serial quarter-wave resonator short-term is provided in one and has in the intermediary layer of the wing.

20. method as claimed in claim 15, wherein this first serial quarter-wave resonator short-term and this integrated circuit be provided within the single encapsulation or on.

21. method as claimed in claim 15, wherein this first serial quarter-wave resonator short-term is provided in to install in the circuit board of this integrated circuit.

22. a method that is used to supply power to one integrated circuit, it comprises:

One integrated circuit is provided;

One circuit board is provided;

At least one discrete by-pass capacitor is provided on this circuit board; And

One change frequency is set to a value, and this is worth between about 1.65 times to about 2.2 times of a non-homing type rotary switch frequency in the highest frequency noise generation source of arbitrary substantial power; Wherein

This change frequency is from the electric capacity of this at least one discrete by-pass capacitor in this integrated circuit or at least one plane bypass module.

23. an intermediary layer, it comprises:

One substrate, it has first and second surface; And

One current-dividing network; Wherein

This first surface is configured in order to can be attached to a circuit board;

This second surface is configured in order to can be connected to integrated circuit encapsulation; And

This current-dividing network has a string vibration frequency of allying the communists, this resonance series frequency equal or the power routes network that will connect near this intermediary layer one have an inductance L ₁First assembly and have a capacitor C ₂The vibration frequency of allying the communists in the lump of second assembly.

24. intermediary layer as claimed in claim 23, wherein this substrate comprises at least one wing.

25. intermediary layer as claimed in claim 23, wherein this current-dividing network has one 2 or following quality factor.

26. intermediary layer as claimed in claim 23, wherein this current-dividing network has one 1.4 or following quality factor.

27. intermediary layer as claimed in claim 23, wherein the reactance component of this current-dividing network has one above 2.0 * √ (L ₁/ C ₂) characteristic impedance.

28. intermediary layer as claimed in claim 23, wherein this current-dividing network is configured in order to suppress or to get rid of the resonance behavior of this power routes network by a net phase position feature that changes this power routes network when this current-dividing network is connected to a power routes network.

29. intermediary layer as claimed in claim 23, wherein this current-dividing network comprises a plurality of branches;

Each branch of these a plurality of branches have its oneself zero, make when this current-dividing network is connected to a power routes network, the self-impedance of this current-dividing network remain on 135 ° of this power routes network self-impedance phase place at any point place in this power routes network electrical in.

30. intermediary layer as claimed in claim 23, wherein this current-dividing network is configured to be inserted between this first assembly and this second assembly in order to series connection.

31. intermediary layer as claimed in claim 23, wherein when by this first assembly load, this current-dividing network has and equals or near the vibration frequency of allying the communists in the lump of the vibration frequency of allying the communists in the lump of this first assembly and this second assembly.

32. intermediary layer as claimed in claim 23, wherein this current-dividing network comprises a network group; And

33. intermediary layer as claimed in claim 32, wherein the electric capacity of these a plurality of capacitors uses a plurality of continuous E12 series value and crosses over a narrow range.

34. an intermediary layer, it comprises:

One substrate, it has first and second surface;

One passage, it is placed in this substrate; And

One first serial quarter-wave resonator short-term, it is connected to this passage; Wherein

This first surface is configured in order to be connected to a circuit board;

This second surface is configured in order to be connected to integrated circuit encapsulation; And

When uncompensation one power routes network, the frequency of this first serial quarter-wave resonator short-term is corresponding to the half wave resonances of this power routes network.

35. intermediary layer as claimed in claim 34, wherein the impedance of this first serial quarter-wave resonator short-term on frequency values linear increment with the negative effect of the half wave resonances pattern that minimizes this each first serial quarter-wave resonator short-term and produced.

36. intermediary layer as claimed in claim 34, it further comprises a second series quarter-wave resonator short-term, is configured in order to compensate the half wave resonances that this first serial quarter-wave resonator short-term is produced.

37. an integrated circuit encapsulation, it comprises:

One substrate;

One integrated circuit crystal grain, be placed within this substrate or on; And

One current-dividing network; Wherein

One surface configuration of this substrate becomes in order to be connected to a circuit board;

This current-dividing network has a string vibration frequency of allying the communists, this resonance series frequency equal or the power routes network that will connect near the encapsulation of this integrated circuit one have an inductance L ₁First assembly and have a capacitor C ₂The vibration frequency of allying the communists in the lump of second assembly.

38. integrated circuit encapsulation as claimed in claim 37, wherein this substrate comprises at least one wing.

39. integrated circuit as claimed in claim 37 encapsulation, wherein this current-dividing network has one 2 or following quality factor.

40. integrated circuit as claimed in claim 37 encapsulation, wherein this current-dividing network has one 1.4 or following quality factor.

41. integrated circuit encapsulation as claimed in claim 37, wherein the reactance component of this current-dividing network has one above 2.0 * √ (L ₁/ C ₂) characteristic impedance.

42. integrated circuit encapsulation as claimed in claim 37, wherein this current-dividing network is configured in order to suppress or to get rid of the resonance behavior of this power routes network by a net phase position feature that changes this power routes network when this current-dividing network is connected to a power routes network.

43. integrated circuit encapsulation as claimed in claim 37, wherein this current-dividing network comprises a plurality of branches;

44. integrated circuit encapsulation as claimed in claim 37, wherein this current-dividing network is configured to be inserted between this first assembly and this second assembly in order to series connection.

45. integrated circuit as claimed in claim 37 encapsulation, wherein when by this first assembly load, this current-dividing network has and equals or near the vibration frequency of allying the communists in the lump of the vibration frequency of allying the communists in the lump of this first assembly and this second assembly.

46. integrated circuit encapsulation as claimed in claim 37, wherein this current-dividing network comprises a network group; And

47. integrated circuit encapsulation as claimed in claim 46, wherein the electric capacity of these a plurality of capacitors uses a plurality of continuous E12 series value and crosses over a narrow range.

48. an integrated circuit encapsulation, it comprises:

One substrate;

One integrated circuit crystal grain, be placed within this substrate or on;

One passage, it is placed in this substrate; And

One of this substrate surface configuration becomes in order to be connected to a circuit board; And

49. integrated circuit as claimed in claim 48 encapsulation, wherein the impedance of this first serial quarter-wave resonator short-term on frequency values linear increment with the negative effect of the half wave resonances that minimizes each first serial quarter-wave resonator short-term and produced.

50. integrated circuit encapsulation as claimed in claim 48, it further comprises a second series quarter-wave resonator short-term, is configured in order to compensate the half wave resonances pattern that this first serial quarter-wave resonator short-term is produced.

51. an intermediary layer, it comprises:

One substrate, it has first and second surface; And

One current-dividing network; Wherein

At least a portion of this current-dividing network is positioned near the periphery place of this substrate or its;

This first surface is configured in order to be attached to a circuit board; And

This second surface is configured in order to be connected to integrated circuit encapsulation.

52. medium as claimed in claim 51, wherein this current-dividing network comprises at least one capacitor, and it is to be disposed near the periphery place of this substrate or its.

53. medium as claimed in claim 51, this current-dividing network have a string vibration frequency of allying the communists, this resonance series frequency equal or the power routes network that will connect near this intermediary layer one have an inductance L ₁First assembly and have a capacitor C ₂The vibration frequency of allying the communists in the lump of second assembly.

54. medium as claimed in claim 51, wherein this substrate comprises at least one wing.

55. medium as claimed in claim 51, wherein this current-dividing network has one 2 or following quality factor.

56. medium as claimed in claim 51, wherein this current-dividing network has one 1.4 or following quality factor.

57. medium as claimed in claim 51, wherein the reactance component of this current-dividing network has one above 2.0 * √ (L ₁/ C ₂) characteristic impedance.

58. medium as claimed in claim 51, wherein this current-dividing network is configured in order to suppress or to get rid of the resonance behavior of this power routes network by a net phase position feature that changes this power routes network when this current-dividing network is connected to a power routes network.

59. medium as claimed in claim 51, wherein this current-dividing network comprises a plurality of branches; And

60. medium as claimed in claim 51, wherein this current-dividing network is configured to be inserted between this first assembly and this second assembly in order to series connection.

61. medium as claimed in claim 51, wherein when by this first assembly load, this current-dividing network has and equals or near the vibration frequency of allying the communists in the lump of the vibration frequency of allying the communists in the lump of this first assembly and this second assembly.

62. medium as claimed in claim 51, wherein this current-dividing network is made up of a network group; And

63. medium as claimed in claim 62, wherein the electric capacity of these a plurality of capacitors uses a plurality of continuous E12 series value and crosses over a narrow range.

64. medium as claimed in claim 51, it further comprises:

One is disposed at the interior interconnection array of a part of this substrate, and it is used to be connected to this circuit board and is used to be connected to this integrated circuit encapsulation; And

At least one wing is disposed at the peripheral outer of this part of this substrate with this interconnection array; Wherein

This at least a portion of this current-dividing network be positioned on this at least one wing or within.

65. an integrated circuit encapsulation, it comprises:

One substrate;

One current-dividing network; Wherein

One surface configuration of this substrate becomes in order to be connected to a circuit board; And

At least a portion of this current-dividing network is positioned near the periphery place of this substrate or its.

66. as the encapsulation of the described integrated circuit of claim 65, wherein this current-dividing network comprises at least one capacitor, is disposed near the periphery place of this substrate or its.

67. as the encapsulation of the described integrated circuit of claim 65, this current-dividing network has a string vibration frequency of allying the communists, this resonance series frequency equal or the power routes network that will connect near this integrated circuit encapsulation one have an inductance L ₁First assembly and have a capacitor C ₂The vibration frequency of allying the communists in the lump of second assembly.

68. as the described integrated circuit encapsulation of claim 65, wherein this substrate comprises at least one wing.

69. as the encapsulation of the described integrated circuit of claim 65, wherein this current-dividing network has one 2 or following quality factor.

70. as the encapsulation of the described integrated circuit of claim 65, wherein this current-dividing network has one 1.4 or following quality factor.

71. as the described integrated circuit encapsulation of claim 65, wherein the reactance component of this current-dividing network has one above 2.0 * √ (L ₁/ C ₂) characteristic impedance.

72. as the described integrated circuit encapsulation of claim 65, wherein this current-dividing network is configured in order to suppress or to get rid of the resonance behavior of this power routes network by a net phase position feature that changes this power routes network when this current-dividing network is connected to a power routes network.

73. as the described integrated circuit encapsulation of claim 65, wherein this current-dividing network comprises a plurality of branches; And

74. as the described integrated circuit encapsulation of claim 65, wherein this current-dividing network is configured to be inserted between this first assembly and this second assembly in order to series connection.

75. as the encapsulation of the described integrated circuit of claim 65, wherein when by this first assembly load, this current-dividing network has and equals or near the vibration frequency of allying the communists in the lump of the vibration frequency of allying the communists in the lump of this first assembly and this second assembly.

76. as the described integrated circuit encapsulation of claim 65, wherein this current-dividing network is made up of a network group; And

77. as the described integrated circuit encapsulation of claim 76, wherein the electric capacity of these a plurality of capacitors uses a plurality of continuous E12 series value and crosses over a narrow range.

78. as the described integrated circuit encapsulation of claim 65, it further comprises:

One is disposed at the interior interconnection array of a part of this substrate, and it is used to be connected to this circuit board and is used to be connected to this integrated circuit crystal grain; And