CN101465349B - Semiconductor device - Google Patents
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- CN101465349B CN101465349B CN200710160825XA CN200710160825A CN101465349B CN 101465349 B CN101465349 B CN 101465349B CN 200710160825X A CN200710160825X A CN 200710160825XA CN 200710160825 A CN200710160825 A CN 200710160825A CN 101465349 B CN101465349 B CN 101465349B
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Abstract
The invention provides a semiconductor device, which comprises a protected element and an electrostatic discharge power clamp element; the protected element is located in a protected element region ofa substrate; the electrostatic discharge power clamp element is located in a protective ring region of the substrate and encircles the protected element; the electrostatic discharge power clamp element comprises a first protective ring and a second protective ring; the first protective ring comprises a first well region which is provided with a first conductive type, a first doped region and a second doped region which are located inside the first well region; the first doped region and the second doped region are respectively provided with the first conductive type and a second conductive type; the second protective ring comprises a second well region provided with the second conductive type, and a third doped region which is located in the second well region and provided with the secondconductive type. The invention can increase the noise isolation effect of the protective rings and does not need additional space for containing the ESD power clamp element, thereby greatly saving the chip area.
Description
Technical field
The invention relates to a kind of semiconductor device, particularly relevant for a kind of semiconductor device with static discharge power clamping (electrostatic discharge power clamp) element.
Background technology
Along with the continuous progress of semiconductor fabrication process shrink technology, it is increasingly important how to promote the semiconductor device reliability.Yet, semiconductor device manufacture, process, assemble, transport, in the process such as use, whole flow process all can suffer the threat of Electrostatic Discharge, if no suitable safeguard procedures, semiconductor device will be damaged and can't sell.Therefore, protecting component for electrostatic discharge is designed to the necessary technology of any semiconductor device.(System on a Chip, SoC), because its size of component is little, when suffering static discharge, element can be damaged by electrostatic induced current, and causes the whole system single-chip to lose efficacy to the system single chip that utilizes sophisticated semiconductor manufacturing process made especially.In addition, extra electrostatic storage deflection (ESD) protection circuit can make chip area increase, and can't reach the requirement of high component density.
In this technical field, the semiconductor device that needs a kind of high element reliability and high component density is arranged.
Summary of the invention
One embodiment of the invention provide a kind of semiconductor device, comprise a substrate, and it comprises a protected element region, a protective ring district and an outer member district, and aforesaid substrate has one first conduction type; One protected element is arranged in above-mentioned protected element region; One static discharge power is clamped down on element, be arranged in above-mentioned protective ring district, and surround above-mentioned protected element, above-mentioned static discharge power is clamped down on element and is comprised one first outside protective ring and one second inner protective ring, wherein above-mentioned first protective ring comprises: one first wellblock, and it has above-mentioned first conduction type; One first doped region and one second doped region are arranged in above-mentioned first wellblock, and are adjacent to the surface of aforesaid substrate, and wherein above-mentioned first doped region and above-mentioned second doped region have above-mentioned first conduction type and one second conduction type respectively; Above-mentioned second protective ring comprises: one second wellblock, and it has above-mentioned second conduction type; One the 3rd doped region is arranged in above-mentioned second wellblock, and is adjacent to the surface of aforesaid substrate, and wherein above-mentioned the 3rd doped region has above-mentioned second conduction type; One I/O element is arranged in the outer member district, and is coupled to above-mentioned static discharge power and clamps down on element, and wherein said first wellblock and described second wellblock separate each other.
Another embodiment of the present invention provides a kind of semiconductor device, comprises a substrate, and it comprises a protected element region, a protective ring district and an outer member district, and aforesaid substrate has one first conduction type; One protected element is arranged in above-mentioned protected element region; One static discharge power is clamped down on element, be arranged in above-mentioned protective ring district, and surround above-mentioned protected element, above-mentioned static discharge power is clamped down on element and is comprised one first outside protective ring and one second inner protective ring, wherein above-mentioned first protective ring comprises: one first wellblock, and it has above-mentioned first conduction type; One first doped region and one second doped region are arranged in above-mentioned first wellblock, and are adjacent to the surface of aforesaid substrate, and wherein above-mentioned first doped region and above-mentioned second doped region have above-mentioned first conduction type and one second conduction type respectively; Above-mentioned second protective ring comprises: one second wellblock, and it has above-mentioned second conduction type; One the 3rd doped region is arranged in above-mentioned second wellblock, and is adjacent to the surface of aforesaid substrate, and wherein above-mentioned the 3rd doped region has above-mentioned second conduction type; One I/O element is arranged in the outer member district, and is coupled to above-mentioned static discharge power and clamps down on element.
The present invention can increase the usefulness of protective ring noise isolation, does not need additional space to put ESD power clamping element, can greatly save chip area.
Description of drawings
Fig. 1 is the partial circuit figure of the semiconductor device of the embodiment of the invention.
Fig. 2 a, Fig. 2 b are the partial circuit layout of the semiconductor device of one embodiment of the invention.
Fig. 2 c is the fragmentary cross-sectional view along the A-A ' tangent line of Fig. 2 a.
Fig. 3 a, Fig. 3 b are the partial circuit layout of the semiconductor device of another embodiment of the present invention.
Fig. 3 c is for being the fragmentary cross-sectional view along the A-A ' tangent line of Fig. 3 a.
Drawing reference numeral
100～semiconductor device; 102～protected element;
104～electric static discharge protector; 106～static discharge power is clamped down on element;
108～I/O element; 110～weld pad;
200a, 200b, 200c, 200d～circuit layout;
202～protected element; 201～substrate;
206a, 206b, 206c, 206d～static discharge power are clamped down on element;
208～I/O element; 210～weld pad;
212～the second wellblocks; 214～the first wellblocks;
216～the 3rd doped regions; 218～the 4th doped regions;
220～the first doped regions; 222～the second doped regions;
226a, 226b～first protective ring; 228a, 228b～second protective ring;
230～separator with shallow grooves; 251～protected element region;
252～protective ring district; 253～outer member district;
VDD～high power end; VSS～low power end;
GND～earth terminal.
Embodiment
Below utilize figure attached, to illustrate in greater detail the semiconductor device of the embodiment of the invention.Fig. 1 is the partial circuit figure of the semiconductor device of the embodiment of the invention.Fig. 2 a, Fig. 2 b are the partial circuit layout of the semiconductor device of one embodiment of the invention.Fig. 2 c is the fragmentary cross-sectional view along the A-A ' tangent line of Fig. 2 a or Fig. 2 b.Fig. 3 a, Fig. 3 b are the partial circuit layout of the semiconductor device of another embodiment of the present invention.Fig. 3 c is the fragmentary cross-sectional view along the A-A ' tangent line of Fig. 3 a or Fig. 3 b.In various embodiments of the present invention, the identical or similar elements of identical symbolic representation.
Please refer to Fig. 1, it shows the partial circuit figure of the semiconductor device 100 of the embodiment of the invention.The main element of semiconductor device 100 comprises protected element 102, electrostatic discharge (ESD) protection (electrostaticdischarge; ESD) element 104 (hereinafter to be referred as esd protection element 104), static discharge power clamping (ESD power clamp) element 106 (hereinafter to be referred as ESD power clamping element 106), I/O (input/output, IO) element 108 (hereinafter to be referred as IO element 108) and weld pad 110.As shown in Figure 1, esd protection element 104 is coupled to protected element 102 and IO element 108 via high power end VDD or low power end VSS.ESD power clamping element 106 is coupled to protected element 102 and esd protection element 104 via high power end VDD or low power end VSS.And IO element 108 is coupled to weld pad 110.
Protected element 102 can comprise for example core parts (core device) or other element that needs esd protection element 104 to be protected.In embodiments of the present invention, esd protection element 104 can comprise diode (bipolar), transistor (transistor) or its combination.ESD power clamping element 106 is used for limiting the power bracket of esd protection element 104.IO element 108 is in order to provide power supply or data signal to protected element 102; it can comprise metal oxide semiconductor field effect transistor (metal-oxide-semiconductorfield-effect transistor; MOS transistor); the programmble read only memory PROM (EPROM) of can erasing; the electronics programmble read only memory PROM (EEPROM) of can erasing; static random access memory (SRAM); DRAM (Dynamic Random Access Memory) (DRAM); single-electronic transistor (Single electron transistor, SET); diode; electric capacity; inductance or its combination.
Fig. 2 a, Fig. 2 b, Fig. 3 a, Fig. 3 b are the partial circuit layout (circuit layout) of the semiconductor device of different embodiments of the invention.Fig. 2 a shows partial circuit layout (circuit layout) 200a of the semiconductor device of the embodiment of the invention; circuit layout 200a mainly has three zones, is respectively protected element region 251, protective ring (guard ring) district 252 and outer member district 253.In embodiments of the present invention, protected element 202 is disposed in the protection component district 251; (input/output, IO) element 208 (hereinafter to be referred as IO element 208) and weld pad 210 are disposed in the outer member district 253 in I/O.And static discharge power clamping (ESD power clamp) element 206a (hereinafter to be referred as ESD power clamping element 206a) is disposed in the protective ring district 252, and surrounds protected element 202 in fact.Shown in Fig. 2 a, above-mentioned protected element 202, ESD power clamping element 206a and IO element 208 all are positioned on the substrate 201.ESD power clamping element 206a is coupled to protected element 202 and IO element 208, and weld pad 210 is coupled to IO element 208.In another embodiment of the present invention, outer member district 253 more comprises an electric static discharge protector (figure does not show), and it is coupled to protected element 202 and IO element 208.
Shown in Fig. 2 a, ESD power clamping element 206a comprises one first outside protective ring 226a and one second inner protective ring 228a.The first protective ring 226a comprises one first wellblock 214, one first doped region 220 and one second doped region 222a.In embodiments of the present invention, the conduction type of first wellblock 214 can be identical with the conduction type of substrate 201, for example can be considered a p type wellblock 214.First doped region 220 and the second doped region 222a are arranged in first wellblock 214, and are adjacent to the surface of substrate 201.Shown in Fig. 2 a, the second doped region 222a is a plurality of discontinuous doped regions, and it can (shallow trench isolation STI) separates by a plurality of separator with shallow grooves.In embodiments of the present invention, first doped region 220 and the second doped region 222a can surround protected element 202 respectively in fact, and parallel to each other.In embodiments of the present invention, first doped region 220 and the second doped region 222a can have opposite each other conduction type, and the dopant concentration of first doped region 220 and the second doped region 222a for example can be greater than the dopant concentration of first wellblock 214.Therefore, when first doped region 220 can be considered a n type heavy doping (n+) district 220, the second doped region 222a then can be considered a p type heavy doping (p+) district 222a.Perhaps, when can be considered a p type heavy doping (p+) district 220, the second doped region 222a, first doped region 220 then can be considered a n type heavy doping (n+) district 222a.For the purpose of narrating conveniently, in embodiments of the present invention, first doped region 220 can be a p type heavy doping (p+) district 220, and the second doped region 222a can be a n type heavy doping (n+) district 222a.In addition, the second protective ring 228a comprises one second wellblock 212 and one the 3rd doped region 216.In embodiments of the present invention, the conduction type of second wellblock 212 can with the conductivity type opposite of substrate 201, for example can be considered a n type wellblock 212.The 3rd doped region 216 is arranged in second wellblock 212, and is adjacent to the surface of substrate 201.Shown in Fig. 2 a, the 3rd doped region 216 can surround protected element 202 in fact, and can be parallel to each other with first doped region 220 and the second doped region 222a.The 3rd doped region 216 is with above-mentioned first doped region 220 and the second doped region 222a can (shallow trench isolation STI) separates by a plurality of separator with shallow grooves.Wherein the conduction type of the 3rd doped region 216 can be identical with the conduction type of second wellblock 212, and its dopant concentration for example can be greater than the dopant concentration of second wellblock 212.In embodiments of the present invention, the 3rd doped region 216 can be considered a n type heavy doping (n+) district 216.
Fig. 2 b shows partial circuit layout (circuitlayout) 200b of the semiconductor device of another embodiment of the present invention.Wherein the second doped region 222b of ESD power clamping element 206b is a continuous doped region.
Fig. 2 c shows the profile of ESD power clamping element 206a.Wherein first wellblock 214 and second wellblock 212 separate each other by separator with shallow grooves 230.Similarly, first doped region 220, the second doped region 222a and the 3rd doped region 216 separate each other by separator with shallow grooves 230.In one embodiment of this invention, the 3rd doped region 216 can be coupled to a high power end VDD, and first doped region 220, the second doped region 222a then can be coupled to a low power end VSS simultaneously.Shown in Fig. 2 c, first doped region 220, the second doped region 222a can be coupled to earth terminal GND.N type-p type-n type that the n type second doped region 222a of ESD power clamping element 206a, p type first wellblock 214, p type substrate 201, n type second wellblock 212 and n type the 3rd doped region 216 constitute a parasitism connects face two-carrier transistor (NPNbipolar junction transistor is hereinafter to be referred as NPN BJT).Wherein the n type second doped region 222a can be considered the emitter-base bandgap grading (emitter) of the NPN BJT of above-mentioned parasitism, p type substrate 201 and p type second wellblock 214 can be considered the base stage (base) of the NPN BJT of above-mentioned parasitism, and n type second wellblock 212 and n type the 3rd doped region 216 can be considered the collection utmost point (collector) of the NPN BJT of above-mentioned parasitism.When n type the 3rd doped region 216 couples paramount power end VDD, when first doped region 220 and the second doped region 222a are ground connection GND, can be considered above-mentioned parasitism NPN BJT the indirect forward bias voltage drop of emitter-base bandgap grading-base stage and base stage-collection interpolar connects reverse bias, this mode of operation, we are called forward initiatively bias voltage.When suffering ESD or during from the bombardment (zapping) of high power end VDD, the NPN BJT of above-mentioned parasitism can form from weld pad 210 to substrate 201 path, and therefore a large amount of electronics can inject base stage (p type substrate 201 and p type second wellblock 214) by emitter-base bandgap grading (n type heavy doping (n+) district 222a).Hence one can see that, and ESD power clamping element 206a can conduct a large amount of ESD transient currents, can prevent the phenomenon that the esd protection element voltage is too high, thereby can clamp down on the power bracket of esd protection element.In addition, ESD power clamping element 206a can increase the usefulness (efficiency) of the noise isolation (noise) of the first protective ring 226a and the second protective ring 228a.Because ESD power clamping element 206a is arranged in protective ring district 251, and integrate with the first protective ring 226a and the second protective ring 228a.Therefore, do not need additional space to put ESD power clamping element, can greatly save chip area.In addition, profile and Fig. 2 c of ESD power clamping element 206b are similar, wherein only the second doped region 222a are replaced into the second doped region 222b.
Fig. 3 a is the partial circuit layout 200c of the semiconductor device of other embodiment of the present invention, and wherein element and the identical part shown in 2a, the 2b figure then can not done repeated description at this with reference to the relevant narration of front.Shown in Fig. 3 a, ESD power clamping element 206c comprises one first outside protective ring 226a and one second inner protective ring 228b.Wherein the second protective ring 228b more comprises one the 4th doped region 218.The 4th doped region 218 is arranged in second wellblock 212, and is adjacent to the surface of substrate 201.The 4th doped region 218 can surround protected element 202 in fact, and parallel to each other with first doped region 220, the second doped region 222a and the 3rd doped region 216.In embodiments of the present invention, the 3rd doped region 216 and the 4th doped region 218 can (shallow trench isolation STI) separates by separator with shallow grooves.The conduction type of the 4th doped region 218 can be identical with the conduction type of substrate 201, and its dopant concentration for example can be greater than the dopant concentration of second wellblock 212, and in the embodiment of the invention, the 4th doped region 218 for example can be considered a p type heavy doping (p+) district 218.
Fig. 3 b shows partial circuit layout (circuitlayout) 200d of the semiconductor device of another embodiment of the present invention.Wherein the second doped region 222b of ESD power clamping element 206d is a continuous doped region.
Fig. 3 c shows the profile of ESD power clamping element 206c.Wherein first wellblock 214 and second wellblock 212 separate each other by separator with shallow grooves 230.Similarly, first doped region 220, the second doped region 222a, the 3rd doped region 216 and the 4th doped region 218 separate each other by separator with shallow grooves 230.In one embodiment of this invention, the 3rd doped region 216 and the 4th doped region 218 can be coupled to a high power end VDD simultaneously, and first doped region 220 and the second doped region 222a then can be coupled to a low power end VSS simultaneously.Shown in Fig. 3 c, first doped region 220 and the second doped region 222a can be coupled to earth terminal GND.In embodiments of the present invention, ESD power clamping element 206c can constitute the thyristor (silicon controlled rectifier is hereinafter to be referred as SCR) of a parasitism.When suffering ESD or during from the bombardment (zapping) of high power end VDD, the SCR of above-mentioned parasitism can be triggered, and can form the path from high power end VDD to earth terminal GND.Therefore, a large amount of electric holes can be flow in the p type substrate 201 via n type second wellblock 212 by p type heavy doping (p+) district 216, and n type heavy doping (n+) the district 222a via p type first wellblock 214 is directed at earth terminal GND with electric hole again.Hence one can see that, and ESD power clamping element 206c can conduct a large amount of ESD transient currents, can prevent the phenomenon that the esd protection element voltage is too high, thereby can clamp down on the power bracket of esd protection element.In addition, ESD power clamping element 206c can increase the usefulness (efficiency) of the noise isolation (noise) of the first protective ring 226a and the second protective ring 228b.Because ESD power clamping element 206c is arranged in protective ring district 251, and integrate with the first protective ring 226a and the second protective ring 228b.Therefore, do not need additional space to put ESD power clamping element, can greatly save chip area.In addition, profile and Fig. 3 c of ESD power clamping element 206d are similar, wherein only the second doped region 222a are replaced into the second doped region 222b.
The ESD power clamping element of the embodiment of the invention is arranged in the protective ring district, and integrates with protective ring, can increase the usefulness of protective ring noise isolation.In addition, do not need additional space to put ESD power clamping element, can greatly save chip area.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is worked as with being as the criterion that claims were defined.
Claims (11)
1. a semiconductor device is characterized in that, described semiconductor device comprises:
One substrate, described substrate have a protected element region, a protective ring district and an outer member district, and described substrate has one first conduction type;
One protected element, described protected element is arranged in described protected element region;
One static discharge power is clamped down on element; described static discharge power is clamped down on component position in described protective ring district; and surround described protected element; described static discharge power is clamped down on element and is comprised one first outside protective ring and one second inner protective ring, and wherein said first protective ring comprises:
One first wellblock, described first wellblock has described first conduction type; And
One first doped region and one second doped region, described first doped region and second doped region are arranged in described first wellblock, and be adjacent to the surface of described substrate, wherein said first doped region and described second doped region have described first conduction type and one second conduction type respectively;
Described second protective ring comprises:
One second wellblock, described second wellblock has described second conduction type; And
One the 3rd doped region, described the 3rd doped region is arranged in described second wellblock, and is adjacent to the surface of described substrate, and wherein said the 3rd doped region has described second conduction type; And
One I/O element is arranged in described outer member district, and is coupled to described static discharge power and clamps down on element, and wherein said first wellblock and described second wellblock separate each other.
2. semiconductor device as claimed in claim 1, it is characterized in that described second protective ring more comprises one the 4th doped region, be arranged in described second wellblock, and be adjacent to the surface of described substrate, wherein said the 4th doped region has described first conduction type.
3. semiconductor device as claimed in claim 2 is characterized in that, described the 3rd doped region and described the 4th doped region all are coupled to a power end.
4. semiconductor device as claimed in claim 2 is characterized in that, described the 3rd doped region and described the 4th doped region surround described protected element respectively, and parallel to each other.
5. semiconductor device as claimed in claim 1 is characterized in that, described semiconductor device more comprises:
One electric static discharge protector is coupled to described I/O element and described static discharge power is clamped down on element.
6. semiconductor device as claimed in claim 1 is characterized in that, described first conduction type is the n type, and described second conduction type is the p type.
7. semiconductor device as claimed in claim 1 is characterized in that, described first conduction type is the p type, and described second conduction type is the n type.
8. semiconductor device as claimed in claim 1 is characterized in that, described first doped region and described second doped region surround described protected element respectively, and parallel to each other.
9. semiconductor device as claimed in claim 1 is characterized in that, described first doped region and described second doped region all are coupled to earth terminal.
10. semiconductor device as claimed in claim 1 is characterized in that, described second doped region, described first wellblock, described substrate, described second wellblock and described the 3rd doped region constitute a two-carrier transistor.
11. semiconductor device as claimed in claim 1 is characterized in that, described static discharge power is clamped down on element and is coupled to described protected element and described I/O element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710160825XA CN101465349B (en) | 2007-12-18 | 2007-12-18 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710160825XA CN101465349B (en) | 2007-12-18 | 2007-12-18 | Semiconductor device |
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| Publication Number | Publication Date |
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| CN101465349A CN101465349A (en) | 2009-06-24 |
| CN101465349B true CN101465349B (en) | 2010-06-02 |
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| CN200710160825XA Active CN101465349B (en) | 2007-12-18 | 2007-12-18 | Semiconductor device |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102035194B (en) * | 2009-09-27 | 2013-10-16 | 上海宏力半导体制造有限公司 | Electrostatic discharge protection system |
| CN114446936A (en) * | 2020-10-30 | 2022-05-06 | 中芯集成电路（宁波）有限公司上海分公司 | Semiconductor substrate and manufacturing method thereof, and semiconductor device structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354516A (en) * | 2000-11-16 | 2002-06-19 | 世界先进积体电路股份有限公司 | Static discharge protecting element and related circuit |
| CN1471166A (en) * | 2002-06-14 | 2004-01-28 | ������������ʽ���� | Electrostatic discharge protection element |
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- 2007-12-18 CN CN200710160825XA patent/CN101465349B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354516A (en) * | 2000-11-16 | 2002-06-19 | 世界先进积体电路股份有限公司 | Static discharge protecting element and related circuit |
| CN1471166A (en) * | 2002-06-14 | 2004-01-28 | ������������ʽ���� | Electrostatic discharge protection element |
Non-Patent Citations (1)
| Title |
|---|
| US 5,889,309 A,1999.03.30,全文. |
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| CN101465349A (en) | 2009-06-24 |
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