CN101461721A - Bus-mastering Doppler ultrasound image-forming system - Google Patents
Bus-mastering Doppler ultrasound image-forming system Download PDFInfo
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- CN101461721A CN101461721A CNA200810241932XA CN200810241932A CN101461721A CN 101461721 A CN101461721 A CN 101461721A CN A200810241932X A CNA200810241932X A CN A200810241932XA CN 200810241932 A CN200810241932 A CN 200810241932A CN 101461721 A CN101461721 A CN 101461721A
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Abstract
The invention discloses a bus-control Doppler ultrasonic imaging system, which comprises an ultrasonic probe module, a master control module, a transmitting module, a receiving module, a digital signal processing module and a display module. The system is characterized in that the master control module is connected with the transmitting module, the receiving module and the digital signal processing module respectively through an address bus, a data bus and a control bus; the master control module is used for selecting other modules communicating therewith through the control bus, controlling the data transmission direction, transmitting other control signals, transmitting the source address or the destination address of data through the address bus, and transmitting data through the data bus; and the transmitting module, the receiving module and the digital signal processing module are used for transmitting data through the data bus.
Description
Technical field
The present invention relates to the supersonic imaging apparatus technical field, be specifically related to a kind of bus-mastering Doppler ultrasound image-forming system.
Background technology
Doppler ultrasonic image-forming system is used for detecting the speed and the direction of blood flow, and the form of testing result with coloured image shown, is mainly used in inspection and diagnosis to cardiovascular, woman's product, abdomen organ etc.
As shown in Figure 1, Doppler ultrasonic image-forming system comprises ultrasound probe module, main control module, transmitter module, receiver module, digital signal processing module and display module.The main control module sends the emission ultrasound wave and instructs to transmitter module, transmitter module control ultrasound probe module is launched ultrasound wave in human or animal body, receiver module receives the ultrasonic echo that the human or animal body internal reflection returns and does to handle early stage (as analog-digital conversion, digital filtering, wave beam synthetic etc.), then, by the main control module signal being transferred to digital signal processing module handles to received signal, at last, transferring to display module by the main control module again shows with the form of coloured image.
Main control module, transmitter module, receiver module and digital signal processing module are that the core of Doppler ultrasonic image-forming system is formed module.The design of the communication mode between these four modules has directly determined the quality and the real-time performance of Doppler ultrasonic image-forming system image.
Controller on the Doppler ultrasonic image-forming system disparate modules of prior art is controlled the memory device on the corresponding module respectively independently, that is to say, memory device on the controller control transmitter module on the transmitter module, memory device on the controller control receiver module on the receiver module, the memory device on the DSP CONTROL digital signal processing module on the digital signal processing module.She Ji shortcoming is like this, the difficult control of the synchronicity that data between the disparate modules are transmitted, and the frequency of system's operation is lower, thereby has reduced the real-time of system's operation, and real-time is one of of paramount importance performance indications of Doppler ultrasonic image-forming system.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of bus-mastering Doppler ultrasound image-forming system, overcome synchronicity that the Doppler ultrasonic image-forming system data of prior art transmit be difficult to control, can not assurance system operation real-time defective.
The present invention solves the problems of the technologies described above the technical scheme that is adopted to be:
A kind of bus-mastering Doppler ultrasound image-forming system, comprise the ultrasound probe module, the main control module, transmitter module, receiver module, digital signal processing module and display module, described main control module respectively with described transmitter module, described receiver module, described digital signal processing module passes through address bus, data/address bus is connected with control bus, described main control module is used for selecting other module of communication with it by described control bus, the control data transmission direction, and send other control signal, by described address bus transmission data source address or destination address, by described data/address bus transmission data, described transmitter module, described receiver module, described digital signal processing module is used for by described data/address bus transmission data.
Described bus-mastering Doppler ultrasound image-forming system, wherein said main control module comprises the master controller and first buffer, described master controller is connected by the enable signal line with first buffer, described transmitter module comprises the transmitting terminal memorizer, described receiver module comprises the receiving terminal memorizer, described digital signal processing module comprises the Digital Signal Processing memorizer, and first buffer is connected with described transmitting terminal memorizer, described receiving terminal memorizer and described Digital Signal Processing memorizer respectively with described address bus by described control bus.
Described bus-mastering Doppler ultrasound image-forming system, wherein said main control module also comprises second buffer, described master controller is connected by the enable signal line with second buffer, and second buffer is connected with described transmitting terminal memorizer, described receiving terminal memorizer and described Digital Signal Processing memorizer respectively by described data/address bus.
Described bus-mastering Doppler ultrasound image-forming system, wherein said main control module also comprises the 3rd buffer, described master controller is connected by the enable signal line with the 3rd buffer, described transmitter module comprises the transmitting terminal controller, described receiver module comprises the receiving terminal controller, described digital signal processing module comprises digital signal processor, and the 3rd buffer is connected with described digital signal processor with described transmitting terminal controller, described receiving terminal controller respectively with described control bus by described address bus, described data/address bus.
Described bus-mastering Doppler ultrasound image-forming system, wherein said master controller is by the described transmitting terminal memorizer of the first enable signal line group selection in the described control bus, described receiving terminal memorizer or described Digital Signal Processing memorizer.
Described bus-mastering Doppler ultrasound image-forming system, wherein said master controller is by the described transmitting terminal controller of the second enable signal line group selection in the described control bus, described receiving terminal controller or described digital signal processor.
Described bus-mastering Doppler ultrasound image-forming system, wherein said master controller is made as chip XC5VLX50T.
Described bus-mastering Doppler ultrasound image-forming system, wherein said digital signal processor is made as chip TMS320C6454.
Described bus-mastering Doppler ultrasound image-forming system, wherein said transmitting terminal memorizer, described receiving terminal memorizer and described Digital Signal Processing memorizer are made as chip id T71V416YS.
Described bus-mastering Doppler ultrasound image-forming system, wherein said transmitting terminal controller, described receiving terminal controller and described digital signal processor are made as chip XC3S1600e.
Beneficial effect of the present invention: bus-mastering Doppler ultrasound image-forming system of the present invention is controlled function with major part and is concentrated on the main control module, and to the operation of address bus, data/address bus all via the main control module, therefore the signal of whole system is easy to control synchronously, reduce the complexity of whole system greatly, also greatly reduced the software kit development difficulty.
Description of drawings
The present invention includes following accompanying drawing:
Fig. 1 is a prior art Doppler ultrasonic image-forming system sketch map;
The sketch map that Fig. 2 is connected with address bus by control bus for each module of the present invention;
The sketch map that Fig. 3 connects by data/address bus for each module of the present invention;
The sketch map that Fig. 4 is connected with transmitting terminal controller, receiving terminal controller and Digital Signal Processing controller by bus for master controller of the present invention.
The specific embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
As Fig. 1, Fig. 2, Fig. 3 and shown in Figure 4, bus-mastering Doppler ultrasound image-forming system of the present invention comprises the ultrasound probe module, the main control module, transmitter module, receiver module, digital signal processing module and display module, the main control module respectively with transmitter module, receiver module, digital signal processing module passes through address bus, data/address bus is connected with control bus, the main control module is selected other module of communication with it by control bus, the control data transmission direction, and send other control signal, by address bus transmission data source address or destination address, by data/address bus transmission data, transmitter module, receiver module, digital signal processing module transmits data by data/address bus.The main control module comprises master controller and first buffer (buffer A), master controller is connected by the enable signal line with first buffer, transmitter module comprises the transmitting terminal memorizer, receiver module comprises the receiving terminal memorizer, digital signal processing module comprises the Digital Signal Processing memorizer, and first buffer is connected with transmitting terminal memorizer, receiving terminal memorizer and Digital Signal Processing memorizer respectively with address bus by control bus.The main control module also comprises second buffer, and master controller is connected by the enable signal line with second buffer (bidirectional buffer), and second buffer is connected with transmitting terminal memorizer, receiving terminal memorizer and Digital Signal Processing memorizer respectively by data/address bus.The main control module also comprises the 3rd buffer (buffer B), master controller is connected by the enable signal line with the 3rd buffer, transmitter module comprises the transmitting terminal controller, receiver module comprises the receiving terminal controller, digital signal processing module comprises digital signal processor, and the 3rd buffer is connected with digital signal processor with transmitting terminal controller, receiving terminal controller respectively with control bus by address bus, data/address bus.Master controller is by the first enable signal line group selection transmitting terminal memorizer, receiving terminal memorizer or Digital Signal Processing memorizer in the described control bus.Master controller is by the second enable signal line group selection transmitting terminal controller, receiving terminal controller or digital signal processor in the control bus.
As shown in Figure 2, master controller enables one-way damper A by one-way damper A enable signal line 1, and one-way damper A read line 2 is set to write state, at synchronization, by the transmitting terminal SRAM enable signal in the enable transmission end SRAM control bus, unique single line line in the Digital Signal Processing SRAM enable signal in receiving terminal SRAM enable signal in the receiving terminal SRAM control bus or the Digital Signal Processing SRAM control bus, choose one of them device among above-mentioned three SRAM, master controller just can be selected transmitting terminal SRAM data source address or destination address and control transmitting terminal SRAM by transmitting terminal SRAM address bus 3 and transmitting terminal SRAM control bus 6 like this; Master controller just can and be controlled receiving terminal SRAM by receiving terminal SRAM address bus 4 and receiving terminal SRAM control bus 7 selective reception end SRAM data source address or destination address; Master controller just can be selected Digital Signal Processing SRAM data source address or destination address and control figure signal processing SRAM by Digital Signal Processing SRAM address bus 5 and Digital Signal Processing SRAM control bus 8.
As shown in Figure 3, the main control module enables bidirectional buffer by bidirectional buffer enable signal line 9, and bidirectional buffer read line 10 is set to write state, under the synergism of transmitting terminal SRAM address bus 3 and transmitting terminal SRAM control bus 6, transmitting terminal SRAM data/address bus 11 receives the data of Autonomous Control module; Under the synergism of receiving terminal SRAM address bus 4 and receiving terminal SRAM control bus 7, transmitting terminal SRAM data/address bus 12 receives the data of Autonomous Control module; Under the synergism of Digital Signal Processing SRAM address bus 5 and Digital Signal Processing SRAM control bus 8, Digital Signal Processing SRAM data/address bus 13 receives the data of Autonomous Control module.Then, the main control module enables bidirectional buffer by bidirectional buffer enable signal line 9, and bidirectional buffer read line 10 is set to read states, under the synergism of transmitting terminal SRAM address bus 3 and transmitting terminal SRAM control bus 6, transmitting terminal SRAM data/address bus 11 sends data to the main control module; Under the synergism of receiving terminal SRAM address bus 4 and receiving terminal SRAM control bus 7, receiving terminal SRAM data/address bus 12 sends data to the main control module; Under the synergism of Digital Signal Processing SRAM address bus 5 and Digital Signal Processing SRAM control bus 8, Digital Signal Processing SRAM data/address bus 13 sends data to the main control module.
As shown in Figure 4, the main control module enables one-way damper B by one-way damper B enable signal line 14, and one-way damper B read line 15 is set to write state, at synchronization, by the transmitting terminal controller enable signal in the enable transmission side controller control bus, receiving terminal controller enable signal in the receiving terminal controller control bus or the unique single line line in the Digital Signal Processing enable signal in the DSP CONTROL bus, choose in above-mentioned three devices, master controller just can pass through transmitting terminal controller address bus 16 like this, transmitting terminal controller control bus 19 and transmitting terminal controller data bus 22 are selected the destination address of transmitting terminal controller data to be written and are controlled the transmitting terminal controller, and data are sent to the transmitting terminal controller from the main control module; Master controller just can be by receiving terminal controller address bus 17, receiving terminal controller control bus 20 and receiving terminal controller data bus 23 selective reception side controllers data to be written destination address and control the receiving terminal controller, data are sent to the receiving terminal controller from the main control module; Master controller just can pass through destination address and the control figure signal processor that digital signal processor address bus 18, DSP CONTROL bus 21 and digital signal processor data/address bus 24 are selected digital signal processor data to be written, and data are sent to digital signal processor from the main control module.
Use the chip XC5VLX50T of Xilinx company, digital signal processor to use TI (the Texas Instruments of company with master controller below, Inc) chip TMS320C6454, transmitting terminal memorizer, receiving terminal memorizer and Digital Signal Processing memorizer use IDT (the Integrated Device Technolodgy of company, Inc) chip id T71V416YS, transmitting terminal controller, receiving terminal controller and digital signal processor use the chip XC3S1600e of Xilinx company as example signal controlling process of the present invention to be described:
The memory space of transmitting terminal SRAM is 256K * 32-Bit, therefore the address-bus width of it and main control module is 18 (are designated as TxSRAMADDRESSBUS[17:0]), data-bus width is 32 (are designated as TxSRAMDATABUS[31:0]), in addition, the control bus width of transmitting terminal SRAM and main control module be 4 (be designated as TxSRAMCONTROLBUS[3:0], its corresponding 4 control signals independently: (1) transmitting terminal SRAM read/write enable signal (be designated as TxSRAMWE or TxSRAMCONTROLBUS[0]); (2) transmitting terminal SRAM output enable signal (be designated as TxSRAMOE or TxSRAMCONTROLBUS[1]); (3) transmitting terminal SRAM data direction is selected signal (be designated as TxSRAMDIR or TxSRAMCONTROLBUS[2]); (4) transmitting terminal SRAM enable signal (be designated as TxSRAMEn or TxSRAMCONTROLBUS[3].), address bus TxSRAMADDRESSBUS[17:0 wherein] transmitting terminal SRAM address bus 3 in the corresponding diagram 2, control bus TxSRAMCONTROLBUS[3:0] transmitting terminal SRAM control bus 6 in the corresponding diagram 2, data/address bus TxSRAMDATABUS[31:0] transmitting terminal SRAM data/address bus 11 in the corresponding diagram 3.
The memory space of receiving terminal SRAM is 256K * 32-Bit, therefore the address-bus width of it and main control module is 18 (are designated as RxSRAMADDRESSBUS[17:0]), data-bus width is 32 (are designated as RxSRAMDATABUS[31:0]), in addition, the control bus width of receiving terminal SRAM and main control module be 4 (be designated as RxSRAMCONTROLBUS[3:0], its corresponding 4 control signals independently: (1) receiving terminal SRAM read/write enable signal (be designated as RxSRAMWE or RxSRAMCONTROLBUS[0]); (2) receiving terminal SRAM output enable signal (be designated as RxSRAMOE or RxSRAMCONTROLBUS[1]); (3) receiving terminal SRAM data direction is selected signal (be designated as RxSRAMDIR or RxSRAMCONTROLBUS[2]); (4) receiving terminal SRAM enable signal (be designated as RxSRAMEn or RxSRAMCONTROLBUS[3].), address bus RxSRAMADDRESSBUS[17:0 wherein] receiving terminal SRAM address bus 4 in the corresponding diagram 2, control bus RxSRAMCONTROLBUS[3:0] receiving terminal SRAM control bus 7 in the corresponding diagram 2, data/address bus RxSRAMDATABUS[31:0] transmitting terminal SRAM data/address bus 12 in the corresponding diagram 3.
The memory space of Digital Signal Processing SRAM is 256K * 32-Bit, therefore the address-bus width of it and main control module is 18 (are designated as DSPSRAMADDRESSBUS[17:0]), data-bus width is 32 (are designated as DSPSRAMDATABUS[31:0]), in addition, the control bus width of Digital Signal Processing SRAM and main control module be 4 (be designated as DSPSRAMCONTROLBUS[3:0], its corresponding 4 control signals independently: (1) Digital Signal Processing SRAM read/write enable signal (be designated as DSPSRAMWE or DSPSRAMCONTROLBUS[0]); (2) Digital Signal Processing SRAM output enable signal (be designated as DSPSRAMOE or DSPSRAMCONTROLBUS[1]); (3) Digital Signal Processing SRAM data direction is selected signal (be designated as DSPSRAMDIR or DSPSRAMCONTROLBUS[2]); (4) Digital Signal Processing SRAM enable signal (be designated as DSPSRAMEn or DSPSRAMCONTROLBUS[3].), address bus DSPSRAMADDRESSBUS[17:0 wherein] Digital Signal Processing SRAM address bus 5 in the corresponding diagram 2, control bus DSPSRAMCONTROLBUS[3:0] Digital Signal Processing SRAM control bus 8 in the corresponding diagram 2, data/address bus DSPSRAMDATABUS[31:0] Digital Signal Processing SRAM data/address bus 13 in the corresponding diagram 3.
The data-bus width of transmitting terminal controller and main control module is 32 (are designated as TxCONTROLLERDATABUS[31:0]), there are 256 controlled depositors transmitting terminal controller inside, therefore its address-bus width is 8 (are designated as TxCONTROLLERADDRESSBUS[7:0]), the control bus width be 3 (be designated as TxCONTROLLERCONTROLBUS[2:0], its corresponding 3 control signals independently: (1) transmitting terminal controller read/write enable signal (be designated as TxCONTROLLERWE or TxCONTROLLERCONTROLBUS[0]); (2) transmitting terminal controller data direction selection signal (be designated as TxCONTROLLERDIR or TxCONTROLLERCONTROLBUS[1]; (3) transmitting terminal controller enable signal (be designated as TxCONTROLLEREn or TxCONTROLLERCONTROLBUS[2].), address bus TxCONTROLLERADDRESSBUS[7:0 wherein] transmitting terminal controller address bus 16 in the corresponding diagram 4, control bus TxCONTROLLERCONTROLBUS[2:0] transmitting terminal controller control bus 19 in the corresponding diagram 4, data/address bus TxCONTROLLERDATABUS[31:0] transmitting terminal controller data bus 22 in the corresponding diagram 4.
The data-bus width of receiving terminal controller and main control module is 32 (are designated as RxCONTROLLERDATABUS[31:0]), there are 256 controlled depositors receiving terminal controller inside, therefore its address-bus width is 8 (are designated as RxCONTROLLERADDRESSBUS[7:0]), the control bus width be 3 (be designated as RxCONTROLLERCONTROLBUS[2:0], its corresponding 3 control signals independently: (1) receiving terminal controller read/write enable signal (be designated as RxCONTROLLERWE or RxCONTROLLERCONTROLBUS[0]); (2) receiving terminal controller data direction selection signal (be designated as RxCONTROLLERDIR or RxCONTROLLERCONTROLBUS[1]); (3) receiving terminal controller enable signal (be designated as RxCONTROLLEREn or RxCONTROLLERCONTROLBUS[2].), address bus RxCONTROLLERADDRESSBUS[7:0 wherein] receiving terminal controller address bus 17 in the corresponding diagram 4, control bus RxCONTROLLERCONTROLBUS[2:0] receiving terminal controller control bus 20 in the corresponding diagram 4, data/address bus RxCONTROLLERDATABUS[31:0] receiving terminal controller data bus 23 in the corresponding diagram 4.
The data-bus width of digital signal processor and main control module is 32 (are designated as DSPDATABUS[31:0]), there are 1024 controlled depositors digital signal processor inside, therefore its address-bus width is 10 (are designated as DSPADDRESSBUS[9:0]), the control bus width be 3 (be designated as DSPCONTROLBUS[2:0], its corresponding 3 control signals independently: (1) digital signal processor read/write enable signal (be designated as DSPWE or DSPCONTROLBUS[0]); (2) the digital signal processor data direction is selected signal (be designated as DSPDIR or DSPCONTROLBUS[1]); (3) the digital signal processor enable signal (be designated as DSPEn or DSPCONTROLBUS[2].), address bus DSPADDRESSBUS[9:0 wherein] digital signal processor address bus 18 in the corresponding diagram 4, control bus DSPCONTROLBUS[2:0] DSP CONTROL bus 21 in the corresponding diagram 4, data/address bus DSPDATABUS[31:0] digital signal processor data/address bus 24 in the corresponding diagram 4.
One-way damper A enable signal line 1 is designated as BufAEn, and one-way damper A read line 2 is designated as BufAWE, and bidirectional buffer enable signal line 12 is designated as BiDirBufEn, and bidirectional buffer read line 13 is designated as BiDirBufWE; One-way damper B enable signal line 17 is designated as BufBEn, and one-way damper B read line 18 is designated as BufBWE.
At first, BiDirBufEn is changed to high level enables bidirectional buffer, BiDirBufWE is set to high level, and bidirectional buffer is placed the state of writing.Master controller is changed to high level with BufAEn and enables one-way damper A, and BufAWE is changed to high level makes one-way damper place the state of writing, TxSRAMEn is changed to high level enable transmission end SRAM, like this, master controller just can pass through TxSRAMADDRESSBUS[17:0] select the destination address that transmitting terminal SRAM data write and pass through TxSRAMCONTROLBUS[3:0] control transmitting terminal SRAM, wherein TxSRAMWE is changed to high level, SRAM places the state of writing with transmitting terminal; TxSRAMOE is changed to low level, closes transmitting terminal SRAM data output function; TxSRAMDIR is changed to high level, thus data/address bus TxSRAMDATABUS[31:0] on data flow to transmitting terminal SRAM from the main control module.In like manner, master controller is changed to high level with BufAEn and enables one-way damper A, and BufAWE is changed to high level makes one-way damper place the state of writing, RxSRAMEn is changed to high level enables receiving terminal SRAM, like this, master controller just can pass through RxSRAMADDRESSBUS[17:0] destination address that writes of selective reception end SRAM data and pass through RxSRAMCONTROLBUS[3:0] control receiving terminal SRAM, wherein RxSRAMWE is changed to high level, SRAM places the state of writing with receiving terminal; RxSRAMOE is changed to low level, closes receiving terminal SRAM data output function; RxSRAMDIR is changed to high level, thus data/address bus RxSRAMDATABUS[31:0] on data flow to receiving terminal SRAM from the main control module.Master controller is changed to high level with BufAEn and enables one-way damper A, and BufAWE is changed to high level makes one-way damper place the state of writing, DSPSRAMEn is changed to high level enable digital signals treatment S RAM, like this, master controller just can pass through DSPSRAMADDRESSBUS[17:0] select the destination address that Digital Signal Processing SRAM data write and pass through DSPSRAMCONTROLBUS[3:0] control figure signal processing SRAM, wherein DSPSRAMWE is changed to high level, SRAM places the state of writing with Digital Signal Processing; DSPSRAMOE is changed to low level, closes Digital Signal Processing SRAM data output function; DSPSRAMDIR is changed to high level, thus data/address bus DSPSRAMDATABUS[31:0] on data flow to Digital Signal Processing SRAM from the main control module.Notice that at synchronization, it is high level that a signal can only be arranged among TxSRAMEn, RxSRAMEn and the DSPSRAMEn because synchronization can only enable transmission end SRAM, receiving terminal SRAM or Digital Signal Processing SRAM in a unique device.
Then, BiDirBufWE is set to low level, and bidirectional buffer is placed read states.Master controller is changed to low level with BufAWE makes one-way damper place read states, TxSRAMEn is changed to high level enable transmission end SRAM, like this, master controller just can pass through TxSRAMADDRESSBUS[17:0] select the source address of transmitting terminal SRAM data read and pass through TxSRAMCONTROLBUS[3:0] control transmitting terminal SRAM, wherein TxSRAMWE is changed to low level, SRAM places read states with transmitting terminal; TxSRAMOE is changed to high level, opens transmitting terminal SRAM data output function; TxSRAMDIR is changed to low level, thus data/address bus TxSRAMDATABUS[31:0] on data flow to the main control module from transmitting terminal SRAM.In like manner, master controller is changed to low level with BufAWE makes one-way damper place read states, RxSRAMEn is changed to high level enables receiving terminal SRAM, like this, master controller just can pass through RxSRAMADDRESSBUS[17:0] source address of selective reception end SRAM data read and pass through RxSRAMCONTROLBUS[3:0] control receiving terminal SRAM, wherein RxSRAMWE is changed to low level, SRAM places read states with receiving terminal; RxSRAMOE is changed to high level, opens receiving terminal SRAM data output function; RxSRAMDIR is changed to low level, thus data/address bus RxSRAMDATABUS[31:0] on data flow to the main control module from receiving terminal SRAM.Master controller is changed to low level with BufAWE makes one-way damper place read states, DSPSRAMEn is changed to high level enable digital signals treatment S RAM, like this, master controller just can pass through DSPSRAMADDRESSBUS[17:0] select the source address of Digital Signal Processing SRAM data read and pass through DSPSRAMCONTROLBUS[3:0] control figure signal processing SRAM, wherein DSPSRAMWE is changed to low level, SRAM places read states with Digital Signal Processing; DSPSRAMOE is changed to high level, opens Digital Signal Processing SRAM data output function; DSPSRAMDIR is changed to low level, thus data/address bus DSPSRAMDATABUS[31:0] on data flow to the main control module from Digital Signal Processing SRAM.
At last, master controller BufBEn is set to high level and enables one-way damper B, and BufBWE is set to high level one-way damper B is changed to the state of writing.Master controller is changed to high level enable transmission side controller with TxCONTROLLEREn, like this, master controller just can pass through TxCONTROLLERADDRESSBUS[7:0] select the destination register that the transmitting terminal controller data writes and pass through TxCONTROLLERCONTROLBUS[2:0] control transmitting terminal controller, wherein TxCONTROLLERWE is changed to high level, the transmitting terminal controller is placed the state of writing; TxCONTROLLERDIR is changed to high level, thus data/address bus TxCONTROLLERDATABUS[31:0] on data flow to the transmitting terminal controller from the main control module.In like manner, master controller BufBEn is set to high level and enables one-way damper B, and BufBWE is set to high level one-way damper B is changed to the state of writing.Master controller is changed to high level with RxCONTROLLEREn and enables the receiving terminal controller, like this, master controller just can pass through RxCONTROLLERADDRESSBUS[7:0] destination register that writes of selective reception side controller data and pass through RxCONTROLLERCONTROLBUS[2:0] control transmitting terminal controller, wherein RxCONTROLLERWE is changed to high level, the transmitting terminal controller is placed the state of writing; RxCONTROLLERDIR is changed to high level, thus data/address bus RxCONTROLLERDATABUS[31:0] on data flow to the receiving terminal controller from the main control module.Master controller BufBEn is set to high level and enables one-way damper B, and BufBWE is set to high level one-way damper B is changed to the state of writing.Master controller is changed to high level enable digital signals processor with DSPEn, like this, master controller just can pass through DSPADDRESSBUS[9:0] select the destination register that the digital signal processor data write and pass through DSPCONTROLBUS[2:0] control transmitting terminal controller, wherein DSPWE is changed to high level, digital signal processor is placed the state of writing; DSPDIR is changed to high level, thus data/address bus DSPDATABUS[31:0] on data flow to digital signal processor from the main control module.Note, at synchronization, it is high level that a signal can only be arranged among TxCONTROLLEREn, RxCONTROLLEREn and the DSPEn because synchronization can only the enable transmission side controller, the unique device in receiving terminal controller or the digital signal processor.
Those skilled in the art do not break away from essence of the present invention and spirit, can there be the various deformation scheme to realize the present invention, the above only is the preferable feasible embodiment of the present invention, be not so limit to interest field of the present invention, the equivalent structure that all utilizations description of the present invention and accompanying drawing content are done changes, and all is contained within the interest field of the present invention.
Claims (10)
1, a kind of bus-mastering Doppler ultrasound image-forming system, comprise the ultrasound probe module, the main control module, transmitter module, receiver module, digital signal processing module and display module, it is characterized in that: described main control module respectively with described transmitter module, described receiver module, described digital signal processing module passes through address bus, data/address bus is connected with control bus, described main control module is used for selecting other module of communication with it by described control bus, the control data transmission direction, and send other control signal, by described address bus transmission data source address or destination address, by described data/address bus transmission data, described transmitter module, described receiver module, described digital signal processing module is used for by described data/address bus transmission data.
2, bus-mastering Doppler ultrasound image-forming system according to claim 1, it is characterized in that: described main control module comprises the master controller and first buffer, described master controller is connected by the enable signal line with first buffer, described transmitter module comprises the transmitting terminal memorizer, described receiver module comprises the receiving terminal memorizer, described digital signal processing module comprises the Digital Signal Processing memorizer, first buffer by described control bus and described address bus respectively with described transmitting terminal memorizer, described receiving terminal memorizer is connected with described Digital Signal Processing memorizer.
3, bus-mastering Doppler ultrasound image-forming system according to claim 2, it is characterized in that: described main control module also comprises second buffer, described master controller is connected by the enable signal line with second buffer, and second buffer is connected with described transmitting terminal memorizer, described receiving terminal memorizer and described Digital Signal Processing memorizer respectively by described data/address bus.
4, bus-mastering Doppler ultrasound image-forming system according to claim 3, it is characterized in that: described main control module also comprises the 3rd buffer, described master controller is connected by the enable signal line with the 3rd buffer, described transmitter module comprises the transmitting terminal controller, described receiver module comprises the receiving terminal controller, described digital signal processing module comprises digital signal processor, and the 3rd buffer is by described address bus, described data/address bus and described control bus respectively with described transmitting terminal controller, described receiving terminal controller is connected with described digital signal processor.
5, bus-mastering Doppler ultrasound image-forming system according to claim 4 is characterized in that: described master controller is by the described transmitting terminal memorizer of the first enable signal line group selection in the described control bus, described receiving terminal memorizer or described Digital Signal Processing memorizer.
6, bus-mastering Doppler ultrasound image-forming system according to claim 5 is characterized in that: described master controller is by the described transmitting terminal controller of the second enable signal line group selection in the described control bus, described receiving terminal controller or described digital signal processor.
7, bus-mastering Doppler ultrasound image-forming system according to claim 6 is characterized in that: described master controller is made as chip XC5VLX50T.
8, bus-mastering Doppler ultrasound image-forming system according to claim 7 is characterized in that: described digital signal processor is made as chip TMS320C6454.
9, bus-mastering Doppler ultrasound image-forming system according to claim 8 is characterized in that: described transmitting terminal memorizer, described receiving terminal memorizer and described Digital Signal Processing memorizer are made as chip id T71V416YS.
10, bus-mastering Doppler ultrasound image-forming system according to claim 9 is characterized in that: described transmitting terminal controller, described receiving terminal controller and described digital signal processor are made as chip XC3S1600e.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103371854A (en) * | 2012-04-13 | 2013-10-30 | 深圳市蓝韵实业有限公司 | Four-dimensional ultrasonic probe drive method and device |
| CN106200484A (en) * | 2016-08-05 | 2016-12-07 | 沈阳东软医疗系统有限公司 | Electric machine control system and method |
| CN115312094A (en) * | 2022-07-04 | 2022-11-08 | 深圳市紫光同创电子有限公司 | SRAM control system and method, FPGA chip and electronic equipment |
-
2008
- 2008-12-30 CN CNA200810241932XA patent/CN101461721A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103371854A (en) * | 2012-04-13 | 2013-10-30 | 深圳市蓝韵实业有限公司 | Four-dimensional ultrasonic probe drive method and device |
| CN103371854B (en) * | 2012-04-13 | 2015-07-22 | 深圳市蓝韵实业有限公司 | Four-dimensional ultrasonic probe drive method and device |
| CN106200484A (en) * | 2016-08-05 | 2016-12-07 | 沈阳东软医疗系统有限公司 | Electric machine control system and method |
| CN106200484B (en) * | 2016-08-05 | 2019-08-13 | 东软医疗系统股份有限公司 | Electric machine control system and method |
| CN115312094A (en) * | 2022-07-04 | 2022-11-08 | 深圳市紫光同创电子有限公司 | SRAM control system and method, FPGA chip and electronic equipment |
| WO2024007914A1 (en) * | 2022-07-04 | 2024-01-11 | 深圳市紫光同创电子有限公司 | Sram control system, method, fpga chip, and electronic equipment |
| CN115312094B (en) * | 2022-07-04 | 2024-04-09 | 深圳市紫光同创电子有限公司 | SRAM control system, method, FPGA chip and electronic equipment |
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