CN101458720A - Method for reducing proximity effect of SRAM trap - Google Patents
Method for reducing proximity effect of SRAM trap Download PDFInfo
- Publication number
- CN101458720A CN101458720A CNA2007100944840A CN200710094484A CN101458720A CN 101458720 A CN101458720 A CN 101458720A CN A2007100944840 A CNA2007100944840 A CN A2007100944840A CN 200710094484 A CN200710094484 A CN 200710094484A CN 101458720 A CN101458720 A CN 101458720A
- Authority
- CN
- China
- Prior art keywords
- trap
- sram
- border
- proximity effect
- electrical parameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A method for reducing SRAM well proximity effect, at least three SRAM initial layouts are provided, each SRAM initial layout has neighboring N well and P well which have abutting boundaries; two boundaries in the same well of single SRAM initial layout are moved to reverse direction to obtain a corresponding SRAM updating layout; the each SRAM updating layout has different N well width; at least three electric parameters of SRAM device formed by SRAM updating layout are measured to obtain the electric parameter variation trend; if the measured electric parameter variation trend is same as the variation trend of the corresponding target value, the measured electric parameter and the corresponding target value are compared; if the difference value of the measured electric parameter and the corresponding target value is in a tolerated range, the SRAM updating layout corresponding to the electric parameter can be adopted. The method for reducing the SRAM well proximity effect is visual and has high efficiency.
Description
Technical field
The present invention relates to reduce the method for SRAM trap proximity effect.
Background technology
At the CMOS that is integrated on the same chip, for example among NMOS and the PMOS, on silicon substrate, need at least one trap.For example, when adopting P type substrate, NMOS can be manufactured on the substrate, and PMOS must be manufactured on the n trap in the substrate.As selection, when adopting n type substrate, PMOS can be manufactured on the substrate, and NMOS must be manufactured on the p trap in the substrate.In addition, for fear of with latch relevant problem, usually adopt two trap modes.Regardless of substrate type, two trap modes are included in and form NMOS on the p trap and form PMOS on the n trap.And at present generally all be that the method for utilizing ion to inject forms described trap, for example the patent No. is that the Chinese patent of ZL97103016.2 discloses a kind of method that forms the trap of semiconductor devices, the method for wherein just having used ion to inject.
In the technology that forms two traps at present, find to exist trap proximity effect (WPE, Well ProximityEffect).Described trap proximity effect is meant utilizing ion inject to form the process of trap, injects ion and can enter into the edge of trap along the generation scattering of photoresist edge, and be uneven thereby cause doping profile in the edge of trap crossing on the width of trap.And this inhomogeneous meeting makes each Devices Characteristics parameter difference in the trap, the device that for example approaches the edge of trap have with away from the different threshold voltage of the device at trap edge.And along with the CMOS technology deeply expands to sub-micron and enters into nanometer, device diminishes gradually, and the trap proximity effect is also increasing to the influence of Devices Characteristics parameter.Particularly for storer with array structure, static memory (SRAM) for example, because the characteristics of array structure, N trap and P trap all are spaced, inject when the trap proximity effect occurring when carrying out ion with the process that forms N trap or P trap, the device at all N traps or P trap edge and the difference that all will produce component characteristic parameter away from the device at trap edge, and can cause very big influence for the performance of whole SRAM like this.
Summary of the invention
The invention provides a kind of method of the SRAM of reducing trap proximity effect, solve in the prior art ion implantation process and the trap proximity effect occurs, the problem that the performance of whole SRAM is impacted.
For addressing the above problem, the invention provides a kind of method of the SRAM of reducing trap proximity effect, comprise the following steps,
At least three initial Bututs of SRAM are provided, have adjacent N trap and P trap in the initial Butut of described each SRAM in abutting connection with the border;
With two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance obtain corresponding SRAM updating layout; Described each SRAM updating layout N trap width difference;
Measure at least 3 electrical parameters, the electric parameter variation trend that obtains recording according to the SRAM device of SRAM updating layout formation;
If measured electric parameter variation trend is identical with the variation tendency of corresponding target value, then more measured electrical parameter and corresponding desired value;
If the difference of described electrical parameter that records and corresponding target value then adopts the SRAM updating layout of this electrical parameter correspondence within tolerance.
Described measurement is same a kind of electrical parameter of measuring same metal-oxide-semiconductor in the SRAM device according to the electrical parameter of the SRAM device that the SRAM updating layout forms.
Described electrical parameter is the threshold voltage of metal-oxide-semiconductor.
Described with two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance comprise, the border of N trap and P trap adjacency is moved to P trap direction, another border moving direction of N trap is with described opposite in abutting connection with the border moving direction, and move to the direction of N trap on another border of P trap; Perhaps with the moving to N trap direction in abutting connection with the border of P trap and N trap, the moving direction on another border of P trap is with described opposite in abutting connection with the border moving direction, and move to the direction of P trap on another border of N trap.
The method of the described SRAM of reducing trap proximity effect also comprises, if the variation tendency of measured electric parameter variation trend and corresponding target value is inequality, then with the moving direction negate on two borders in the same trap of the initial Butut of single SRAM, and keep that displacement is constant to regain corresponding SRAM updating layout.
The method of the described SRAM of reducing trap proximity effect also comprises, if measured electric parameter variation trend is identical with the variation tendency of corresponding target value, the measured electrical parameter and the difference of corresponding target value exceed tolerance, the displacement that then changes two borders in the same trap of the initial Butut of single SRAM regains corresponding SRAM updating layout, up to the electrical parameter of the measured SRAM device that forms according to described SRAM updating layout and corresponding desired value difference within tolerance.
Compared with prior art, the method of the above-mentioned disclosed SRAM of reducing trap proximity effect has the following advantages: in the method for the above-mentioned disclosed SRAM of reducing trap proximity effect, by changing moving direction and the displacement that has in the initial Butut of SRAM in abutting connection with two borders of the adjacent N trap on border and P trap, obtain making the SRAM device of corresponding SRAM updating layout to meet the moving direction and the displacement on two borders of adjacent N trap that desired value requires and P trap.And the SRAM device that meets the desired value requirement has good matching, has also reduced the trap proximity effect.And, owing to only need moving direction and displacement, just can obtain reducing the changing method of trap proximity effect, thereby the described method efficient that reduces the trap proximity effect is higher by two borders that change described adjacent N trap and P trap.
Description of drawings
Fig. 1 is a kind of embodiment process flow diagram of the present invention's method of reducing SRAM trap proximity effect;
Fig. 2 is the adjacent N trap and the P well structure synoptic diagram of method shown in Figure 1;
Fig. 3 be corresponding adjacent N trap shown in Figure 2 and P well structure the N trap and the wide variety synoptic diagram of P trap;
Fig. 4 is an embodiment of the invention SRAM circuit diagram.
Embodiment
In the method that reduces SRAM trap proximity effect disclosed in this invention, by changing moving direction and the displacement that has in the SRAM Butut in abutting connection with two borders of the adjacent N trap on border and P trap, obtain making the SRAM device of corresponding SRAM Butut to meet the moving direction and the displacement on two borders of adjacent N trap that desired value requires and P trap.And the SRAM device that meets the desired value requirement has good matching, has also reduced the trap proximity effect.And, owing to only need moving direction and displacement, just can obtain reducing the changing method of trap proximity effect, thereby the described method efficient that reduces the trap proximity effect is higher by two borders that change described adjacent N trap and P trap.
With reference to shown in Figure 1, a kind of embodiment that the present invention reduces the method for SRAM trap proximity effect comprises the following steps,
Step s1 provides at least three initial Bututs of SRAM, has adjacent N trap and P trap in abutting connection with the border in the initial Butut of described each SRAM;
Step s2, with two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance obtain corresponding SRAM updating layout; Described each SRAM updating layout N trap width difference;
Step s3 measures at least 3 electrical parameters according to the SRAM device of SRAM updating layout formation, the electric parameter variation trend that obtains recording;
Step s4, the variation tendency of the judging measured electrical parameter whether variation tendency with corresponding desired value is identical, if described variation tendency is identical with the variation tendency of desired value, execution in step s5 then; If the variation tendency of described variation tendency and desired value is inequality, then execution in step s6;
Step s5 compares electrical parameter and corresponding desired value according to the SRAM device of described SRAM updating layout formation;
Step s6 with the moving direction negate on two borders in the same trap of the initial Butut of single SRAM, and keeps the constant SRAM updating layout that regains correspondence of displacement, and returns step s3
Step s7, whether the difference of judging described electrical parameter and corresponding desired value is within tolerance, if difference is within tolerance, execution in step s8 then; Exceed tolerance as if difference, then execution in step s9;
Step s8 adopts the SRAM updating layout of this electrical parameter correspondence;
Step s9, the displacement that only changes two borders in the same trap of the initial Butut of single SRAM regains corresponding SRAM updating layout, and returns step s5.
Described measurement is same a kind of electrical parameter of measuring same metal-oxide-semiconductor in the SRAM device according to the electrical parameter of the SRAM device that the SRAM updating layout forms.
Described electrical parameter is the threshold voltage of metal-oxide-semiconductor.
Described with two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance comprise, the border of N trap and P trap adjacency is moved to P trap direction, another border moving direction of N trap is with described opposite in abutting connection with the border moving direction, and move to the direction of N trap on another border of P trap; Perhaps with the moving to N trap direction in abutting connection with the border of P trap and N trap, the moving direction on another border of P trap is with described opposite in abutting connection with the border moving direction, and move to the direction of P trap on another border of N trap.
Changing object lesson that N trap and P trap width in the Butut reduce SRAM trap proximity effect below by one, to make that the present invention reduces the method for SRAM trap proximity effect clearer.
With reference to shown in Figure 1, execution in step s1 provides at least three initial Bututs of SRAM, has adjacent N trap and P trap in abutting connection with the border in the initial Butut of described each SRAM.In general, variation tendency for the electrical parameter that can access the SRAM device, at least need to measure the electrical parameter value of same metal-oxide-semiconductor in three different SRAM devices, same metal-oxide-semiconductor is meant the corresponding metal-oxide-semiconductor that is arranged in SRAM device same position in the described different SRAM devices.Choose four initial Bututs of SRAM in this example as the required Butut of variation tendency of measuring electrical parameter.
Conventional SRAM circuit is with reference to shown in Figure 4, be dual-port 8 pipe SRAM, described SRAM comprises two back-to-back first phase inverters and second phase inverter, i.e. the output of first phase inverter links to each other with the input of second phase inverter, and the output of second phase inverter links to each other with the input of first phase inverter.Described first phase inverter comprises PMOS pipe MP1 and NMOS pipe MN1, and described second phase inverter comprises PMOS pipe MP2 and NMOS pipe MN2.Described SRAM also comprises four NMOS pipe MN3～MN6 as transmission gate.Wherein the grid of NMOS pipe MN3 links to each other with word line WLB, and drain electrode links to each other with bit line BLB, and source electrode links to each other with the output of first phase inverter; The grid of NMOS pipe MN4 links to each other with word line WLB, and drain electrode links to each other with additional bit line/BLB, and source electrode links to each other with the output of second phase inverter; The grid of NMOS pipe MN5 links to each other with word line WLA, and drain electrode links to each other with bit line BLA, and source electrode links to each other with the output of first phase inverter; The grid of NMOS pipe MN6 links to each other with word line WLA, and drain electrode links to each other with additional bit line/BLA, and source electrode links to each other with the output of second phase inverter.
And the initial Butut of corresponding described SRAM circuit can be designed to have in abutting connection with the adjacent N trap on border and the structure of P trap, correspondingly, also has in the SRAM device according to the initial Butut formation of described SRAM to have in abutting connection with the adjacent N trap on border and the semiconductor structure of P trap.With reference to shown in Figure 2, the semiconductor structure of described adjacent N trap with adjacent border and P trap comprises in the N trap 12 and P trap 11 and substrate 10 on silicon substrate 10, the silicon substrate 10, the isolation structure 17 between N trap 12 and the P trap 11.Described semiconductor structure is a semiconductor structure with adjacent NMOS and PMOS in fact, described NMOS is formed on the P trap 11, comprise source/drain electrode 14 that the grid structure 16 that is positioned on the silicon substrate 10 and silicon substrate 10 are positioned at grid structure 16 both sides and leakage/source electrode 14 '.Described PMOS is formed on the N trap 12, comprise source/drain electrode 13 that the grid structure 15 that is positioned on the silicon substrate 10 and silicon substrate 10 are positioned at grid structure 15 both sides and leakage/source electrode 13 '.
Continue with reference to shown in Figure 1, execution in step s2, with two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance obtain corresponding SRAM updating layout; Described each SRAM updating layout N trap width difference.
Moving to P trap direction in abutting connection with the border of N trap and P trap at first is set herein, and another border moving direction of N trap is with described opposite in abutting connection with the border moving direction, and move to the direction of N trap on another border of P trap.Please refer to shown in Figure 3, N trap 12 is owing to N trap and P trap moves to the P trap in abutting connection with the border, and move to the direction away from the P trap on another border, the N trap by the position shown in the original solid box expand to frame of broken lines 12 ' shown in the position, and widening of N trap 12 is that identical width is widened on the border, both sides simultaneously; P trap 11 then since with the moving to P trap direction of N trap in abutting connection with the border, move to N trap direction on another border, the P trap by position shown in the original solid box taper to dot-dash wire frame 11 ' shown in the position, and the reduction of P trap 11 is that the border, both sides subtracts narrow identical width simultaneously.Described width adjustment process is exactly the distance between the process photoresistance of adjusting ion injection formation trap in fact.By learning in the description of aforesaid trap proximity effect, the distance between the photoresistance is closely related to the influence that device performance produces with the trap proximity effect.Thereby, by adjusting the distance between the photoresistance, just can access along with distance between photoresistance changes, the electrical parameter of formed device is because the variation that the trap proximity effect is produced.
Then, set the displacement on described two borders, because SRAM is relatively stricter for the designing requirement of size of devices, therefore the displacement value on two borders that set need be within the scope that design allows.The N trap that for example designing requirement limited or the changing value of P trap are at ± 40nm, and the displacement value on each bar border on two borders that set so just can not surpass 20nm.And, the displacement value on two different borders all is set for the initial Butut of each SRAM.As mentioned above, this example has been chosen four SRAM, the spacing value of displacement value of setting each bar limit on two borders between the initial Butut of each SRAM so is 5nm, the initial Butut of first SRAM is set to: N trap and P trap moved 5nm in abutting connection with the border to P trap direction, 5nm is moved to the direction away from the P trap in another border, 5nm is moved to N trap direction in another border of P trap, and promptly the N trap is widened 10nm, the P trap subtracts narrow 10nm; Second initial Butut of SRAM is set to: N trap and P trap move 10nm in abutting connection with the border to P trap direction, 10nm is moved to the direction away from the P trap in another border, 10nm is moved to N trap direction in another border of P trap, and promptly the N trap is widened 20nm, the P trap subtracts narrow 20nm; The 3rd the initial Butut of SRAM is set to: N trap and P trap move 15nm in abutting connection with the border to P trap direction, 15nm is moved to the direction away from the P trap in another border, 15nm is moved to N trap direction in another border of P trap, and promptly the N trap is widened 30nm, the P trap subtracts narrow 30nm; The 4th the initial Butut of SRAM is set to: N trap and P trap move 20nm in abutting connection with the border to P trap direction, 20nm is moved to the direction away from the P trap in another border, 20nm is moved to N trap direction in another border of P trap, and promptly the N trap is widened 40nm, the P trap subtracts narrow 40nm.Through above-mentioned change, the initial Butut of each SRAM has obtained each self-corresponding SRAM updating layout.Above-mentioned example is not in order to qualification only for making explanation clearer, and the interval of the displacement on two borders can require according to the efficient of designing requirement and debugging decide in the value of the displacement on described two borders and the same trap of the initial Butut of each SRAM.
Continue with reference to shown in Figure 2, the change of the corresponding above-mentioned initial Butut of SRAM, suppose adjacent N trap 12 and P trap 11 in the SRAM device of the initial Butut correspondence of first SRAM in abutting connection with boundary position 18 places in the separatrix originally, by above-mentioned with N trap width widen 10nm in the initial Butut of first SRAM, after P trap width subtracts narrow 10nm, 19 places, separatrix have just been moved in abutting connection with boundary position according to N trap and P trap in the formed semiconductor structure of SRAM updating layout that obtains.
With reference to shown in Figure 1, execution in step s3 measures at least 3 electrical parameters according to the SRAM device of SRAM updating layout formation, the electric parameter variation trend that obtains recording.
When obtained each corresponding SRAM device according to described each SRAM updating layout after, just choose the same metal-oxide-semiconductor in described each SRAM device, and measure the electrical parameter of described metal-oxide-semiconductor by checkout equipment.Measured electrical parameter is the threshold voltage of metal-oxide-semiconductor in this example.After by the threshold voltage that measures same metal-oxide-semiconductor in described each SRAM device, just can access the Trendline of threshold voltage.
In conjunction with illustrated in figures 1 and 2, execution in step s4, the variation tendency of the judging measured electrical parameter whether variation tendency with corresponding desired value is identical, if described variation tendency is identical with the variation tendency of desired value, execution in step s5 then; If the variation tendency of described variation tendency and desired value is inequality, then execution in step s6.
For each SRAM device, electrical parameter on the described same metal-oxide-semiconductor, for example threshold voltage all has each self-corresponding desired value with the index as the detection performance, the threshold voltage of the described same metal-oxide-semiconductor in for example corresponding first SRAM device has first desired value, and the threshold voltage of the described same metal-oxide-semiconductor in corresponding second SRAM device has second desired value, and can access the Trendline of the desired value of same metal-oxide-semiconductor described in each SRAM according to described desired value.Then, the Trendline of the threshold voltage of same metal-oxide-semiconductor among the Trendline of the desired value of resulting threshold voltage and corresponding each SRAM that measures is compared, if the trend of the described threshold voltage that measures is inequality with the variation tendency of corresponding desired value, the moving direction on two borders that set adjacent N trap and P trap then are described is wrong, just needs to change the moving direction on two borders of described adjacent N trap and P trap this moment.
Continue the above-mentioned N of widening trap, subtract the example of narrow P trap, if find that the trend of measured threshold voltage is inequality with corresponding desired value variation tendency, then described each SRAM Butut is changed into: with moving to N trap direction of N trap and P trap in abutting connection with the border, move to P trap direction on another border, move to the direction away from the N trap on another border in two borders of P trap, promptly subtracts narrow N trap width, widens P trap width.And, displacement to two borders of described adjacent N trap and P trap is also reset: in order to narrate conveniently, here also the displacement on two borders of adjacent N trap and P trap in each SRAM Butut is made as 5nm, 10nm, 15nm and 20nm respectively, promptly first SRAM Butut is set to: N trap and P trap moved 5nm in abutting connection with the border to N trap direction, 5nm is moved to P trap direction in another border, another border of P trap is to away from the mobile 5nm of the direction of N trap, and promptly the N trap subtracts narrow 10nm, the P trap is widened 10nm; Second SRAM Butut is set to: N trap and P trap moved 10nm in abutting connection with the border to N trap direction, 10nm is moved to P trap direction in another border, another border of P trap is to away from the mobile 10nm of the direction of N trap, and promptly the N trap subtracts narrow 20nm, the P trap is widened 20nm; The 3rd SRAM Butut is set to: with N trap and P trap move 15nm in abutting connection with the border to N trap direction, 15nm is moved to P trap direction in another border, another border of P trap is to away from the mobile 15nm of the direction of N trap, promptly the N trap subtracts narrow 30nm, the P trap is widened 30nm; The 4th SRAM Butut is set to: N trap and P trap moved 20nm in abutting connection with the border to N trap direction, 20nm is moved to P trap direction in another border, another border of P trap is to away from the mobile 20nm of the direction of N trap, and promptly the N trap subtracts narrow 40nm, the P trap is widened 40nm.Through above-mentioned change, each SRAM Butut has obtained each self-corresponding SRAM updating layout again.
Continue with reference to shown in Figure 2, for example to first SRAM Butut, by N trap width in the described Butut is subtracted narrow 10nm, obtain the SRAM updating layout behind the P trap width widen 10nm, according to adjacent N trap and P trap in the formed SRAM device of described SRAM updating layout in abutting connection with boundary position in the separatrix 20 places.Then, measure the threshold voltage of same metal-oxide-semiconductor described in the SRAM device that forms according to described SRAM updating layout once more, and obtain the Trendline of new threshold voltage with described adjacent N trap and P trap wide variety.And once more resulting Trendline is compared with the variation tendency line of corresponding desired value, the variation tendency with corresponding desired value is identical to judge described variation tendency.
If described variations in threshold voltage trend is identical with the variation tendency of desired value, illustrate then in each set SRAM Butut that the moving direction on two borders is correct in the same trap, next just need to have debugged set displacement value.
Continue with reference to shown in Figure 1, execution in step s5 compares electrical parameter and corresponding desired value according to the SRAM device of described SRAM updating layout formation.When the variation tendency of the variations in threshold voltage trend of described metal-oxide-semiconductor and corresponding target value is identical, with regard to the difference between the comparative threshold voltage desired value corresponding with it.
Continue with reference to shown in Figure 1, execution in step s7, the difference of judging described electrical parameter and corresponding desired value whether within tolerance, as if difference within tolerance, execution in step s8 then; Exceed tolerance as if difference, then execution in step s9.
In this step, all be to compare with the tolerance of setting respectively for the threshold voltage of same metal-oxide-semiconductor described in resulting each SRAM and the difference of pairing desired value.Described tolerance is for requiring the difference range accepted of preset threshold voltage and corresponding desired value according to fabrication error and design accuracy, for example according to fabrication error and design accuracy requirement, threshold voltage is 30% of a described desired value with the acceptable difference range of difference of corresponding desired value, and so described tolerance is exactly 30% of a desired value.
If difference exceeds tolerance, then need to change described displacement value.For example strengthen the displacement value, and obtain new threshold voltage once more by above-mentioned steps, if new threshold voltage value is with respect to before more near desired value, then illustrate for described SRAM, the displacement value on two borders of N trap and P trap is big more, the then measured threshold voltage that obtains is more near desired value, and therefore only need continue to increase the displacement value just can obtain the threshold voltage within tolerance.And if increasing displacement value makes then just need constantly reduce threshold voltage wide value the displacement value and make threshold voltage drop within the tolerance on the contrary.
If difference within tolerance, illustrates that then set displacement value is more suitable.
At last, exactly the moving direction and the displacement on two borders of described adjacent N trap and P trap is applied to obtain on the corresponding initial Butut of SRAM the SRAM updating layout.And according to aforesaid analysis, the matching of the SRAM device that forms according to described SRAM updating layout is better, has also reduced the trap proximity effect.Chosen four initial Bututs of SRAM in this example, therefore last what use also is the SRAM updating layout that has adopted the variation scheme of the moving direction on two borders of adjacent N trap of quadruplet and P trap and displacement.Certainly, all that also can choose on the wafer for example have the crystal grain of SRAM as test structure, and all corresponding initial Bututs of each SRAM are provided with the moving direction on two borders of a kind of adjacent N trap and P trap and the variation scheme of displacement, and obtain being suitable for the moving direction on two borders of the adjacent N trap of each SRAM Butut and P trap and the variation scheme of displacement according to above-mentioned method equally.Owing in this process, only need the moving direction and the displacement on two borders of adjacent N trap of change and P trap just can obtain the trend of the electrical parameter of SRAM, thereby debugging efficiency is higher with wide variety.
In addition, the Butut of all changes scheme also can be provided in advance for the process of the above-mentioned acquisition electrical parameter trend identical with the desired value variation tendency, it is opposite promptly same Butut to be provided with the moving direction on two kinds of two borders simultaneously, the wide variety scheme that the displacement value is identical, and measure all changes scheme the Butut correspondence SRAM electrical parameter and obtain Trendline, finally determine suitable variation scheme.
In sum, in the above-mentioned disclosed method that reduces SRAM trap proximity effect, by changing moving direction and the displacement that has in the SRAM Butut in abutting connection with two borders of the adjacent N trap on border and P trap, obtain making the SRAM device of corresponding SRAM Butut to meet the moving direction and the displacement on two borders of adjacent N trap that desired value requires and P trap.And the SRAM device that meets the desired value requirement has good matching, has also reduced the trap proximity effect.And, owing to only need moving direction and displacement, just can obtain reducing the changing method of trap proximity effect, thereby the described method efficient that reduces the trap proximity effect is higher by two borders that change described adjacent N trap and P trap.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (6)
1. a method that reduces SRAM trap proximity effect is characterized in that, comprise the following steps,
At least three initial Bututs of SRAM are provided, have adjacent N trap and P trap in the initial Butut of described each SRAM in abutting connection with the border;
With two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance obtain corresponding SRAM updating layout; Described each SRAM updating layout N trap width difference;
Measure at least 3 electrical parameters, the electric parameter variation trend that obtains recording according to the SRAM device of SRAM updating layout formation;
If measured electric parameter variation trend is identical with the variation tendency of corresponding target value, then more measured electrical parameter and corresponding desired value;
If the difference of described electrical parameter that records and corresponding target value then adopts the SRAM updating layout of this electrical parameter correspondence within tolerance.
2. the method that reduces SRAM trap proximity effect as claimed in claim 1 is characterized in that, described measurement is same a kind of electrical parameter of measuring same metal-oxide-semiconductor in the SRAM device according to the electrical parameter of the SRAM device that the SRAM updating layout forms.
3. the method that reduces SRAM trap proximity effect as claimed in claim 2 is characterized in that, described electrical parameter is the threshold voltage of metal-oxide-semiconductor.
4. the method that reduces SRAM trap proximity effect as claimed in claim 1, it is characterized in that, described with two borders in the same trap of the initial Butut of single SRAM round about the mobile phase same distance comprise, the border of N trap and P trap adjacency is moved to P trap direction, another border moving direction of N trap is with described opposite in abutting connection with the border moving direction, and move to the direction of N trap on another border of P trap; Perhaps with the moving to N trap direction in abutting connection with the border of P trap and N trap, the moving direction on another border of P trap is with described opposite in abutting connection with the border moving direction, and move to the direction of P trap on another border of N trap.
5. as each described method that reduces SRAM trap proximity effect of claim 1 to 4, it is characterized in that, also comprise, if the variation tendency of measured electric parameter variation trend and corresponding target value is inequality, then with the moving direction negate on two borders in the same trap of the initial Butut of single SRAM, and keep that displacement is constant to regain corresponding SRAM updating layout.
6. as each described method that reduces SRAM trap proximity effect of claim 1 to 4, it is characterized in that, also comprise, if measured electric parameter variation trend is identical with the variation tendency of corresponding target value, the measured electrical parameter and the difference of corresponding target value exceed tolerance, the displacement that then changes two borders in the same trap of the initial Butut of single SRAM regains corresponding SRAM updating layout, up to the electrical parameter of the measured SRAM device that forms according to described SRAM updating layout and corresponding desired value difference within tolerance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100944840A CN101458720B (en) | 2007-12-13 | 2007-12-13 | Method for reducing proximity effect of SRAM trap |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100944840A CN101458720B (en) | 2007-12-13 | 2007-12-13 | Method for reducing proximity effect of SRAM trap |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101458720A true CN101458720A (en) | 2009-06-17 |
| CN101458720B CN101458720B (en) | 2010-09-29 |
Family
ID=40769577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100944840A Active CN101458720B (en) | 2007-12-13 | 2007-12-13 | Method for reducing proximity effect of SRAM trap |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101458720B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
| CN102142383B (en) * | 2010-02-03 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
| CN102956425A (en) * | 2011-08-22 | 2013-03-06 | 北京中科信电子装备有限公司 | Method for quickly finding out largest beam value |
| CN105260538A (en) * | 2015-10-14 | 2016-01-20 | 上海华力微电子有限公司 | Modeling method for SRAM unit |
| CN107275327A (en) * | 2011-07-26 | 2017-10-20 | 瑞萨电子株式会社 | Semiconductor devices |
| CN107798197A (en) * | 2017-10-31 | 2018-03-13 | 上海华力微电子有限公司 | A kind of standard cell lib layout design method of reduction WPE effects |
| WO2023029566A1 (en) * | 2021-09-03 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006134939A (en) * | 2004-11-02 | 2006-05-25 | Nec Electronics Corp | Semiconductor device |
-
2007
- 2007-12-13 CN CN2007100944840A patent/CN101458720B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142383B (en) * | 2010-02-03 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
| CN107275327A (en) * | 2011-07-26 | 2017-10-20 | 瑞萨电子株式会社 | Semiconductor devices |
| CN107275327B (en) * | 2011-07-26 | 2021-08-24 | 瑞萨电子株式会社 | Semiconductor device with a plurality of transistors |
| CN102956425A (en) * | 2011-08-22 | 2013-03-06 | 北京中科信电子装备有限公司 | Method for quickly finding out largest beam value |
| CN105260538A (en) * | 2015-10-14 | 2016-01-20 | 上海华力微电子有限公司 | Modeling method for SRAM unit |
| CN105260538B (en) * | 2015-10-14 | 2019-06-28 | 上海华力微电子有限公司 | A kind of sram cell modeling method |
| CN107798197A (en) * | 2017-10-31 | 2018-03-13 | 上海华力微电子有限公司 | A kind of standard cell lib layout design method of reduction WPE effects |
| CN107798197B (en) * | 2017-10-31 | 2021-05-21 | 上海华力微电子有限公司 | Standard cell library layout design method for reducing WPE effect |
| WO2023029566A1 (en) * | 2021-09-03 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101458720B (en) | 2010-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101458720B (en) | Method for reducing proximity effect of SRAM trap | |
| US9478553B2 (en) | SRAM cell connection structure | |
| US9269639B2 (en) | Method of detecting and measuring contact alignment shift relative to gate structures in a semicondcutor device | |
| CN105807556B (en) | Layout correction method | |
| US7868606B2 (en) | Process variation on-chip sensor | |
| KR20140012012A (en) | Memory cell | |
| US20170323894A1 (en) | Layout pattern for static random access memory | |
| KR20140107083A (en) | Cell and macro placement on fin grid | |
| US9401366B1 (en) | Layout pattern for 8T-SRAM and the manufacturing method thereof | |
| CN106206586B (en) | Static random access memory | |
| US8394681B2 (en) | Transistor layout for manufacturing process control | |
| CN109216455A (en) | Semiconductor devices and forming method thereof | |
| US8409882B2 (en) | Differential FET structures for electrical monitoring of overlay | |
| US8508017B2 (en) | Test device and semiconductor integrated circuit device | |
| US20150179536A1 (en) | Circuit technique to electrically characterize block mask shifts | |
| CN103346107A (en) | Method for detecting alignment degree between polycrystalline silicon grid and contact hole | |
| US8258805B2 (en) | Test device and semiconductor integrated circuit device | |
| KR20140008099A (en) | Semiconductor memory device | |
| Patterson et al. | In-line characterization of EDRAM for a FINFET technology using VC inspection | |
| CN101458721B (en) | Method for reducing backward effect of narrow channel | |
| US20070051948A1 (en) | Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices | |
| Balasinski | A methodology to analyze circuit impact of process-related MOSFET geometry | |
| US6746882B1 (en) | Method of correcting non-linearity of metrology tools, and system for performing same | |
| CN101452742B (en) | Method for improving SRAM matching degree | |
| KR101387689B1 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |