CN101453308B - IP clock packet processing method, equipment and system - Google Patents
IP clock packet processing method, equipment and system Download PDFInfo
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- CN101453308B CN101453308B CN2008101901300A CN200810190130A CN101453308B CN 101453308 B CN101453308 B CN 101453308B CN 2008101901300 A CN2008101901300 A CN 2008101901300A CN 200810190130 A CN200810190130 A CN 200810190130A CN 101453308 B CN101453308 B CN 101453308B
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Abstract
The embodiment of the invention relates to a method, a device and a system for processing IP clock messages. The method comprises: acquiring timestamp information which is obtained by analyzing the IP clock messages through a network processor in an analysis mode corresponding to the message type of the received IP clock messages and corresponds to the IP clock messages; and acquiring clock adjustment reference information which is used by a master control unit to adjust local timestamp information according to the timestamp information and the local timestamp information. The device comprises a first receiving module and a first processing module, wherein the first receiving module is used for acquiring the timestamp information which is obtained by analyzing the received IP clock messages through the network processor and corresponds to the IP clock messages; and the first processing module is used for acquiring the clock adjustment reference information which is used for the master control unit to adjust a clock according to the timestamp information and the local timestamp information. The method, the device and the system can flexibly analyze complex IP clock messages which are newly expanded and packaged by protocols by adoption of the network processor to analyze the IP clock messages.
Description
Technical field
The embodiment of the invention relates to wireless communication technology field, relates in particular to a kind of IP clock packet processing method, equipment and system.
Background technology
Along with procotol (Internet Protocol, hereinafter to be referred as: IP) the continuous development of packet switching network, the stationary problem of IP clock becomes increasingly conspicuous.What transmit in the digital exchange system is the discrete pulse signal that obtains after information is encoded, inconsistent as if the IP clock between two digital local exchange installations, will in the buffer storage of digital exchange system, produce losing or repeating of code element, cause in the bit stream of transmission, occurring the damage of sliding.For example, at traditional fixed network time division multiplexing (Time DivisionMultiplex; Hereinafter to be referred as: when TDM) business is by Ethernet bearing,, then very easily cause slip, cause TDM voice and data traffic transmission deterioration, even transmission is interrupted if the IP clock at bearer network two ends is inconsistent; If the IP clock between the IP wireless access network different base station can not can occur going offline when then service application is switched in the base station synchronously in certain precision.
The main adaptive clock recovery technology that adopts realizes the synchronous of IP clock in the prior art.In the adaptive clock recovery technology, the IP clock information is packaged into the IP clock message, (the Application Specific Integrated Circuit of special-purpose integrated circuit in the transmission equipment, hereinafter to be referred as: logical block ASIC), as field programmable gate array (Field-Programmable Gate Array, hereinafter to be referred as: FPGA) can from this IP clock message, extract the IP clock information, and according to the IP clock information calculation delay value that extracts; Then, logical block reports this time delay value the main control unit of CPU; At last, main control unit carries out digital-to-analogue conversion to this time delay value to be handled, and adjusts local clock module according to the IP clock information that obtains after the digital-to-analogue conversion processing, thereby realization IP clock is synchronous.
The inventor is in realizing process of the present invention, find that there is following shortcoming at least in prior art: because the program of the logical block of ASIC is to be cured in this logical block, therefore this logical block lacks autgmentability, only can resolve the IP clock message of set form and protocol type, and can not resolve the IP clock message that protocol format new expansion, complicated encapsulates, thereby cause the logical block of ASIC to have limitation when carrying out the parsing of IP clock message, suitable protocol type scope is little.
Summary of the invention
The embodiment of the invention provides a kind of IP clock packet processing method, equipment and system, logical block lacks autgmentability in the prior art in order to solve, only can resolve the IP clock message of set form and protocol type, and can not resolve the defective of the IP clock message of protocol format encapsulation new expansion, complicated, realize neatly IP clock message complexity, new expansion being resolved.
The embodiment of the invention provides a kind of IP clock packet processing method, comprising:
Obtain network processing unit adopt the analysis mode corresponding with the type of message of the IP clock message that receives to described IP clock message resolve acquisition, with described IP clock message time corresponding stamp information;
According to described timestamp information and local time stamp information, obtain main control unit and adjust the used clock adjustment reference information of described local time stamp information.
The embodiment of the invention provides a kind of IP clock packet processing method, comprising:
Network processing unit receives the IP clock message, determines the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and described IP clock message time corresponding stamp information to described IP clock message;
Described network processing unit obtains main control unit and carries out the used clock adjustment reference information of clock adjustment according to described timestamp information and local time stamp information.
The embodiment of the invention provides a kind of IP clock message treatment facility, comprising:
First receiver module, be used to obtain network processing unit adopt the analysis mode corresponding with the type of message of the IP clock message that receives to described IP clock message resolve acquisition, with described IP clock message time corresponding stamp information;
First processing module is used for according to described timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.
The embodiment of the invention provides a kind of network processing unit, comprising:
Second receiver module is used to receive the IP clock message that outside network device that field programmable gate array transmits sends, or the IP clock message that sends of outside network device;
Second parsing module, the type of message of the IP clock message that is used for determining that described second receiver module receives adopts the analysis mode corresponding with described type of message that described IP clock message is resolved, and obtains and described IP clock message time corresponding stamp information;
Second sending module is used for described timestamp information is sent to described field programmable gate array.
The embodiment of the invention also provides a kind of network processing unit, comprising:
The 3rd parsing module is used to receive the IP clock message, determines the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and described IP clock message time corresponding stamp information to described IP clock message;
The 3rd processing module is used for according to described timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.
The embodiment of the invention provides a kind of IP clock message treatment system, comprising:
Network processing unit, receive the IP clock message, determine the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and described IP clock message time corresponding stamp information to the described IP clock message that receives;
IP clock message treatment facility is used to receive the described timestamp information that described network processing unit sends, and according to described timestamp information and local time stamp information, obtains clock and adjusts used clock adjustment reference information;
Main control unit is used for adjusting reference information according to the described clock that described IP clock message treatment facility sends and carries out the clock adjustment.
The embodiment of the invention also provides a kind of IP clock message treatment system, comprising:
Network processing unit, be used to receive the IP clock message, determine the type of message of described IP clock message, adopt the analysis mode corresponding that described IP clock message is resolved with described type of message, obtain to stab information with described IP clock message time corresponding, and, obtain clock and adjust used clock adjustment reference information according to described timestamp information and local time stamp information;
Main control unit is used for adjusting reference information according to described clock and carries out the clock adjustment.
IP clock packet processing method, equipment and system that the embodiment of the invention provides, adopt the analysis mode corresponding that the IP clock message is resolved by network processing unit with the type of message of the IP clock message that receives, make network processing unit utilize the microcode programming just can resolve IP clock messages more complexity, the new protocol encapsulation of expanding neatly, thereby the IP clock message that network processing unit is resolved is not limited to simply, the IP clock message of prior protocols form encapsulation, has enlarged the scope of the protocol format that can resolve encapsulation IP clock message.
Description of drawings
Fig. 1 is the flow chart of IP clock packet processing method first embodiment of the present invention;
Fig. 2 obtains the principle schematic that clock is adjusted the reference information process for FPGA among IP clock packet processing method first embodiment of the present invention;
Fig. 3 is the flow chart of IP clock packet processing method second embodiment of the present invention;
Fig. 4 is the flow chart of IP clock packet processing method the 3rd embodiment of the present invention;
Fig. 5 is the flow chart of IP clock packet processing method the 4th embodiment of the present invention;
Fig. 6 is the structural representation of IP clock message treatment facility first embodiment of the present invention;
Fig. 7 is the structural representation of IP clock message treatment facility second embodiment of the present invention;
Fig. 8 is the structural representation of network processing unit first embodiment of the present invention;
Fig. 9 is the structural representation of network processing unit second embodiment of the present invention;
Figure 10 is the structural representation of IP clock message treatment system first embodiment of the present invention;
Figure 11 is the structural representation of IP clock message treatment system second embodiment of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the flow chart of IP clock packet processing method first embodiment of the present invention, and as shown in Figure 1, the method for present embodiment comprises:
For E1 T1 for this network environment of STM-1, the clock information that is used for carrying out clock synchronization between each network element all is the form transmission of adopting the IP clock message.So-called clock synchronization is meant to keep certain strict particular kind of relationship between the signal that on frequency or phase place occur with same Mean Speed its corresponding significant instant, to keep equipment all in the communication network with identical speed operation.
For instance, in order to obtain this clock information, FPGA can receive network processing unit (Network Processor, hereinafter to be referred as: NP) send, this NP stabs information to what the IP clock message that receives was resolved acquisition with IP clock message time corresponding.
Particularly, present embodiment can adopt NP that the IP clock message that receives is resolved.NP is the programmable processor that designs for handle packet specially, can directly finish the general task of network data processing.It applies specifically to the various Processing tasks of the communications field, such as converging and fire compartment wall etc. of bag processing, protocal analysis, route querying, sound/data.
The NP device inside is made up of several microcode processors and some hardware co-processor usually, and a plurality of microcode processor comes the control and treatment flow process in the inner parallel processing of NP by the microcode of working out in advance.For some complicated standard operation,, then adopt hardware co-processor further to improve handling property as the congestion avoidance algorithm of internal memory operation, routing table lookup algorithm and flow scheduling algorithm etc.NP supports programming fully, and programming mode is simple, in case have new technology or demand to occur, can realize by the microcode programming easily, thereby technology and function follow-up and extended capability faster more flexibly are provided.
By These characteristics as can be seen, because NP has extended capability flexibly, therefore along with the agreement that is used to encapsulate the IP clock message constantly develops, NP can programme by microcode and support more protocol type, thereby makes NP can discern the more IP clock message of multi-protocols encapsulation neatly.Therefore, NP in the present embodiment is when resolving the IP clock message that receives, can be according to the type of message of the IP clock message that receives, adopt the analysis mode corresponding that this IP clock message is resolved with this type of message, thereby can support to be present in E1 T1 point-to-point multiplex protocol (Point to Point Protocol Multiplexing in this network environment of STM-1, hereinafter to be referred as: PPPMUX), Multi-Link Point-to-Point Protocol (Multi Link Point to Point Protocol, hereinafter to be referred as: MLPPP), IP compressing head file (IP Header Compression, hereinafter to be referred as: IPHC) and compressed real-time transport protocol (Compressed Real-time Transport Protocol, hereinafter to be referred as: CRTP) wait these complex protocols.
NP can obtain with this IP clock message time corresponding and stab information by the IP clock message that parsing receives, and this timestamp information promptly is used for local clock information is carried out clock synchronization.
Specifically, FPGA can obtain clock adjustment reference information according to timestamp information that sends from NP and local time stamp information.
Fig. 2 obtains the principle schematic that clock is adjusted the reference information process for FPGA among IP clock packet processing method first embodiment of the present invention, as shown in Figure 2, this FPGA obtain clock adjust reference information method can for:
FPGA adopts phase discriminator that timestamp information and the local time stamp information that receives is compared, and obtains the relative delay.Because in the packet switching network, the relative delay of each IP clock message is different, therefore, FPGA can compare all timestamp informations and the local time stamp information that receives from NP in a period of time, find out the minimum delay, will adjust the used clock of local time stamp information as main control unit with this minimum delay time corresponding information of stabbing and adjust reference information.
Continually local time stamp information is adjusted for fear of main control unit, can also be carried out low-pass filtering, to restrain short term jitter this minimum delay.For instance, filtering algorithm can adopt method as described below:
F
m＝F
m-1+G1×(Y
m-Y
m-1)+G2×(Y
m-TransitT?arg?et)
Y wherein
mIt is the minimum delay of the m time interior message of sampling window.If the sampling period is 1 second, then m promptly represents m second.
F
mAfter being the m time sampling, the signal frequency value that calculates.F
mBe a digital signal, can be used for control figure formula phase-locked loop (Digital Phase locked loop, hereinafter to be referred as: DPLL).
TransitTarget is the average retardation of presetting, and represents the time interval of clock source and local clock in theory, and in practice, there is drift in TransitTarget.
G1 and G2 are two parameters, and G1 has embodied the inhibition (first derivative of relative delay) that line delay is changed, and G2 has embodied the inhibition to frequency drift.
Main control unit can with minimum delay time corresponding stamp information be that clock is adjusted reference information and calibrated local time stamp information, if clock is adjusted reference information greater than local time stamp information, then main control unit will improve the local clock frequency; If clock is adjusted reference information less than local time stamp information, then main control unit will reduce the local clock frequency, thereby finish the adjustment of local clock.
Present embodiment is when obtaining the IP clock information, and NP can adopt corresponding analysis mode that this IP clock message is resolved according to the type of message of the IP clock message that receives.Because NP has extended capability flexibly, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby make NP can resolve the more IP clock message of multi-protocols encapsulation neatly, overcome the limitation of prior art when resolving the IP clock message.After NP obtained corresponding timestamp information, FPGA can send the timestamp information that comes according to NP and obtain clock adjustment reference information, carries out the clock adjustment thereby make things convenient for main control unit to adjust reference information according to this clock.Further, because NP can programme by microcode, support the IP clock message of various protocols encapsulation neatly, therefore, adopt NP that the IP clock message that receives is resolved the transmission that can realize the IP clock message between networks of different type, and the situation that the IP clock message can't be identified when across a network transmits can not appear, thus reach the effect of heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
IP clock packet processing method first embodiment of the present invention can comprise two kinds of technical schemes.
A technical scheme is: FPGA receives the IP clock message from outside network device, if FPGA itself can not resolve this IP clock message, then this IP clock message is transmitted to NP, NP can resolve this IP clock message, obtain the timestamp information that carries in this IP clock message, NP sends to FPGA with this timestamp information then, and FPGA can obtain main control unit according to this timestamp information and local time stamp information to carry out clock and adjust used clock and adjust reference information.Wherein, can comprise to the IP clock message of the outside network device transmission of NP forwarding by FPGA: with the received IP clock message of NP corresponding protocols message sink mouth.
Another technical scheme is: NP directly receives the IP clock message that outside network device sends, NP sends to FPGA with this timestamp information after obtaining corresponding timestamp information in that this IP clock message is resolved, and FPGA obtains main control unit according to the timestamp information that receives and local time stamp information to carry out clock and adjust used clock and adjust reference information.
In above-mentioned two technical schemes, FPGA obtains NP the IP clock message that receives is resolved can comprising with IP clock message time corresponding stamp information of acquisition: receive NP by Serial Peripheral Interface (Serial Peripheral Interface, hereinafter to be referred as: the loopback frame information of SPI) returning, this loopback frame information comprises timestamp information, also comprises being used to identify the loopback frame sign that this loopback frame information has high priority; Identify the timestamp information that obtains in the loopback frame information according to this loopback frame.Outside network device both can be the clock source device, also can be any one network element in the network.
Adopt two embodiment that two kinds of technical schemes that IP clock packet processing method first embodiment of the present invention comprises are elaborated below.
Fig. 3 is the flow chart of IP clock packet processing method second embodiment of the present invention, and as shown in Figure 3, present embodiment is above-mentioned first technical scheme, and the method for present embodiment can comprise:
Receive the IP clock message that outside network device sends with NP corresponding protocols message sink mouth among step 301, the FPGA, this IP clock message is sent to NP;
Specifically, can comprise a plurality of protocol massages receiving ports in FPGA, each protocol massages receiving port can corresponding different agreement form.FPGA is when receiving the IP clock message of outside network device transmission, can know by which protocol massages receiving port to receive, thereby make FPGA to judge that the IP clock message that receives is that FPGA itself can resolve or FPGA itself can not resolve according to different protocol massages receiving ports.If this IP clock message is by receiving with FPGA corresponding protocols message sink mouth, the program that the FPGA inside solidification promptly is described can be resolved this IP clock message, then FPGA within it portion this IP clock message is resolved and is calculated the minimum delay, report main control unit to carry out the adjustment of local time stamp at last.If this IP clock message is by receiving with NP corresponding protocols message sink mouth, it is the protocol format that the program of FPGA inside solidification does not support to encapsulate this IP clock message, then FPGA can send to NP with this IP clock message, promptly asks NP that this IP clock message is resolved.
NP can support the various protocols type by the microcode programming, and therefore, NP can discern the more IP clock message of multi-protocols encapsulation neatly.NP in the present embodiment is when resolving the IP clock message that receives, can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved according to this type of message with this type of message, thereby can support to be present in E1 T1 these complex protocols such as PPPMUX, MLPPP, IPHC and CRTP in this network environment of STM-1.And along with the more expansion of multi-protocols form, NP can support the protocol format of new expansion by the microcode programming.
The timestamp information that the IP clock message that NP receives by parsing obtains promptly can be used for the local clock information of each network element is carried out clock synchronization.
This loopback frame sign can identify this loopback frame information and comprise the timestamp information that is used for synchronous local clock, and has high priority, thereby make when FPGA receives this loopback frame information, this loopback frame information of priority treatment, obtain the timestamp information that wherein carries, and this loopback frame information can not abandoned, guaranteed that the FPGA acquisition time stabs the reliability of information.
In addition, this loopback frame information can further include the length information and the check information of timestamp information, is used for this loopback frame information is carried out Content inspection, verification and error control etc.This loopback frame information can adopt form encapsulation as shown in table 1:
Table 1
| The loopback frame sign | Timestamp information | Length information | Check information |
If clock is adjusted reference information greater than local time stamp information, then main control unit will improve the local clock frequency; If clock is adjusted reference information less than local time stamp information, then main control unit will reduce the local clock frequency, thereby finish the adjustment of local clock.
In the present embodiment, FPGA can be when determining that according to the message sink mouth that receives the IP clock message program of FPGA inside solidification is not supported to encapsulate the protocol format of this IP clock message, determine that this IP clock message can be supported by NP, and this IP clock message is transmitted to NP, request NP resolves this IP clock message.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.After NP obtained corresponding timestamp information, FPGA can send the timestamp information that comes according to NP and obtain clock adjustment reference information, carries out the clock adjustment thereby make things convenient for main control unit to adjust reference information according to this clock.And, because NP can support the IP clock information of various protocols encapsulation neatly by the microcode programming, therefore, adopt NP that the IP clock message that receives is resolved and to realize the heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
Fig. 4 is the flow chart of IP clock packet processing method the 3rd embodiment of the present invention, and as shown in Figure 4, present embodiment is above-mentioned second technical scheme, and the method for present embodiment comprises:
The IP clock message that step 401, NP send according to the outside network device that receives is determined the type of message of this IP clock message, and adopt the analysis mode corresponding that this IP clock message is resolved with this type of message, obtain to stab information with this IP clock message time corresponding;
Specifically, (UserDatagram Protocol, hereinafter to be referred as UDP) port numbers, so NP can number know that the message that receives is the IP clock message by this udp port owing to all carry special User Datagram Protoco (UDP) in the IP clock message.
NP can support the various protocols type by the microcode programming, and therefore, NP can discern the more IP clock message of multi-protocols encapsulation neatly.NP in the present embodiment is when resolving the IP clock message that receives, can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved according to this type of message with this type of message, thereby can support to be present in E1 T1 these complex protocols such as PPPMUX, MLPPP, IPHC and CRTP in this network environment of STM-1.And along with the more expansion of multi-protocols form, NP can support the protocol format of new expansion by the microcode programming.
The timestamp information that the IP clock message that NP receives by parsing obtains promptly can be used for the local clock information of each network element is carried out clock synchronization.
This loopback frame sign can identify this loopback frame information and comprise the timestamp information that is used for synchronous local clock, and has high priority, thereby make when FPGA receives this loopback frame information, this loopback frame information of priority treatment, obtain the timestamp information that wherein carries, and this loopback frame information can not abandoned, guaranteed that the FPGA acquisition time stabs the reliability of information.In addition, this loopback frame information can further include the length information and the check information of timestamp information.
If clock is adjusted reference information greater than local time stamp information, then main control unit will improve the local clock frequency; If clock is adjusted reference information less than local time stamp information, then main control unit will reduce the local clock frequency, thereby finish the adjustment of local clock.
In the present embodiment, NP can directly not receive the IP clock message that outside network device sends by FPGA.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.After NP obtained corresponding timestamp information, FPGA can send the timestamp information that comes according to NP and obtain clock adjustment reference information, carries out the clock adjustment thereby make things convenient for main control unit to adjust reference information according to this clock.And, because NP can support the IP clock information of various protocols encapsulation neatly by the microcode programming, therefore, adopt NP that the IP clock message that receives is resolved and to realize the heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
Fig. 5 is the flow chart of IP clock packet processing method the 4th embodiment of the present invention.In the method for present embodiment, NP both can receive the IP clock message that outside network device sends, obtain corresponding timestamp information, this timestamp information and local time stamp information can be compared again, obtain main control unit and carry out the used clock adjustment reference information of clock adjustment, and the timestamp information that gets access to need not be sent to FPGA, request FPGA obtains clock according to this timestamp information and adjusts reference information.As shown in Figure 5, the method for present embodiment comprises:
Specifically, NP can receive the IP clock message that outside network device sends, and this outside network device both can be the clock source device, also can be any one network element in the network.
Owing to all carry special udp port number in the IP clock message, so NP can number know that the message that receives is the IP clock message by this udp port.
NP can support the various protocols type by the microcode programming, and therefore, NP can discern the more IP clock message of multi-protocols encapsulation neatly.NP in the present embodiment is when resolving the IP clock message that receives, can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved according to this type of message with this type of message, thereby can support to be present in E1 T1 these complex protocols such as PPPMUX, MLPPP, IPHC and CRTP in this network environment of STM-1.And along with the more expansion of multi-protocols form, NP can support the protocol format of new expansion by the microcode programming.
The timestamp information that the IP clock message that NP receives by parsing obtains promptly can be used for the local clock information of each network element is carried out clock synchronization.
If clock is adjusted reference information greater than local time stamp information, then main control unit will improve the local clock frequency; If clock is adjusted reference information less than local time stamp information, then main control unit will reduce the local clock frequency, thereby finish the adjustment of local clock.
In the present embodiment, NP can replace all functions of FPGA, NP both can directly receive outside network device and send and next IP clock information, the timestamp information that carries in this IP clock information is obtained in parsing, can adjust reference information to obtain clock according to this timestamp information and local time stamp confidence again, thereby can notify main control unit to adjust reference information local clock information synchronously according to this clock.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.And, because NP can support the IP clock information of various protocols encapsulation neatly by the microcode programming, therefore, adopt NP that the IP clock message that receives is resolved and to realize the heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
Fig. 6 is the structural representation of IP clock message treatment facility first embodiment of the present invention, as shown in Figure 6, the equipment of present embodiment can comprise: first receiver module 11 and first processing module 12, wherein, first receiver module 11 be used to obtain NP adopt the analysis mode corresponding with the type of message of the IP clock message that receives to described IP clock message resolve acquisition, with this IP clock message time corresponding stamp information; First processing module 12 is used for according to this timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.
For instance, this first receiver module 11 and first processing module 12 can be the functional module among the FPGA, and that this first receiver module 11 can receive is that NP sends, this NP stabs information to what the IP clock message that receives was resolved acquisition with IP clock message time corresponding.Promptly first receiver module 11 in FPGA receives before the timestamp information, and NP can adopt corresponding analysis mode that this IP clock message is resolved according to the type of message of the IP clock message that receives.Because NP has extended capability flexibly, therefore along with the agreement that is used to encapsulate the IP clock message constantly develops, NP can programme by microcode and support more protocol type, thereby makes NP can discern the more IP clock message of multi-protocols encapsulation neatly.Therefore, NP in the present embodiment is when resolving the IP clock message that receives, can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved according to this type of message with this type of message, thereby can support to be present in E1 T1 these complex protocols such as PPPMUX, MLPPP, IPHC and CRTP in this network environment of STM-1.
NP can obtain the timestamp information that sends to first receiver module 1 among the FPGA by the IP clock message that parsing receives.
In the present embodiment, the timestamp information that first receiver module obtains is to obtain by adopting NP that the IP clock message that receives is resolved.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.Timestamp information and local time stamp information that second processing module can receive first receiver module compare, and obtain clock and adjust reference information, carry out the clock adjustment thereby make things convenient for main control unit to adjust reference information according to this clock.And, because NP can programme by microcode, support the IP clock message of various protocols encapsulation neatly, therefore, adopt NP that the IP clock message that receives is resolved the transmission that can realize the IP clock message between networks of different type, and the situation that the IP clock message can't be identified when across a network transmits can not appear, thus reach the effect of heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
Fig. 7 is the structural representation of IP clock message treatment facility second embodiment of the present invention, as shown in Figure 7, the equipment of present embodiment can comprise: first receiver module 11 and first processing module 12, wherein, first receiver module 11 be used to obtain NP adopt the analysis mode corresponding with the type of message of the IP clock message that receives to described IP clock message resolve acquisition, with this IP clock message time corresponding stamp information; First processing module 12 is used for according to this timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.Further, first receiver module 1 can comprise: first receiving element 111 and first resolution unit 112; First receiving element 111 is used to receive the loopback frame information that NP returns by SPI, and this loopback frame information comprises timestamp information, also comprises being used to identify the loopback frame sign that this timestamp information has high priority; First resolution unit 112 is used for obtaining according to this loopback frame sign the timestamp information of loopback frame information.
For instance, the IP clock message that NP receives can comprise: the IP clock message that the outside network device of being transmitted to NP by FPGA sends, perhaps outside network device is to the IP clock message of NP transmission.
Because NP has flexibility and extensibility, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore, the IP clock message that NP can encapsulate the various complex protocols that receive is resolved, obtain the timestamp information that carries in this IP clock message, NP can construct loopback frame information then, this timestamp information is carried in this loopback frame information, this loopback frame information also comprises the loopback frame sign, can identify this loopback frame information and comprise the timestamp information that is used for synchronous local clock, and has high priority, win receiving element 111 when receiving this loopback frame information thereby make, and this loopback frame information of priority treatment is obtained the timestamp information that wherein carries, and this loopback frame information can not abandoned, guaranteed that the FPGA acquisition time stabs the reliability of information.
Then, NP sends to first receiving element 111 by the SPI mouth with this loopback frame information.First receiving element 11 can send to the loopback frame information that receives first resolution unit 112.First resolution unit 112 can be resolved this loopback frame information, timestamp information and the local time stamp information that to obtain from this loopback frame information compare, obtain clock and adjust reference information, main control unit promptly can be adjusted reference information according to this clock local clock is adjusted.This first resolution unit 112 is obtained first processing module 12 among method that clock adjusts reference information and IP clock message treatment facility first embodiment of the present invention, and to obtain the method for clock adjustment reference information identical, repeats no more.
In the present embodiment, NP can resolve from the IP clock message that outside network device directly receives IP clock message or the NP that FPGA transmits.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.After obtaining corresponding timestamp information, NP can construct the loopback frame information of carrying this timestamp information, and this loopback frame information is sent to first receiving element by SPI, this first resolution unit can be obtained clock according to the timestamp information that carries in this loopback frame information and adjust reference information, carries out the clock adjustment thereby make things convenient for main control unit to adjust reference information according to this clock.In the present embodiment,, therefore adopt NP that the IP clock message that receives is resolved and to realize the heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration because NP can support the IP clock message of multiple complex protocol encapsulation.
Fig. 8 is the structural representation of network processing unit first embodiment of the present invention, as shown in Figure 8, the NP of present embodiment comprises: second receiver module 13, second parsing module 14 and second sending module 15, wherein, second receiver module 13 is used to receive the IP clock message that outside network device that FPGA transmits sends, or the IP clock message that sends of outside network device; Second parsing module 14 is used for the type of message of the IP clock message of definite described second receiver module reception, adopt the analysis mode corresponding that the IP clock message that second receiver module 13 receives is resolved, obtain to stab information with this IP clock message time corresponding with described type of message; Second sending module 15 is used for this timestamp information is sent to FPGA.
Specifically, the IP clock message that second receiver module 13 receives can comprise: what receive transmits the IP clock message that outside network device sends by FPGA, the IP clock message that the outside network device that perhaps receives directly sends to NP.
Because NP has flexibility and extensibility, therefore, the IP clock message that the various complex protocols that second parsing module 14 can adopt the analysis mode corresponding with the type of message of the IP clock message that receives that second receiver module 13 is received encapsulate is resolved, obtain the timestamp information that carries in this IP clock message, at last, second sending module 15 can send to FPGA with this timestamp information.This second sending module 15 can be structure loopback frame information with the process that this timestamp information sends to FPGA, this timestamp information is carried in this loopback frame information, this loopback frame information also comprises the loopback frame sign, can identify this loopback frame information and comprise the timestamp information that is used for synchronous local clock, and has high priority, thereby make FPGA when receiving this loopback frame information, this loopback frame information of priority treatment, obtain the timestamp information that wherein carries, and this loopback frame information can not abandoned, guaranteed that the FPGA acquisition time stabs the reliability of information.Then, second sending module 15 can send to FPGA with this loopback frame information by the SPI mouth.FPGA can compare according to timestamp information that carries in this loopback frame information and local time stamp information, obtains clock and adjusts reference information, and main control unit promptly can be adjusted reference information according to this clock local clock is adjusted.
In the present embodiment, because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message that second receiver module receives is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby make second parsing module can resolve the more IP clock message of multi-protocols encapsulation neatly, overcome the limitation of prior art when resolving the IP clock message.After obtaining corresponding timestamp information, second sending module can send to FPGA with this timestamp information, thereby make FPGA obtain clock and adjust reference information, carry out the clock adjustment thereby make things convenient for main control unit to adjust reference information according to this clock according to this timestamp information.The NP of present embodiment can support the IP clock message of multiple complex protocol encapsulation, thereby can realize the heterogeneous network compatibility under the different agreement, provides the basis of IP clock synchronization for further realizing the network integration.
Fig. 9 is the structural representation of network processing unit second embodiment of the present invention, as shown in Figure 9, the NP of present embodiment comprises: the 3rd parsing module 16 and the 3rd processing module 17, wherein, the 3rd parsing module 16 is used to receive the IP clock message, determine the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and this IP clock message time corresponding stamp information to the IP clock message; The 3rd processing module 17 is used for according to this timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.
NP in the present embodiment can replace all functions of FPGA fully, be that NP in the present embodiment both can receive the IP clock message that outside network device sends, obtain corresponding timestamp information, this timestamp information and local time stamp information can be compared again, obtain main control unit and carry out the used clock adjustment reference information of clock adjustment.
Specifically, the 3rd parsing module 16 can receive the IP clock message that outside network device sends, determine the type of message of this IP clock message then, and adopt the analysis mode corresponding that this IP clock message is resolved with this type of message, obtain to stab information with this IP clock message time corresponding.This outside network device both can be the clock source device, also can be any one network element in the network.
Owing to all carry special udp port number in the IP clock message, therefore the 3rd parsing module 16 can number know that the message that receives is the IP clock message by this udp port.
NP can support the various protocols type by the microcode programming, therefore, NP can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved with this type of message according to this type of message, thereby make the 3rd parsing module 16 can discern the more IP clock message of multi-protocols encapsulation neatly, as in the face of E1 T1 during this network environment of STM-1, the 3rd parsing module 16 can be resolved the IP clock message of these complex protocols encapsulation such as PPPMUX, MLPPP, IPHC and CRTP.And along with the more expansion of multi-protocols form, NP can support the protocol format of new expansion by the microcode programming.
Timestamp information and local time stamp information that the 3rd processing module 17 can be obtained according to the 3rd parsing module 16 are obtained main control unit and are carried out clock and adjust used clock and adjust reference information.
The NP of present embodiment can replace all functions of FPGA, NP both can directly receive outside network device and send and next IP clock information, the timestamp information that carries in this IP clock information is obtained in parsing, can adjust reference information to obtain clock according to this timestamp information and local time stamp confidence again, thereby can notify main control unit to adjust reference information local clock information synchronously according to this clock.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes the 3rd parsing module among the NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.And, because NP can support the IP clock information of various protocols encapsulation neatly by the microcode programming, therefore, the NP of employing present embodiment resolves the IP clock message that receives and can realize the heterogeneous network compatibility, provides the basis of IP clock synchronization for further realizing the network integration.
Figure 10 is the structural representation of IP clock message treatment system first embodiment of the present invention, as shown in figure 10, the system of present embodiment comprises: NP 1, IP clock message treatment facility 2 and main control unit 3, wherein, NP 1 receives the IP clock message, determine the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and this IP clock message time corresponding stamp information to the IP clock message that receives; IP clock message treatment facility 2 is used to receive the timestamp information that NP 1 sends, and according to this timestamp information and local time stamp information, obtains clock and adjusts used clock adjustment reference information; Main control unit 3 is used for adjusting reference information according to the clock that this IP clock message treatment facility 2 sends and carries out the clock adjustment.
Specifically, the IP clock message that NP 1 receives both can be transmitted the IP clock message that outside network device sends for IP clock message treatment facility 2, can be again the IP clock message that NP 1 directly receives from outside network device.NP 1 can resolve this IP clock message then.Because NP can support the various protocols type by the microcode programming, therefore, NP can discern the more IP clock message of multi-protocols encapsulation neatly.NP in the present embodiment is when resolving the IP clock message that receives, can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved according to this type of message with this type of message, thereby can support to be present in E1 T1 these complex protocols such as PPPMUX, MLPPP, IPHC and CRTP in this network environment of STM-1.And along with the more expansion of multi-protocols form, NP can support the protocol format of new expansion by the microcode programming.
NP 1 resolves after this IP clock message acquisition time stamp information, this timestamp information can be sent to IP clock message treatment facility 2.The method that NP 1 stabs information to IP clock message treatment facility 2 transmitting times can be structure loopback frame information, this timestamp information is carried in this loopback frame information, this loopback frame information also comprises the loopback frame sign, can identify this loopback frame information and comprise the timestamp information that is used for synchronous local clock, and has high priority, thereby make IP clock message treatment facility 2 when receiving this loopback frame information, this loopback frame information of priority treatment, obtain the timestamp information that wherein carries, and this loopback frame information can not abandoned, guaranteed that IP clock message treatment facility 2 acquisition times stab the reliability of information.Then, NP 1 can send to IP clock message treatment facility 2 with this loopback frame information by the SPI mouth.
IP clock message treatment facility 2 can be for having arbitrary logical block of computing function, such as FPGA.Timestamp information and local time stamp information that this IP clock message treatment facility 2 can come NP 1 transmission compare, and obtain clock and adjust reference information.
Main control unit 3 promptly can be adjusted reference information according to the clock that IP clock message treatment facility 2 sends local clock is adjusted, if clock is adjusted reference information greater than local time stamp information, then main control unit 3 will improve the local clock frequency; If clock is adjusted reference information less than local time stamp information, then main control unit 3 will reduce the local clock frequency, thereby finish the adjustment of local clock, realize the IP clock synchronization.
In the present embodiment, because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby make NP can resolve the more IP clock message of multi-protocols encapsulation neatly, overcome the limitation of prior art when resolving the IP clock message.After NP obtains corresponding timestamp information, IP clock message treatment facility only needs simply to calculate according to the timestamp information that NP sends and can obtain clock and adjust reference information, thereby makes things convenient for main control unit to carry out the local clock adjustment according to this clock adjustment reference information.The system of present embodiment can be set at as required and merge on the arbitrary network element that has in polytype network.Because NP can programme by microcode, support the IP clock message of various protocols encapsulation neatly, therefore, adopt NP that the IP clock message that receives is resolved the transmission that can realize the IP clock message between networks of different type, and the situation that the IP clock message can't be identified when across a network transmits can not appear, thereby reach the effect of heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
Figure 11 is the structural representation of IP clock message treatment system second embodiment of the present invention, as shown in figure 11, the system of present embodiment comprises: NP 1 and main control unit 3, wherein, NP 1 is used to receive the IP clock message, determine the type of message of described IP clock message, adopt the analysis mode corresponding that this IP clock message is resolved with described type of message, obtain to stab information with IP clock message time corresponding, and, obtain clock and adjust used clock adjustment reference information according to this timestamp information and local time stamp information; Main control unit 3 is used for adjusting reference information according to this clock and carries out the clock adjustment.
NP 1 in the present embodiment both can receive the IP clock message that outside network device sends, obtain corresponding timestamp information, this timestamp information and local time stamp information can be compared again, obtain main control unit 3 and carry out the used clock adjustment reference information of clock adjustment.
Specifically, NP 1 receives the IP clock message, can determine type of message according to this IP clock message then, and adopts the analysis mode corresponding with this type of message that this IP clock message is resolved, and obtains to stab information with this IP clock message time corresponding.This outside network device both can be the clock source device, also can be any one network element in the network.
Owing to all carry special udp port number in the IP clock message, so NP 1 can number know that the message that receives is the IP clock message by this udp port.
NP 1 can support the various protocols type by the microcode programming, and therefore, NP 1 can discern the more IP clock message of multi-protocols encapsulation neatly.NP 1 in the present embodiment is when resolving the IP clock message that receives, can determine the type of message of this IP clock message according to the IP clock message that receives, and adopt the analysis mode corresponding that this IP clock message is resolved according to this type of message with this type of message, thereby can support to be present in E1 T1 these complex protocols such as PPPMUX, MLPPP, IPHC and CRTP in this network environment of STM-1.And along with the more expansion of multi-protocols form, NP 1 can support the protocol format of new expansion by the microcode programming.
NP 1 can obtain clock and adjust used clock adjustment reference information according to this timestamp information and local time stamp information.At last, NP 1 can adjust reference information with this clock and send to main control unit 3, this main control unit 3 can be adjusted reference information according to this clock and regulate local clock, if clock is adjusted reference information less than local time stamp information, then main control unit 3 will reduce the local clock frequency, thereby finish the adjustment of local clock, realize the IP clock synchronization.
In the present embodiment, NP both can directly receive outside network device and send and next IP clock information, the timestamp information that carries in this IP clock information is obtained in parsing, can adjust reference information to obtain clock according to this timestamp information and local time stamp confidence again, thereby can notify main control unit to adjust reference information local clock information synchronously according to this clock.Because NP has extended capability flexibly, can determine new expansion, the type of message of the IP clock message of complex protocol encapsulation, and adopt corresponding analysis mode to resolve, therefore no matter the IP clock message is to adopt which kind of agreement to encapsulate, NP all can programme the wider protocol type of support scope by microcode, thereby makes NP can resolve the more IP clock message of multi-protocols encapsulation neatly, has overcome the limitation of prior art when resolving the IP clock message.The system of present embodiment can be set at as required and merge on the arbitrary network element that has in polytype network.Because NP can programme by microcode, support the IP clock message of various protocols encapsulation neatly, therefore, adopt NP that the IP clock message that receives is resolved the transmission that can realize the IP clock message between networks of different type, and the situation that the IP clock message can't be identified when across a network transmits can not appear, thereby reach the effect of heterogeneous network compatibility, provide the basis of IP clock synchronization for further realizing the network integration.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (12)
1. an IP clock packet processing method is characterized in that, comprising:
Obtain network processing unit adopt the analysis mode corresponding with the type of message of the IP clock message that receives to described IP clock message resolve acquisition, with described IP clock message time corresponding stamp information;
According to described timestamp information and local time stamp information, obtain main control unit and adjust the used clock adjustment reference information of described local time stamp information.
2. IP clock packet processing method according to claim 1 is characterized in that, described IP clock message comprises:
The IP clock message that the outside network device of being transmitted to described network processing unit by field programmable gate array sends; Or
The IP clock message that outside network device sends to described network processing unit.
3. IP clock packet processing method according to claim 2 is characterized in that, the IP clock message that the described outside network device of being transmitted to described network processing unit by field programmable gate array sends comprises:
With the received IP clock message of described network processing unit corresponding protocols message sink mouth.
4. according to claim 1 or 2 or 3 described IP clock packet processing methods, it is characterized in that, the described network processing unit that obtains adopts the analysis mode corresponding with the type of message of the IP clock message that receives that described IP clock message is resolved acquisition and described IP clock message time corresponding stamp information, comprising:
Receive the loopback frame information that described network processing unit returns by Serial Peripheral Interface, described loopback frame information comprises described timestamp information, also comprises being used to identify the loopback frame sign that described loopback frame information has high priority;
Identify the described timestamp information that obtains in the described loopback frame information according to described loopback frame.
5. IP clock packet processing method according to claim 4 is characterized in that, described loopback frame information also comprises the length information and the check information of described timestamp information.
6. an IP clock packet processing method is characterized in that, comprising:
Network processing unit receives the IP clock message, determines the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and described IP clock message time corresponding stamp information to described IP clock message;
Described network processing unit obtains main control unit and carries out the used clock adjustment reference information of clock adjustment according to described timestamp information and local time stamp information.
7. an IP clock message treatment facility is characterized in that, comprising:
First receiver module, be used to obtain network processing unit adopt the analysis mode corresponding with the type of message of the IP clock message that receives to described IP clock message resolve acquisition, with described IP clock message time corresponding stamp information;
First processing module is used for according to described timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.
8. IP clock message treatment facility according to claim 7 is characterized in that, described first receiver module comprises:
First receiving element is used to receive the loopback frame information that described network processing unit returns by Serial Peripheral Interface, and described loopback frame information comprises described timestamp information, also comprises being used to identify the loopback frame sign that described timestamp information has high priority;
First resolution unit is used for identifying the described timestamp information that obtains described loopback frame information according to described loopback frame.
9. a network processing unit is characterized in that, comprising:
Second receiver module is used to receive the IP clock message that outside network device that field programmable gate array transmits sends, or the IP clock message that sends of outside network device;
Second parsing module, the type of message of the IP clock message that is used for determining that described second receiver module receives adopts the analysis mode corresponding with described type of message that described IP clock message is resolved, and obtains and described IP clock message time corresponding stamp information;
Second sending module is used for described timestamp information is sent to described field programmable gate array.
10. a network processing unit is characterized in that, comprising:
The 3rd parsing module is used to receive the IP clock message, determines the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and described IP clock message time corresponding stamp information to described IP clock message;
The 3rd processing module is used for according to described timestamp information and local time stamp information, obtains main control unit and carries out the used clock adjustment reference information of clock adjustment.
11. an IP clock message treatment system is characterized in that, comprising:
Network processing unit, receive the IP clock message, determine the type of message of described IP clock message, and the employing analysis mode corresponding with described type of message resolved acquisition and described IP clock message time corresponding stamp information to the described IP clock message that receives;
IP clock message treatment facility is used to receive the described timestamp information that described network processing unit sends, and according to described timestamp information and local time stamp information, obtains clock and adjusts used clock adjustment reference information;
Main control unit is used for adjusting reference information according to the described clock that described IP clock message treatment facility sends and carries out the clock adjustment.
12. an IP clock message treatment system is characterized in that, comprising:
Network processing unit, be used to receive the IP clock message, determine the type of message of described IP clock message, adopt the analysis mode corresponding that described IP clock message is resolved with described type of message, obtain to stab information with described IP clock message time corresponding, and, obtain clock and adjust used clock adjustment reference information according to described timestamp information and local time stamp information;
Main control unit is used for adjusting reference information according to described clock and carries out the clock adjustment.
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| CN102377663A (en) * | 2010-08-24 | 2012-03-14 | 华为技术有限公司 | Method, device and system for processing clock message |
| CN102413017B (en) * | 2011-12-01 | 2018-06-12 | 中兴通讯股份有限公司 | Time-delay performance monitoring method and device |
| CN103560486B (en) * | 2013-11-07 | 2016-02-24 | 贵州电力试验研究院 | Be applicable to the voltage Phase-Locked Synchronous networking method of sampling of transformer differential protection |
| CN104461997B (en) * | 2014-11-26 | 2017-12-05 | 上海斐讯数据通信技术有限公司 | A kind of POS phy interfaces equipment and design method |
| CN114666205A (en) * | 2017-07-10 | 2022-06-24 | 比吉斯合伙人有限公司 | Network for packet monitoring and replay |
| CN110782709B (en) * | 2019-11-04 | 2020-11-03 | 四川九洲空管科技有限责任公司 | High-precision clock redundancy backup method for civil aviation ADS-B ground station system |
| CN113179441B (en) * | 2021-03-26 | 2023-06-30 | 卡莱特云科技股份有限公司 | Synchronous playing method, device, system and computer equipment |
| CN114138054A (en) * | 2021-10-14 | 2022-03-04 | 北京国科天迅科技有限公司 | Timestamp obtaining method and device, electronic equipment and storage medium |
| CN114629972B (en) * | 2022-03-21 | 2024-03-22 | 中国科学院计算机网络信息中心 | Data message processing method and device |
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