CN101453215A - Frequency synthesizer having multiple frequency locking circuits - Google Patents
Frequency synthesizer having multiple frequency locking circuits Download PDFInfo
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- CN101453215A CN101453215A CNA2007101962441A CN200710196244A CN101453215A CN 101453215 A CN101453215 A CN 101453215A CN A2007101962441 A CNA2007101962441 A CN A2007101962441A CN 200710196244 A CN200710196244 A CN 200710196244A CN 101453215 A CN101453215 A CN 101453215A
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- clock signal
- frequency
- circuit
- locking circuits
- lock
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Abstract
A frequency synthesizer comprises a plurality of frequency locking circuits, a selection circuit and a control circuit, wherein the frequency locking circuits are used for locking a plurality of clock signals respectively according to a plurality of reference clock signals and outputting the clock signals; the selection circuit is used for selecting a certain clock signal from the clock signals as an output clock signal, and a certain frequency locking circuit among the frequency locking circuits locks the certain clock signal; the control circuit controls the frequency locking circuits; moreover, when the selection circuit selects the certain clock signal as the output clock signal, the control circuit controls at least one frequency locking circuit among other frequency locking circuits except the certain frequency locking circuit, so as to lock another clock signal according to another reference clock signal at the same time.
Description
Technical field
The present invention relates to frequency synthesizer, particularly relate to a kind of frequency synthesizer with a plurality of frequency locking circuits.
Background technology
In general electronic system or circuit, need frequency synthesizer satisfying the synchronisation requirement of system usually, and frequency synthesizer have frequency locking circuits (as: phase-locked loop) usually so that specific signal is locked to characteristic frequency.Yet, along with the development of technology, the speed of system is quick day by day, so the lock speed of frequency locking circuits also more and more is much accounted of, but the lock speed of frequency locking circuits often is subject to the frequency of reference clock signal, and therefore the application in high-speed frequency hopping system is also therefore limited.
Fig. 1 shows the frequency synthesizer 100 in order to address the above problem in the prior art.As shown in Figure 1, this frequency synthesizer 100 comprises a N frequency locking circuits 102～106 (partly frequency locking circuits omits and do not draw) and a selection circuit 108.In N frequency locking circuits 102～106 each is respectively according to corresponding reference clock signal RCS
1, RCS
2... RCS
NLock corresponding clock signal CS
1, CS
2... CS
NExtremely with each reference clock signal RCS
1, RCS
2... RCS
NCorresponding characteristic frequency.According to required frequency, choice device 108 can be selected clock signal CS
1, CS
2... CS
NOne of them is as desired output clock signal OCS.
Yet, this type of circuit but has sizable shortcoming, that is exactly that each frequency locking circuits 102～106 only corresponds to a reference clock signal in operation, lack flexibility, and, if system needs more signals that are locked to different frequency more, then the area of this type of circuit is big more, thereby runs in the opposite direction with the gesture of driving of electronic system size microminiaturization now.Moreover, if the frequency locking circuits that is not used continues clock signal is locked to characteristic frequency always, will increase unnecessary power consumption and system burden.Therefore, just need a kind of mechanism of novelty to solve above-mentioned problem.
Summary of the invention
As mentioned above, one of purpose of the present invention is for providing a kind of frequency synthesizer, the setting-up time (Settling Time) that can utilize a plurality of locking frequency circuit to set (Settling) simultaneously to relax the locking frequency circuit, and reduce the consumption of power.
Another purpose of the present invention is for providing a kind of frequency synthesizer, and it is that a plurality of frequency locking circuits of control just lock signal when needed, to reduce power consumption and system burden.
Another purpose of the present invention is for providing a kind of frequency synthesizer, and its frequency locking circuits can corresponding more than one reference clock signal, with the elasticity that increases system and reduce circuit area.
The preferred embodiment of this case has disclosed a kind of frequency synthesizer, comprises a plurality of frequency locking circuits, selects circuit and control circuit.Frequency locking circuits is in order to lock a plurality of clock signals and to export described clock signal according to a plurality of reference clock signals respectively.Select circuit to be coupled to described frequency locking circuits, in order to select a specific clock signal as an output clock signal in described clock signal, the characteristic frequency lock-in circuit in the wherein said frequency locking circuits locks this specific clock signal.Control circuit is coupled to a plurality of frequency locking circuits to control described frequency locking circuits, wherein when this selections circuit select specific clock signal be used as exporting clock signal during, control circuit can control in other frequency locking circuits beyond the characteristic frequency lock-in circuit at least one frequency locking circuits come the while according to another reference clock signal to lock another clock signal.
In addition, this frequency synthesizer can also include a reference frequency generation module, in order to M reference clock signal of output, wherein the number of frequency locking circuits is N (N＜M), above-mentioned control circuit is coupled to the reference frequency generation module in addition in addition, uses from the reference clock signal of selecting to export to frequency locking circuits in M the reference clock signal.
Description of drawings
Fig. 1 is the function block schematic diagram of existing frequency synthesizer.
Fig. 2 is the function block schematic diagram of the frequency synthesizer of the first embodiment of the present invention.
Fig. 3 is the of the present invention second function block schematic diagram of executing the frequency synthesizer of example.
Fig. 4 is the function block schematic diagram of the frequency synthesizer of the third embodiment of the present invention.
Fig. 5 is the function block schematic diagram of the frequency synthesizer of the fourth embodiment of the present invention.
The reference numeral explanation
100,200,300,400,500 frequency synthesizers
102,104,106,404,406,408,504,506,508 frequency locking circuits
202,302,402,502 control circuits
204,304 first frequency lock-in circuits
206,306 second frequency lock-in circuits
208,308 the 3rd frequency locking circuits
108,210,310,410,510 select circuit
312,512 reference frequency generation modules
Embodiment
Fig. 2 shows the frequency synthesizer 200 according to the first embodiment of the present invention.As shown in Figure 2, this frequency synthesizer 200 has a control circuit 202, a first frequency lock-in circuit 204, a second frequency lock-in circuit 206, one the 3rd frequency locking circuits 208 and a selection circuit 210.First frequency lock-in circuit 204 is according to one first reference clock signal RCS
1Lock the first clock signal CS
1And export the first clock signal CS
1, second frequency lock-in circuit 206 is according to one second reference clock signal RCS
2Locking second clock signal CS
2And output second clock signal CS
2, the 3rd frequency locking circuits 208 is according to the 3rd reference clock signal RCS
3Lock the 3rd clock signal CS
3And export the 3rd clock signal CS
3 Select circuit 210 in order to select clock signal CS
1, CS
2And CS
3One of them is as an output clock signal OCS.Control circuit 202 is in order to control first frequency lock-in circuit 204, second frequency lock-in circuit 206 and the 3rd frequency locking circuits 208.In this embodiment, be with phase-locked loop (PhaseLocked Loop, PLL) come real working frequency lock-in circuit 204,206 and 208, come the real circuit 210 that elects with a multiplexer MUX, yet those skilled in the art can utilize other circuit to reach identical functions, also do not take off category of the present invention.
Choose the first clock signal CS at selection circuit 210
1During output clock signal OCS, second frequency lock-in circuit 206 is with second clock signal CS
2Be locked to the second reference clock signal RCS
2And the 3rd frequency locking circuits 208 is according to the 3rd reference clock signal RCS
3Operate; And select circuit 210 choose second clock signal CS2 for output clock signal OCS during, the 3rd frequency locking circuits 208 just is locked to the 3rd clock signal CS3 the 3rd reference clock signal RCS
3
In addition, each in the frequency locking circuits 204～208 can correspond to more than one reference clock signal in operation.For example, as the first clock signal CS
1Be locked to the first reference clock signal RCS
1And the first clock signal CS
1When being selected as output signal OCS, control circuit 202 control second frequency lock-in circuits 206 make second clock signal CS
2Be locked to the second reference clock signal RCS gradually
2As second clock signal CS
2Be locked to the second reference clock signal RCS
2After, system hops to the second reference clock signal RCS
2Frequency, and control circuit 202 control the 3rd frequency locking circuits 208 makes the 3rd clock signal CS
3Be locked to the 3rd reference clock signal RCS gradually
3As the 3rd clock signal CS
3Be locked to the 3rd reference clock signal RCS
3After, system hops to the second reference clock signal RCS
2Frequency, and control circuit 202 is also controlled first frequency lock-in circuit 204 and is made the first clock signal CS
1Be locked to frequency gradually and be different from the first reference clock signal RCS
1The 4th reference clock signal RCS
4By said method, can utilize same frequency locking circuits to be locked to different reference clock signals with its corresponding clock signal, can make system more flexible and significantly reduce circuit institute must area, and, by the mechanism that just starts frequency locking circuits when needed, can reduce the unnecessary power consumption and the burden of system.
It is noted that the operation of frequency synthesizer 200 does not need to observe fully above-mentioned operation.For example, when selecting circuit 210 to select the first clock signal CS
1During for output clock signal OCS, control circuit 202 can only be controlled second frequency lock-in circuit 206 and make second clock signal CS
2Be locked to the second reference clock signal RCS gradually
2, also can control second frequency lock-in circuit 206 simultaneously and the 3rd frequency locking circuits 208 makes second clock signal CS
2With the 3rd clock signal CS
3Be locked to the second reference clock signal RCS respectively gradually
2And the 3rd reference clock signal RCS
3That is to say, as a plurality of clock signal CS
1, CS
2, CS
3When one of them selected circuit 210 was chosen as output clock signal OCS, controller 202 will be controlled corresponding at least one gradually that it is corresponding clock signal in the frequency locking circuits of non-selected clock signal and be locked to the corresponding reference clock signal.And the number of its locking time and desire locking, visible system demand or user's needs and determining.
Fig. 3 shows frequency synthesizer 300 according to a second embodiment of the present invention.Be similar to above-mentioned frequency synthesizer 200, frequency synthesizer 300 also comprises control circuit 302, first frequency lock-in circuit 304, second frequency lock-in circuit 306, the 3rd frequency locking circuits 308 and selects circuit 310.Different being in frequency synthesizer 300 also has a reference frequency generation module 312, is used for exporting M reference clock signal RCS
1, RCS
2... RCS
M(M〉3).In this embodiment, control circuit 302 is except the operation of control first frequency lock-in circuit 304, second frequency lock-in circuit 306 and the 3rd frequency locking circuits 308, also in order to from M reference clock signal RCS
1, RCS
2... RCS
MThe middle reference clock signal of selecting to export to frequency locking circuits 304～308.Except reference frequency generation module 312, the mode of operation of frequency synthesizer 300 and said frequencies synthesizer 200 there is no too big-difference, so do not repeat them here.
It is noted that frequency synthesizer according to the present invention is not limited to only have three frequency locking circuits.Fig. 4 shows the frequency synthesizer 400 of a third embodiment in accordance with the invention.Frequency synthesizer 400 has a control circuit 402, a N frequency locking circuits 404～408 and selects circuit 410.The mode of operation of control circuit 402, frequency locking circuits 404～408 and selection circuit 410 is identical with second embodiment with above-mentioned first embodiment.That is to say, as a plurality of clock signal CS
1, CS
2... CS
NWhen one of them selected circuit 410 was chosen as output clock signal OCS, controller 402 will be controlled corresponding at least one gradually that it is corresponding clock signal in the frequency locking circuits of non-selected clock signal and be locked to the corresponding reference clock signal.And the clock signal number of its locking time and desire locking determines when visible system demand or user's needs.
Fig. 5 shows the frequency synthesizer 500 of a fourth embodiment in accordance with the invention.Be similar to frequency synthesizer 400, frequency synthesizer 500 has a control circuit 502, a N frequency locking circuits 504～508 and selects circuit 510.Unique different being in frequency synthesizer 500 also comprised a reference frequency generation module 512, in order to M reference clock signal RCS of output
1, RCS
2... RCS
M(M〉N), and control circuit 502 is except control frequency lock-in circuit 504～508 is more in order to from M reference clock signal RCS
1, RCS
2... RCS
MThe middle reference clock signal of selecting to export to frequency locking circuits 504～508.
If mode according to prior art, the time of staying of each locking frequency is tp, be ts blanking time, then according to enforcement of the present invention, set (Settling) simultaneously by a plurality of (for example: N) frequency locking circuits, then set the setting time limit ts that the time limit (Settling Time) can be when only using a frequency locking circuits, relax for ts+ (N-1) (tp+ts), and as prior art, need a plurality of interchangers (Switch) to switch a plurality of frequency locking circuits, and reduce the consumption of power.
Note that in the application's specification and claim has used some vocabulary to censure specific assembly.Those skilled in the art should understand, and hardware manufacturer may be called same assembly with different nouns.This specification and and claim in be not used as distinguishing the mode of assembly, but the criterion that is used as distinguishing with the difference of assembly on function with the difference of title.In the whole text specification and and claim in mentioned " comprising " be an open term, so should be construed to " comprise but be not limited to ".In addition, " couple " speech and comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to one second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other device or connection means if describe one first device in the literary composition.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. frequency synthesizer comprises:
A plurality of frequency locking circuits are in order to lock a plurality of clock signals and to export described clock signal according to a plurality of reference clock signals respectively;
One selects circuit, is coupled to described frequency locking circuits, and in order to select a specific clock signal as an output clock signal in described clock signal, the characteristic frequency lock-in circuit in the wherein said frequency locking circuits locks this specific clock signal; And
One control circuit, be coupled to these a plurality of frequency locking circuits to control described frequency locking circuits, wherein when this selections circuit select this specific clock signal be used as this output clock signal during, this control circuit can control in other described frequency locking circuits beyond this characteristic frequency lock-in circuit at least one frequency locking circuits while according to another reference clock signal to lock another clock signal.
2. frequency synthesizer as claimed in claim 1, wherein said frequency locking circuits are the phase-locked loop.
3. frequency synthesizer as claimed in claim 1, it also includes a reference frequency generation module, is used for exporting described reference clock signal.
4. frequency synthesizer as claimed in claim 3, the number of wherein said frequency locking circuits is not more than the number of described reference clock signal.
5. frequency synthesizer as claimed in claim 3, wherein this control circuit is coupled to this reference frequency generation module, uses from least one specific reference clock signal of selecting to export to described frequency locking circuits in the described reference clock signal.
6. frequency synthesizer as claimed in claim 1, wherein this frequency synthesizer is exported one first clock signal, a second clock signal and one the 3rd clock signal in regular turn, and described frequency locking circuits comprises:
One first frequency lock-in circuit is in order to lock this first clock signal and to export this first clock signal according to one first reference clock signal;
One second frequency lock-in circuit is in order to lock this second clock signal and to export this second clock signal according to one second reference clock signal; And
One the 3rd frequency locking circuits is in order to lock the 3rd clock signal and to export the 3rd clock signal according to one the 3rd reference clock signal.
7. frequency synthesizer as claimed in claim 6, wherein this selection circuit choose this first clock signal for this output clock signal during, this second frequency lock-in circuit is locked to this second reference clock signal with this second clock signal, and the 3rd frequency locking circuits operates according to the 3rd reference clock signal.
8. frequency synthesizer as claimed in claim 7, wherein this selection circuit choose this second clock signal for this output clock signal during, the 3rd frequency locking circuits is locked to the 3rd reference clock signal with the 3rd clock signal.
9. frequency synthesizer as claimed in claim 6, wherein this frequency synthesizer is output one the 4th clock signal behind the 3rd clock signal, and after this selection circuit was selected should export clock signal and switched to this second reference clock signal from this first reference clock signal, this first frequency lock-in circuit was understood foundation one the 4th reference clock signal that should the 4th clock signal is operated.
10. frequency synthesizer as claimed in claim 1, wherein this selection circuit is a multiplexer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101962441A CN101453215A (en) | 2007-11-30 | 2007-11-30 | Frequency synthesizer having multiple frequency locking circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101962441A CN101453215A (en) | 2007-11-30 | 2007-11-30 | Frequency synthesizer having multiple frequency locking circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101453215A true CN101453215A (en) | 2009-06-10 |
Family
ID=40735269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101962441A Pending CN101453215A (en) | 2007-11-30 | 2007-11-30 | Frequency synthesizer having multiple frequency locking circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101453215A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751982A (en) * | 2012-07-11 | 2012-10-24 | 烽火通信科技股份有限公司 | Clock selection circuit suitable for backboard spending treatment of communication equipment |
| CN105141309A (en) * | 2015-09-24 | 2015-12-09 | 山东大学 | Phase-locked loop rapid locking circuit used for frequency hopping communication and operation method thereof |
-
2007
- 2007-11-30 CN CNA2007101962441A patent/CN101453215A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751982A (en) * | 2012-07-11 | 2012-10-24 | 烽火通信科技股份有限公司 | Clock selection circuit suitable for backboard spending treatment of communication equipment |
| CN102751982B (en) * | 2012-07-11 | 2014-10-29 | 烽火通信科技股份有限公司 | Clock selection circuit suitable for backboard spending treatment of communication equipment |
| CN105141309A (en) * | 2015-09-24 | 2015-12-09 | 山东大学 | Phase-locked loop rapid locking circuit used for frequency hopping communication and operation method thereof |
| CN105141309B (en) * | 2015-09-24 | 2017-11-14 | 山东大学 | A kind of phase locked loop fast lock circuit and its operation method for frequency hopping communications |
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Application publication date: 20090610 |