CN101452215A - Control method for key dimension - Google Patents
Control method for key dimension Download PDFInfo
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- CN101452215A CN101452215A CNA2007101716127A CN200710171612A CN101452215A CN 101452215 A CN101452215 A CN 101452215A CN A2007101716127 A CNA2007101716127 A CN A2007101716127A CN 200710171612 A CN200710171612 A CN 200710171612A CN 101452215 A CN101452215 A CN 101452215A
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Abstract
The invention discloses a control method for a key size, which relates to the photolithographic process in the field of semiconductor. The control method comprises the following steps: providing a plurality of control pieces, and forming simulated substrates on the surfaces of the control pieces; coating chemical amplification photoresist on the simulated substrates of the control pieces, and carrying out exposure; carrying out the step of development; after the development, measuring the key size for the control pieces, and setting the measured size as a reference size; placing the control pieces in an environment in which wafers are produced and the storage and the transfer are the same for different time; and measuring the key size of the control pieces which are stored for different time, and establishing a coincidence relation curve of the key size and the storage time. The storage time corresponding to the part of the curve between the reference size and the maximum qualified size for producing the wafers is the safe storage time for producing the wafers. The control method finds out the safe storage time of the wafers through the coincidence relation between the key size after the development and the storage time. The control method has a shorter cycle and improves the production efficiency and ensures the yield of good products.
Description
Technical field
The present invention relates to the photoetching process of semiconductor applications, specifically, relate to a kind of control method of the critical size to wafer.
Background technology
Along with the continuous development of semiconductor technology, release the wafer of high-end designs, as the wafer of 0.18um-90nm and following technology generation with rapid changepl. never-ending changes and improvementsly.(Critical Diameter, requirement CD) in the photoetching process that carry out in the gold-tinted zone of semiconductor fabrication factory, are usually adopted chemical amplification photoresist (Chemical amplified Resist) in order to satisfy critical size.Chemical amplification photoresist H after exposure
+Reactant be developed liquid and develop to fall, become the critical size of requirement.But, owing to have NH in the environment of manufacturing works
4 +, SO
4 2-Plasma, characteristic can change when the chemical amplification photoresist was deposited under such environment, and the resting period is long more, influence big more to the critical size of inspecting (ADI) wafer after the follow-up development, and then cause inspecting after the etching variation of the critical size of (AEI) wafer, finally cause the decline of wafer yield rate.Therefore, the control method that needs a kind of critical size exceeds maximum permissible value to find out the safe wafer resting period with the critical size of avoiding obtaining.
At present, relatively the control method of critical size commonly used is to control the resting period of wafer by the corresponding relation of yield rate and resting period.That is to say that yield rate will be arranged earlier, could select control to the resting period, the cycle of this method is long.For large batch of wafer production, can not have much impact, but the wafer production of corresponding short run is unfavorable for enhancing productivity.
Summary of the invention
In view of this, the technical matters that the present invention solves provides a kind of control method of critical size, and it can find out the safe storage time of wafer effectively, in time.
For solving the problems of the technologies described above, the invention provides a kind of control method of new critical size.This control method comprises the steps: to provide several control sheets that use for test, forms one deck simulation substrate on control sheet surface; On control sheet simulation substrate, be coated with one deck chemical amplification photoresist, expose, and the exposure figure that needs on exposure figure and the production wafer is identical; Carry out development step then; After the development, the control sheet is carried out the measurement of critical size, mensuration is of a size of reference dimension; Described control sheet is placed on depositing of production wafer transmits in the identical environment, place the different resting periods respectively; Measure critical size through the control sheet after the described different resting periods, be made into the corresponding relation curve of critical size and resting period, the resting period of the part correspondence of this corresponding relation curve between the maximum qualified size of reference dimension and production wafer promptly is the safe storage time of producing wafer.
Compared with prior art, control method provided by the invention is found out resting period of security wafer by develop back critical size and the corresponding relation of resting period, and the cycle is shorter, has improved production efficiency and assurance good product yield rate.
Description of drawings
Fig. 1 is the critical size of the wafer that the present invention relates to and the corresponding relation figure of resting period.
Fig. 2 is the process flow diagram of control method of the present invention.
Embodiment
Below control method one embodiment of the critical size of wafer of the present invention is described in conjunction with the accompanying drawings, in the hope of further understanding purpose of the present invention, specific structural features and advantage.
See also Fig. 1 and Fig. 2, control method provided by the invention is found out the safe storage time of wafer by develop back critical size and the corresponding relation of resting period, concrete steps progressively are described below, the wafer that actual production is herein used is called the production wafer, and the wafer that test is used is called control sheet (control wafer).
S100: several control sheets at first are provided, adopt the method for chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form thin film as the simulation substrate on control sheet surface; This simulation substrate can be the resistant layer of titanium nitride (TiN), medium anti-reflecting layer (DARC), bottom reflector (BARC) or other materials identical with the etched material layers of needs of producing wafer, and thickness that should the simulation substrate is roughly the same with the thickness of the material layers of producing wafer.
S200: the surface at control sheet simulation substrate is coated with last layer chemical amplification photoresist, exposes, and wherein the exposure figure that needs on the exposure figure on all control sheets and the production wafer is identical; Carry out development step then.
S300: after the development, the control sheet is carried out the measurement of critical size for the first time, the dimension definitions of this measurement is a reference dimension, i.e. reference dimension line 1 among Fig. 1; In addition, the dimension line among Fig. 1 is a qualified size line 2 of producing the critical size of wafer, that is to say that the critical size that is positioned at reference dimension line 1 and qualified size line 2 all satisfies technological requirement.
S400: above-mentioned control sheet is placed in the wafer carrying magazine (cassette pod), place it in the yellow light area (promptly transmitting identical environment) of wafer manufacturing works with depositing of production wafer, place respectively the different resting periods then, 1hrs as shown in fig. 1 (hour), 2hrs, 4hrs, 8hrs, 12hrs, 18hrs, 24hrs etc.
S500: measure above-mentioned critical size, be made into the corresponding relation curve of critical size and resting period, curve 4 as shown in Figure 1 through the control sheet after the different resting periods; Described corresponding relation curve corresponding resting period of part between reference dimension and qualified size is exactly the safe storage time of producing wafer.As shown in fig. 1, the part of corresponding relation curve 4 between reference dimension line 1 and qualified size line 2, just the resting period of the part correspondence on straight line 3 left sides all is the safe storage time.
Claims (3)
1. the control method of a critical size, is characterized in that described control method comprises the steps: at the safe storage time that is used to obtain to produce wafer
Several control sheets that uses for test are provided, form one deck simulation substrate on control sheet surface;
On control sheet simulation substrate, be coated with one deck chemical amplification photoresist, expose, and the exposure figure that needs on exposure figure and the production wafer is identical;
Carry out development step then;
After the development, the control sheet is carried out the measurement of critical size, mensuration is of a size of reference dimension;
Described control sheet is placed on depositing of production wafer transmits in the identical environment, place the different resting periods respectively;
Measure critical size through the control sheet after the described different resting periods, be made into the corresponding relation curve of critical size and resting period, the resting period of the part correspondence of this corresponding relation curve between the maximum qualified size of reference dimension and production wafer promptly is the safe storage time of producing wafer.
2. the control method of critical size as claimed in claim 1 is characterized in that: the step of described formation simulation substrate is: adopt chemical vapor deposition or physical gas-phase deposite method depositing titanium nitride or medium anti-reflecting layer or bottom reflector as the simulation substrate.
3. the control method of critical size as claimed in claim 1 is characterized in that: need the thickness of etched material layers identical with material on the thickness of described formation simulation substrate and material and the production wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101716127A CN101452215B (en) | 2007-11-30 | 2007-11-30 | Control method for key dimension |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101716127A CN101452215B (en) | 2007-11-30 | 2007-11-30 | Control method for key dimension |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101452215A true CN101452215A (en) | 2009-06-10 |
| CN101452215B CN101452215B (en) | 2010-10-20 |
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ID=40734522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101716127A Expired - Fee Related CN101452215B (en) | 2007-11-30 | 2007-11-30 | Control method for key dimension |
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| CN (1) | CN101452215B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872127A (en) * | 2010-05-28 | 2010-10-27 | 上海宏力半导体制造有限公司 | Method for making relation curve of photoresist thickness and critical dimension |
| CN102437020A (en) * | 2011-11-24 | 2012-05-02 | 上海宏力半导体制造有限公司 | Wafer control wafer and forming method thereof |
| CN102023486B (en) * | 2009-09-09 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring key size swing curve of photo-etching technique |
| CN110928149A (en) * | 2018-09-20 | 2020-03-27 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
| CN115101509A (en) * | 2022-08-25 | 2022-09-23 | 合肥新晶集成电路有限公司 | Wafer structure and chip yield detection method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5926690A (en) * | 1997-05-28 | 1999-07-20 | Advanced Micro Devices, Inc. | Run-to-run control process for controlling critical dimensions |
| US7482178B2 (en) * | 2003-08-06 | 2009-01-27 | Applied Materials, Inc. | Chamber stability monitoring using an integrated metrology tool |
-
2007
- 2007-11-30 CN CN2007101716127A patent/CN101452215B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102023486B (en) * | 2009-09-09 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring key size swing curve of photo-etching technique |
| CN101872127A (en) * | 2010-05-28 | 2010-10-27 | 上海宏力半导体制造有限公司 | Method for making relation curve of photoresist thickness and critical dimension |
| CN102437020A (en) * | 2011-11-24 | 2012-05-02 | 上海宏力半导体制造有限公司 | Wafer control wafer and forming method thereof |
| CN102437020B (en) * | 2011-11-24 | 2016-01-27 | 上海华虹宏力半导体制造有限公司 | Wafer control slice and forming method thereof |
| CN110928149A (en) * | 2018-09-20 | 2020-03-27 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
| CN110928149B (en) * | 2018-09-20 | 2024-04-19 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
| CN115101509A (en) * | 2022-08-25 | 2022-09-23 | 合肥新晶集成电路有限公司 | Wafer structure and chip yield detection method |
| CN115101509B (en) * | 2022-08-25 | 2022-11-11 | 合肥新晶集成电路有限公司 | Wafer structure and chip yield detection method |
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| Publication number | Publication date |
|---|---|
| CN101452215B (en) | 2010-10-20 |
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Granted publication date: 20101020 Termination date: 20181130 |