CN101447336A - Complex laminated chip element - Google Patents

Complex laminated chip element Download PDF

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Publication number
CN101447336A
CN101447336A CNA2008101809357A CN200810180935A CN101447336A CN 101447336 A CN101447336 A CN 101447336A CN A2008101809357 A CNA2008101809357 A CN A2008101809357A CN 200810180935 A CN200810180935 A CN 200810180935A CN 101447336 A CN101447336 A CN 101447336A
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China
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aforementioned
conductive pattern
pattern layer
circuit board
coupling
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CNA2008101809357A
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CN101447336B (en
Inventor
朴寅吉
黄舜夏
金德熙
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Moda Innochips Co Ltd
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Priority claimed from KR1020030052562A external-priority patent/KR100470116B1/en
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Publication of CN101447336B publication Critical patent/CN101447336B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

The present invention relates to a laminated chip element which can be manufactured to have desired electric properties by combining various elements in accordance with the desired objectives. More particularly, the present invention relates to a laminated chip element which has superior high frequency properties and can be manufactured to control capacitance and/or inductance of the laminated chip element to a desired value. There is provided a laminated chip element, comprising at least one first sheet on which first and second conductive patterns are formed, the first and second conductive patterns being spaced apart from each other in a direction of both ends of the first sheet; and at least one second sheet on which a third conductive pattern is formed, the third conductive pattern being formed in a transverse direction of both the ends of the first sheet; wherein one ends of the first and second conductive patterns are connected to the first and second external terminals, respectively, at least one end of the third conductive pattern is connected to a third external terminal, and the first and second sheets are laminated. There is also provided a laminated chip element, comprising: at least one first sheet on which a conductive pattern is formed, the first conductive pattern consisting of first and third portions, the first and second portions being spaced apart from each other in a direction of both ends of the first sheet, the second portion connecting the first and second portions to each other to have a predetermined inductance; and at least one second sheet on which a conductive pattern is formed in a transverse direction of both the ends of the first sheet; wherein the first and second portions are connected to the first and second external terminals, respectively, at least one ends of the second conductive pattern is connected to a third external terminal, and the first and second sheets are laminated.

Description

Complex laminated chip element
The application is original application application number 2004800217963 (international application no PCT/KR2004/001759), and on July 15 2004 applying date, denomination of invention is divided an application for " complex laminated chip element ".
Technical field
The present invention relates to require by produce the laminated chip element of expectation electrical property in conjunction with different elements according to the expection of target.Say that more specifically the present invention makes it reach desired value about the making of the laminated chip element with good high frequency property and electric capacity and induction coefficient how to control laminated chip element.The present invention also relates to not be subjected to the influence of overvoltage and static environment to guarantee semiconductor integrated circuit and main electronic component by making laminated chip element in conjunction with passive components such as rheostat, resistor and transducers.
Background technology
In electronic circuit, resistor (R), capacitor (C) and transducer (L) all are typical passive components, and their performance and effect have nothing in common with each other.
Resistor plays a part Control current in circuit, and it also plays a part impedance matching in alternating current circuit; It is galvanic by allowing alternating current to pass through that capacitor then has prevention, and in addition, capacitor also can be used for playing a part filter out noise in time constant circuit, delay circuit and RC and the LC filter circuit; Transducer can be made various filters in conjunction with capacitor.This type of filter can filter out noise or the signal of certain frequency of shade selectively, and the signal of other frequencies then can pass through fully.
In general, because rheostat can change resistance according to the difference of voltage, so it is at the main electronic component of protection and circuit is exempted from be widely used aspect the influence of overvoltage and static environment.Electric current is under normal condition and without rheostat; but when overvoltage surpasses preset value; as " thunder and lightning " moment or similarly form by rheostatic two terminals; the very fast decline of rheostatic resistance; therefore, thus exhausted most electric current has protected circuit to exempt from the influence of overvoltage by rheostat without any current flowing to other elements.Consider the trend of present electronic instrument microminiaturization, this type of rheostat also trends towards microminiaturization, matrixing exempts from the influence of static and overvoltage to guarantee large-scale integrated circuit.
In addition, rheostat also has the effect of capacitor under the non-existent normal condition of overvoltage.Capacitor has character like this: have only when curtage when independently changing between the electrode, just allow signal to pass through.But capacitor also not only has electric capacity that the interference inductance is also arranged.Identical with it, transducer is not that inductance is only arranged yet, and also there is interference capacitors in it, and it also can stop the change of electric current in the lead.This shows that under the frequency of estimating was self resonance frequency, the function of element can change.
The rheostat that employing is combined with resistor can be guaranteed the stable operation of electronic equipment, be not subjected to the influence of overvoltage because main electronic component or circuit can both be protected effectively, and noise will be removed also.
When overvoltage no longer exists, can bring into play the effect of the capacitor that is combined with resistor in conjunction with the rheostat of resistor.In addition, the rheostat that is combined with transducer can be formed pi type filter (containing capacitor and transducer), and it has the excellent properties of removing high frequency noise.Under overvoltage was present in situation in the circuit, the rheostat that has the rheostat of resistor or have a transducer still had rheostatic function, and it can protective circuit exempt from overcurrent.Usually, the appropriate combination of typical passive component such as resistor, transducer and capacitor can play good impedance matching, leach high frequency or low frequency noise and the effect of filter menu one signal in certain band frequency scope in circuit.
If passive component is connected the modular elements that forms in the electronic circuit by lead, because of ampere wires generally can extend, so the size of polyphone inductance and resistance changes along with the length of lead.Therefore avoid high-frequency current to flow usually, and because the electric energy loss of each element, insertion loss also will take place.As above-mentioned reason, complex laminated chip element can produce by the combination different elements.
Figure 35 is a flow chart of making complex laminated chip element according to prior art, is that four capacitor elements are combined as an one chip element at this.Figure 36 and 37 is respectively the cutaway view and the plane graph of traditional laminated chip element.According to Figure 35, four first conductive pattern layer 1410 are arranged parallel to each other on first circuit board 1401, and each first conductive pattern layer head and the tail is relatively arranged.Two tail ends of each first conductive pattern layer 1410 in the first circuit board 1401 extend to respectively and are connected with second coupling with first coupling 1430, and it is respectively as input, out splice going splice.The second circuit board 1402 that is equipped with second conductive pattern layer 1411 is positioned on first conductive pattern layer 1410, and two tail ends of second circuit board 1402 extend to the 3rd coupling 1432 and are connected, and it is as earth terminal.Stacked and compress after the chip, laminated sheet is cut into suitable size, again with its hot pressing, each chip all has been made into an element body like this.Shown in Figure 35 (b), first, second conductive pattern layer 1410 and 1411 that must form element body is so that the two ends of first, second conductive pattern layer 1410 and 1411 can be exposed to the outer surface of element body.Shown in Figure 35 of institute (c), form first, second, third coupling 1430,1431 and 1432 at the outer surface of element body, with coupling respectively with corresponding first, second conductive layer 1410 with after 1411 tail end is connected, chip component is assembled and is finished.Meanwhile, adopt unit elements of dotted line (two point dotted line) boundary expression in the drawings.
The chip component B-B face cutaway view that Figure 36 gets for adopting production process shown in Figure 35, Figure 37 is the chip component plane graph after finishing.When applying voltage, capacitor is the electronic component as store charge, and it generally separates the electrode that insulate by two by dielectric medium and forms.As shown in figure 36, first, second conductive pattern layer 1410 and 1411 sees through a wiring board and separate; As shown in figure 37, first conductive pattern layer 1410 overlaps on second conductive pattern layer 1411 by an overlay segment 1440, and its electric capacity is directly proportional with the area of overlay segment 1440 and is inversely proportional to the thickness of wiring board.
Laminated chip element can be represented with the equivalent circuit diagram as Figure 38.Different with the two ends laminated chip, the laminated chip shown in Figure 35 to 38 has a special built-in electrode structure, and wherein flowing the electric current crosscut in first and second conductive pattern layer is 90 degree each other, and it is exactly so-called feedthrough capacitor.
Figure 39 has showed that respectively three end feedthrough capacitors are as low pass filter (a) and the ordinary capacitor frequency characteristic curve diagram as low pass filter (b).As shown in the figure, compare with ordinary capacitor, feedthrough capacitor has higher self resonance frequency.Because all input/output terminals and earth terminal are within the one chip element fully, so can obtain high insertion loss with respect to high frequency noise.Therefore in fact, three end punching laminated chip elements are used in electronic circuit widely.
Yet, traditional laminated chip element is obtaining good impedance matching, removing high/low frequency noise and is selecting the aspect of performance of single signal etc. unsatisfactory in particular frequency range, and the electric capacity, resistance and the inductance that seek out desired value concerning the user also are not easy.Therefore, be fit to require also have certain difficulty aspect the element of frequency characteristic in making.
In addition, because the production process of traditional laminated chip element itself is just very complicated and difficult, the one chip of making compound chip and a plurality of unit elements being integrated into arranged by the combination different elements is difficulty and complicated more just.
Summary of the invention
Make the problem that exists in the correlation technique in order to solve laminated chip element, one of purpose of the present invention is for making a kind of laminated chip element with good frequency characteristic (as denoising sound, low insertion loss or the like).
A further object of the present invention is for making a kind of laminated chip element that can obtain electric capacity, resistance and the inductance of desired value according to the re-set target of element.
Another object of the present invention is for making a kind of laminated chip element that can protect main electronic component such as semiconductor integrated circuit not to be subjected to overvoltage and static environmental impact.
Another purpose of the present invention is for making a kind of laminated chip element, thereby and is that the method that the one chip sheet need not additional process is simplified its production process most by adopting arranged with a plurality of demand elements combination.
Purpose according to the present invention, provide a lamination chip component to comprise, at least one be formed with first wiring board (first, second conductive layer is upwards separate in the footpath of two tail ends of first wiring board) of first, second conductive layer and second wiring board that at least one has the 3rd conductive layer (the 3rd conductive layer is positioned at first wiring board, two tail ends transversely, one of first, second conductive layer end is connected with first, second coupling respectively and one of at least the three conductive layer hold be connected with the 3rd coupling); Wherein first, second wiring board is laminated to each other.
Another target that will reach according to the present invention, provide a lamination chip component to comprise, at least one be formed with first wiring board (first, second conductive layer is upwards separate in the footpath of two tail ends of first wiring board) of first, second conductive layer and second wiring board that at least one has the 3rd conductive layer (the 3rd conductive layer is positioned at first wiring board, two tail ends transversely, one of first, second conductive layer end be connected with first, second coupling respectively and two opposite ends of first, second joint of the 3rd conductive layer respectively with the 3rd, all round joint be connected); Wherein first, second wiring board is laminated to each other.
First, second wiring board each other can be alternately laminated.And can be stacked and adjacent between two second wiring boards.
Another purpose according to the present invention, provide a lamination chip component to comprise, at least one is formed with first wiring board of first conductive layer, and being formed at the first wiring board two-end-point, first conductive layer directly makes progress, at least one is formed with second wiring board of second conductive layer, second conductive layer is formed at the direction identical with first conductive layer, and at least one is formed with the tertiary circuit plate of the 3rd conductive layer, the 3rd conductive layer is formed at first wiring board, two ends transversely, and wherein first, one of second conductive layer end is respectively with first, one of second coupling connection and at least the three conductive layer end is connected with the 3rd coupling.First is folded to the tertiary circuit flaggy.
Two second wiring boards can be laminated to each other and be adjacent.Preferable, laminated chip element should comprise that also at least one is formed with second wiring board of second conductive layer, and second conductive layer is formed at first conductive layer and directly makes progress, and wherein an end of second conductive layer is connected with second coupling.First can be stacked to the tertiary circuit plate, and makes the one or more tertiary circuit plates can be between first and second wiring boards.
According to another object of the present invention, one lamination chip component is provided, comprise that at least one is formed with first wiring board of first conductive layer, and being formed at the first wiring board two-end-point, first conductive layer directly makes progress, at least one is formed with second wiring board of second conductive layer, second conductive layer is formed at the direction identical with first conductive layer, at least one is formed with the tertiary circuit plate of the 3rd conductive layer, the 3rd conductive layer is formed at first wiring board, two ends transversely, and at least one is formed with the 4th wiring board of the 4th conductive layer, the 4th conductive layer is formed at the direction identical with the 3rd conductive layer, wherein two of first and second conductive layers opposite ends are respectively with first, second coupling connects, and the 3rd, two anti-phase ends of the 4th conductive layer are respectively with the 3rd, joint connection all round.First to fourth wiring board is stacked.
Third and fourth wiring board can be between first and second wiring boards.
According to another object of the present invention, one lamination chip component is provided, comprise that at least one is formed with first wiring board of first conductive layer, and being formed at the first wiring board two-end-point, first conductive layer directly makes progress, at least one is formed with second wiring board of second conductive layer, second conductive layer is formed at the direction identical with first conductive layer, and at least one is formed with the tertiary circuit plate of the 3rd conductive layer, the 3rd conductive layer is formed at the direction identical with first conductive layer, wherein two of first and second conductive layers opposite ends are respectively with first, second coupling connects, and an end of the 3rd conductive layer is connected with the 3rd coupling respectively.First is folded to the tertiary circuit flaggy.
The ground floor pressing plate is made up of two first wiring boards and the tertiary circuit plate that is embedded between two first wiring boards, and second layer laminated sheet is made up of two second wiring boards and the tertiary circuit plate that is embedded between two second wiring boards.First and second is pressing plate lamination each other layer by layer.One or more tertiary circuit plates can be between first and second wiring boards.
The purpose one of according to the present invention, one lamination chip component is provided, comprise that at least one has first wiring board of first conductive layer, wherein first conductive layer is made up of first to the 3rd section institute, first, second section is upwards separate in the footpath of two tail ends of first wiring board, separates with first, second section and is positioned at first wiring board, two ends transversely for the 3rd section; Second wiring board of at least one tool second conductive layer, wherein second conductive layer is formed by the 4th, the 5th section, the 4th section overlapping with first, the 3rd section part, the 5th section overlapping with second, third section part, and one of first, second section end is connected with first, second coupling respectively, one of at least the three section end is connected with the 3rd coupling, and first, second wiring board is stacked.First and second wiring boards can alternately be laminated to each other.
In the laminated chip element formerly, the overlay segment area between conductive layer each other can be different.
In the laminated chip element formerly, under the preferable situation, the resistance pattern layer is positioned on the laminated chip element, and two ends of resistance pattern layer are connected with first, second coupling respectively.In such cases, can form two metallic gaskets and isolate mutually each other, and form the resistance pattern layer so that two metallic gaskets are coupled together.In addition, the top layer at the lamination wiring board also can form an insulating pattern or layer.The resistance pattern layer generally comprises resistance material such as nickel-chromium (Ni-Cr) or ruthenium-oxide (RuO 2).Perhaps, chip component (according to the front introduction) comprises that also at least one is formed with the resistor wiring board of resistance pattern layer, wherein has a resistor wiring board at least through stacked.
In the laminated chip element formerly, under the preferable situation, on laminated chip element the inductive patterns layer must be installed, the two-end-point of inductive patterns layer is connected with first, second coupling respectively.Under the better situation, the inductive patterns layer should be spiral, and an insulative bridge is arranged on the root direction of principal axis of spiral type inductive patterns layer, and a bridge patterned layer extends to its outside from the center-side of inductive patterns layer.Under more preferable situation, a ferrous acid salt deposit should be arranged, and the resistance pattern layer is on the ferrous acid salt deposit on laminated chip element.The inductive patterns layer comprises that simultaneously, the inductive patterns layer also can comprise such as Ni-Cr and RuO such as silver (Ag), platinum (Pt) and palladium metal materials such as (Pd) 2The constant resistance material.Can form two metallic gaskets and isolate mutually each other, form the inductive patterns layer so that two metallic gaskets are coupled together.In addition, the top layer at the lamination wiring board also is equipped with an insulating pattern or layer.
According to the front introduction, a plurality of lamination chip components are laid parallel and integration and making becomes arranged each other, that is to say, on the terminal relatively direction of corresponding wiring board, it is parallel each other to form a plurality of conductive pattern layer, so that a plurality of unit elements can integratedly be made into the laminated chip element of arranged.In addition, the conductive pattern layer that forms on the terminal relatively lateral orientation of corresponding wiring board can extend on each unit elements.Under preferable situation, some inductive patterns layer on above-mentioned a plurality of laminated chip elements of mentioning generally is positioned at the upper surface of laminated chip element, in addition inductive patterns layer is positioned at the lower surface of laminated chip element, and the two-end-point of each inductive patterns layer all is connected with corresponding first, second coupling.Under the better condition, a plurality of inductive circuit plates are further lamination all, has an inductive patterns layer on each inductive circuit plate at least, and the two-end-point of its each inductive patterns layer all is connected with corresponding first, second coupling.With this understanding, the inductive patterns layer can be the circuitous shape of wriggling.
In the laminated chip element formerly, under the preferable situation, most of inductive circuit plates need further lamination, an inductive patterns layer is all arranged on each inductive circuit plate, and the inductive patterns layer is contacted each other by the through hole on the inductive circuit plate and is coupled together, and the two-end-point of the inductive patterns layer after the connection is connected with first, second coupling respectively again.Under better condition, through hole adopts electric conducting material to fill up so that the inductive patterns layer is connected with each other.With this understanding, the inductive circuit plate comprises the first inductive circuit plate that is formed with the first inductive patterns layer, wherein an end points of the first inductive patterns layer extends to the edge of the first inductive circuit plate and a through hole is present in first another end points of inductive patterns layer, be formed with the second inductive circuit plate of the second inductive patterns layer, wherein an end points of the second inductive patterns layer extends to the edge of the second inductive circuit plate and a through hole is present in second another end points of inductive patterns layer, and the 3rd inductive circuit plate that is formed with the 3rd inductive patterns layer, wherein on the 3rd inductive patterns layer two ends through hole is arranged respectively, wherein the 3rd inductive circuit plate is positioned at first, between second wiring board, fill up electric conducting material in the through hole, first, one end of the second inductive patterns layer is respectively with first, second coupling connects, and first to the 3rd inductive patterns layer is connected to each other by the electric conducting material that is filled in the through hole.In addition, the inductive patterns layer also can be formed on the direction of first, second coupling.But a plurality of these type of laminated chip element laid parallels and the integrated matrix form that is made as.That is to say that formed a plurality of conductive layers are parallel each other on the terminal relatively orientation of corresponding wiring board, so that a plurality of unit elements can integratedly be made into the laminated chip element of arranged.In addition, the conductive layer that is formed on the terminal relatively lateral orientation of corresponding wiring board extends on each unit elements.
According to the present invention on the other hand, one lamination chip component is provided, comprise that at least one has first wiring board of first conductive layer, wherein first conductive layer is made up of first to the 3rd section institute, first, second section makes progress separate and connects both the 3rd section and have an inductance that is predetermined in the footpath of two tail ends of first wiring board; Second wiring board of at least one tool second conductive layer, wherein second conductive layer is positioned at first wiring board, two ends transversely, and first, second section is connected with first, second coupling respectively, and one of at least the second conductive layer end is connected with the 3rd coupling, and first, second wiring board is stacked.Preferable, first and second wiring boards can alternately be laminated to each other, and first, second section of first conductive layer divides first, second coupling corresponding with it to link to each other on corresponding first wiring board.
Target according to the present invention, one lamination chip component is provided, comprise first wiring board that has first conductive layer at least and first conductive layer is formed at the first wiring board two-end-point directly makes progress, and at least one is formed with second wiring board of second conductive layer and second conductive layer is formed at the direction identical with first conductive layer; Wherein the first conductive layer two ends are connected with first, second coupling respectively, and a joint linkage section of second conductive layer is connected with the 3rd coupling, first, second wiring board lamination.The joint linkage section can be an end of second conductive layer, also can be the stage casing of second conductive layer.In addition, the joint linkage section still is two ends of second conductive layer.Under this preferable condition, first, second conductive layer that is positioned on the corresponding wiring board is arranged in parallel with each other, so that unit elements can integratedly be made as laminated chip element, the joint linkage section of second conductive layer that outermost is two-layer is connected with the 3rd coupling, the joint linkage section of other second conductive layer then with corresponding one by one joining of joint linkage section of neighbour second conductive layer, to arbitrary unit elements, the two-end-point of arbitrary first conductive layer and first, second coupling are joined.The second one or more wiring boards are between two first wiring boards.
Under preferable condition, the wiring board of previous laminated chip element can comprise ferrite wiring board, ceramic wiring board, rheostat wiring board, PTC themistor wiring board or NTC themistor wiring board etc., conductive pattern layer can comprise metal material such as Ag, Pt and Pd, and wherein some conductive pattern layer can comprise resistance material such as Ni-Cr and RuO 2
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
In conjunction with appended figure and by the following description to optional embodiment, characteristic of the present invention and advantage are apparent, and accompanying drawing is described below:
Fig. 1 is the production process figure that makes laminated chip element according to embodiments of the invention 1.
Fig. 2 is the cutaway view of the laminated chip element made according to embodiments of the invention 1.
Fig. 3 is the equivalent circuit diagram of the laminated chip element made according to embodiments of the invention 1.
Fig. 4 is the curve chart of the frequency characteristic of the laminated chip element made according to embodiments of the invention 1.
Fig. 5 is the production process figure of the laminated chip element made according to embodiments of the invention 2.
Fig. 6 is the cutaway view of the laminated chip element made according to embodiments of the invention 2.
Fig. 7 is the production process figure of the laminated chip element made according to embodiments of the invention 3.
Fig. 8 is the production process figure of the laminated chip element made according to embodiments of the invention 4.
Fig. 9 is the cutaway view of the laminated chip element made according to embodiments of the invention 4.
Figure 10 is the production process figure of the laminated chip element made according to embodiments of the invention 5.
Figure 11 is the curve chart of the frequency characteristic of the laminated chip element made according to embodiments of the invention 5.
Figure 12 is the production process figure of the laminated chip element made according to embodiments of the invention 6.
Figure 13 is the equivalent circuit diagram of the laminated chip element made according to embodiments of the invention 6.
Figure 14 is the production process figure of the laminated chip element made according to embodiments of the invention 7.
Figure 15 is the plane graph of the laminated chip element made according to embodiments of the invention 7.
Figure 16 is the equivalent circuit diagram of the laminated chip element made according to embodiments of the invention 7.
Figure 17 is a perspective view of revising laminated chip element of making according to embodiments of the invention 7.
Figure 18 is that another that make according to embodiments of the invention 7 revised the perspective view of laminated chip element.
Figure 19 is the production process figure of the laminated chip element made according to embodiments of the invention 8.
Figure 20 is the production process figure of the laminated chip element made according to embodiments of the invention 9.
Figure 21 is that another that make according to embodiments of the invention 9 revised the exploded perspective view of laminated chip element.
Figure 22 is the production process figure of the laminated chip element made according to embodiments of the invention 10.
Figure 23 is the equivalent circuit diagram of the laminated chip element made according to embodiments of the invention 10.
Figure 24 is the curve chart of the frequency characteristic of the laminated chip element made according to embodiments of the invention 10 and prior art.
Figure 25 is the production process figure of the laminated chip element made according to embodiments of the invention 11.
Figure 26 is the equivalent circuit diagram of the laminated chip element made according to embodiments of the invention 11.
Figure 27 is the operation chart of the laminated chip element made according to embodiments of the invention 11.
Figure 28 is the curve chart of the frequency characteristic of the laminated chip element made according to embodiments of the invention 11 and prior art.
Figure 29 is the production process figure of the laminated chip element made according to embodiments of the invention 12.
Figure 30 is the operation chart of the laminated chip element made according to embodiments of the invention 12.
Figure 31 is the curve chart of the frequency characteristic of the laminated chip element made according to embodiments of the invention 12 and prior art.
Figure 32 is the production process figure of the laminated chip element made according to embodiments of the invention 13.
Figure 33 is the operation chart of the laminated chip element made according to embodiments of the invention 13.
Figure 34 is the curve chart of the frequency characteristic of the laminated chip element made according to embodiments of the invention 13 and prior art.
Figure 35 is the production process figure of the laminated chip element made according to prior art.
Figure 36 is the cutaway view of the laminated chip element made according to prior art.
Figure 37 is the plane graph of the laminated chip element made according to prior art.
Figure 38 is the equivalent circuit diagram of the laminated chip element made according to prior art.
Figure 39 is the curve chart of the frequency characteristic of the laminated chip element made according to prior art.
100,200,300,400,500,600,700,800,900,1000,1100,1200,1300,1400: blank circuit board
101-102,201-202,301-303,401-404,501-503,601-602,701-703,801-803,901-903,1001a-d, 1002,1101-1102,1201-1202,1301-1302,1401-1402: circuit board
110-112、210-212、310-312、410-413、510-512、610-611、710-712、
1010-812、910-912、1010a-d、1011、1110-1111、1210-1211、1310-1311、
1410-1411: conductive pattern layer
212a-b, 610a-c, 611a-b, 1010a1-a3: the part section of conductive pattern layer
130-132,230-233,330-332,430-433,530-532,630-632,730-732,1030-1032,1130-1132,1230-1232,1330-1332,1430-1432: coupling
140,240,340,440,540,640: metallic gasket
740: the ferrous acid salt deposit
840a-840d, 940a-940c: the inductive circuit plate
150,250,350,450,550,650: resistive layer
750,850a-850d, 950a-950c: inductor layer
160,260,360,460,560,660: insulating barrier
770: bridge shape pattern
780: insulative bridge
Embodiment
Hereinafter, we will describe embodiments of the invention in conjunction with the accompanying drawings particularly:
[embodiment 1]
Fig. 1 to Fig. 4 has specifically showed the laminated chip element of making according to the embodiment of the invention 1.
Fig. 1 is the production process figure of the laminated chip element made according to the embodiment of the invention 1, wherein a plurality of elements, and as four unit elements, integrated making becomes the one chip element.
At first, making can be installed the green circuit plate of expectation element.If the making rheostat, at first must buy and be used to make rheostatic initial feed powder, generally by arriving that commercial sources just can be bought.Maybe can prepare the initial feed powder, with ZnO powder and other additives such as Bi 2O 3,, CoO and MnO and solvent such as water or ethanol is mixed, and their mixture was got final product with ball mill grinding in 24 hours.In order to make the green circuit plate, at first obtain slurry with PVB base binder additive and the rheostatic material powder of the above-mentioned making that is mentioned to are mixed, then these mixtures are dissolved in the toluene/ethanol based solvent about 24 hours of employing ball mill grinding.By using similar instruments such as doctor above-mentioned slurry can be made into the green circuit plate 100 to 102 (as shown in Figure 1) of expection thickness.By the same quadrat method of foregoing description, also raw material powder, PTC themistor or the NTC themistor that is used to make capacitor can be made into corresponding green circuit plate with expection thickness.
Conductive pattern layer is positioned on the green circuit plate, can conducting glue Ag, Pt and Pd etc. are printed on the green circuit plate and form conductive pattern layer as screen plate printing method, utilizes the web plate of the tool internal electrode pattern layer that had for example before designed.This that is to say, first, second conductive pattern layer 110 and 111 is formed on the first circuit board, make first, second conductive pattern layer 110 and 111 isolate the two relative tail ends that are in circuit board 101 mutually and directly make progress, and the 3rd conductive pattern layer 112 on the second circuit board 102 is positioned at 101 liang of relative tail ends of first circuit board transversely.First, second conductive pattern layer 110 and 111 width can be different.
When a plurality of unit elements are made as the one chip element as four unit elements are integrated, many to first, second conductive pattern layer 110 and 111 parallel to each other putting, so that every pair of first, second conductive pattern layer 110 and 111 all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.The 3rd conductive pattern layer 112 that connects common electrode extends on the unit elements.In addition, an end points of an end points of first conductive pattern layer 110 and second conductive pattern layer outer surface that is exposed to the lamination element is connected first and second couplings 130 and 131 respectively.The outer surface that 112 two opposite endpoint of the 3rd conductive pattern layer also are exposed to the lamination element is connected with the 3rd coupling 132.Perhaps, the outer surface that the wherein arbitrary end points of the 3rd conductive pattern layer 112 optionally is exposed to the lamination element is connected with the 3rd coupling 132, and an other end points of the conductive pattern layer that needn't be connected with coupling, also needn't be exposed to the outer surface of lamination element.
Two first circuit boards 101 and two second circuit boards 102, it all has corresponding conductive pattern layer above each, optionally mutual lamination between them.Next, lamination is without any the blank circuit board 100 of conductive pattern layer, as shown in Figure 1.In addition, for the electric capacity that obtains to expect, although first, second circuit board 101 and 102 lamination alternately each other in embodiments of the present invention, a plurality of first, second circuit boards 101 and 102 still selectivity lamination in every way under some occasion.That is to say that by controlling the lamination number of first, second circuit board, the electric capacity of element can control to desired value.
After the circuit board lamination, laminated sheet compresses by pressurization, heating, and makes the circuit board behind the lamination form combination closely each other.Again afterwards, laminated sheet was cut into suitable size.If laminated sheet cuts along double dotted line laminated sheet is cut into unit elements, just each unit elements has become the one chip element.Equally, if laminated sheet cuts according to the unit elements of given number, each incised layer pressing plate that has several unit elements will be made as an one chip element.As shown in Figure 1, four unit elements are positioned at same septum if laminated sheet is cut, and are arranged in parallel, have the matrix type one chip element of four unit elements with producing each other.
In fact, first, second circuit board 101 and 102 can a plurality ofly prepare according to certain first to the 3rd conductive pattern layer that is spaced by making repeatedly on corresponding circuit board.101 and 102 stacked when first, second circuit board, compress after, if necessary laminated sheet is cut into the size (for example, shown in Fig. 1 (a)) of expection, this production process process is suitable for a large amount of productions.
In order from laminated sheet, to remove, laminated sheet 300 ℃ of following roastings, is improved temperature then, sintering under suitable sintering temperature (as 1100 ℃) as organic substances such as bonding agents.
At this moment, coupling is connected with each conductive pattern layer and optionally before forming coupling, forms resistance (pattern) layer 150 and metallic gasket 140, and make element.
Metallic gasket 140 has predetermined area, and the upper surface that it is positioned at laminated sheet that is to say that it is positioned on the blank circuit board, and its position is corresponding with first, second coupling 130 and 131.Resistive layer 150 is to adopt resistance gluing RuO 2Deng and the upper surface that is printed in laminated sheet form, it and metallic gasket 140 are connected to each other.And then on resistive layer 150, form insulation (pattern) layer 160 with protective resistance layer 150.
This resistive layer also can be positioned on the independent circuit board.That is, the resistor circuit plate with resistive layer is through lamination, cutting, again with it with first, second circuit board 101 and 102 sintering.The protective layer of the circuit board upper space behind the blank circuit board 100 conduct protection laminations, further lamination rather than formation insulating barrier 160.In order to simplify production process, the making of resistive layer can not need metallic gasket 140.
After coupling (be arranged in the laminated sheet outside, in order to the conductive pattern layer and the resistive layer of articulamentum pressing plate) formed, laminated chip element also promptly completed.The Ag adhesive is coated on the rubber disc (its periphery with corresponding to the joint number that will form and the groove of position), and by rubber disc is glued mutually with the intimate of laminated sheet, the rotation rubber disk covers coupling with brush again.Laminated sheet after then brush being covered is at suitable sintering temperature.
After the coupling that connection is positioned at conductive pattern layer and resistive layer on the laminated sheet forms, by use as the stencil printing general for example epoxy resin or glass printing form one deck insulating protective layer in the surface of resistive layer.
But insulating barrier 160 or/and be positioned at the influence that insulating protective layer protective resistance layer on the resistive layer is not corroded by moisture etc.
Four pairs first conductive pattern layer 110 and second conductive pattern layer 111 are separate, be positioned on the first circuit board two opposite end directions, they are emitted on the first circuit board 101 of laminated chip abreast, and wherein every pair of first, second conductive pattern layer is distributed within the scope of each unit elements.The 3rd conduction (pattern) layer 112 is positioned on the second circuit board 102, is in first circuit board two relative tail ends transversely.Resistive layer 150 is positioned at the upper surface of stacked wiring board, is on the direction of first circuit board 2 opposite end points.In addition, for each unit elements, first, second coupling 130 and 131 conductive pattern layer that link to each other with 111 with separately first, second conductive pattern layer 110 are input and output side (being signal electrode), also are connected with two opposite endpoint of resistive layer 150 respectively.The 3rd coupling 132 conductive pattern layer that are connected with 112 two opposite endpoint of the 3rd conductive pattern layer are common terminal (grounding electrode).With this understanding, common terminal can join with the 3rd conductive pattern layer 112 arbitrary contacts.
Meanwhile, the part after being separated by double dot dash line has just had the function of unit elements, has formed overlapping part between first and second conductive pattern layer 110 and the 111 and the 3rd conductive pattern layer 112.Because the area of overlapped part differs from one another, so the capacitor C1 that has between the electric capacity of overlapped part between the first and the 3rd conductive pattern layer is different from the capacitor C2 with electric capacity of overlapped part between the second and the 3rd conductive pattern layer.Therefore, the structure of present embodiment chips element is exactly that capacitor C1 and C2 are between common terminal that connects 150 liang of opposite end points of resistive layer respectively and input and output joint, as shown in Figure 3.
It should be noted that if a plurality of first, second circuit boards 101 and 102 alternatively laminated each other in the element, as shown in Figure 1, then first, second conductive pattern layer 110 and 111 and be positioned at the 3rd conductive pattern layer 112 in the middle of first, second circuit board 101 and 102 behind the lamination not only overlapped and also with the 3rd conductive pattern layer 112 and with adjacent first, second conductive pattern layer 110 and 111 overlaids of low, high circuit board (being the outermost circuit board).Therefore, between the low spot of first, second conductive pattern layer 110 on the intermediate circuit plate and 111 and high point, formed an electric capacity.
Shown in the cutaway view of Fig. 2, in laminated chip element, metallic gasket 140 is contained in respectively on 150 two end points of resistive layer.Therefore, if accurately controlled distance between the metallic gasket 140, so also just accurately controlled the resistance of resistive layer 150.When a plurality of unit elements were made into one chip, the resistance of each unit elements was promptly consistent.
Because it is also inequality each other to be positioned at the electric capacity of input and output joint capacitor, when the element in the present embodiment when the low pass filter because it has two electric capacity, thus element have two adjacent from humorous frequency (as shown in Figure 4).Therefore, the frequency range that can remove high frequency noise is widened.In addition, because laminated chip element has the resistors in series that is positioned at holding wire middle (being between the input and output joint), and resistors in series or act on the restricting signal line current or as the resistors in series of impedance matching, and in digit circuit, it can also stop the generation of the ringing in the square-wave pulse signal.
Meanwhile, some conductions (pattern) layers can adopt metal material such as Ag, Pt and Pd etc. so that improve electric conductivity, and some conductive pattern layer then can adopt such as Ni-Cr and RuO 2The constant resistance material is so that reach the purpose that reduces electric conductivity.Therefore, but the impedance matching in the easy adjustment circuit.
[embodiment 2]
Present embodiment 2 as shown in Figure 5 and Figure 6.Embodiment 2 mainly is by changing conduction (pattern) the layer shape of (it is connected with common terminal among the embodiment 1), carrying out modulation with the character to previous element.
Fig. 5 wherein has four unit elements to be integrated and is made into the one chip element for the production process figure of the laminated chip element made according to embodiments of the invention.
The green circuit plate that the expection element is housed adopts the method making identical with embodiment 1.
Conductive pattern layer is positioned on the green circuit plate, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say, first, second conductive pattern layer 210 and 211 is printed on the first circuit board 201, makes first, second conductive pattern layer 210 and 211 isolate the two relative tail ends that are in circuit board 201 mutually and directly makes progress.The 3rd conductive pattern layer 212 is made up of first section 212a and second section 212b, its separate each other be positioned at be in first circuit board 201 on the second circuit board 202 two relative tail ends transversely.The width of first conductive pattern layer 210 and second conductive pattern layer 211 each other can be inequality.Shown in Fig. 5 a.
When a plurality of unit elements are assembled into an one chip element as four unit elements are integrated, many in first conductive pattern layer 210 and second conductive pattern layer 211 put element is parallel to each other, so that every pair of conductive pattern layer all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.First section (partly) 212a of the 3rd conductive pattern layer 212 is connected with common terminal (grounding electrode) with second section 212b.In addition, an end points of an end points of first conductive pattern layer 210 and second conductive pattern layer 211 outer surface that is exposed to the lamination element is connected first and second couplings 230 and 231 respectively.The outer surface that the two opposite ends point of first section 212a and second section 212b is exposed to the lamination element respectively with the 3rd coupling 232 with all round joint 233 be connected.Each of the conductive pattern layer that is not connected with coupling partly needn't be exposed to the outer surface of lamination element.
In the present embodiment shown in Fig. 5 (a), first, second circuit board 201 and 202 laminations are so that two second circuit boards 202 can be between two first circuit boards 201, and blank circuit board 200 can be laminated thereon.For making its element have the electric capacity of expection, a plurality of first circuit boards 201 and second circuit board 202 can come in conjunction with lamination by different way.This that is to say, by controlling the lamination number of first, second circuit board, just the electric capacity of element can be controlled to desired value.
After circuit board such as above-mentioned step layer were pressed, laminated sheet compressed, cuts into operations such as suitable size, roasting and sintering as experience as described in the embodiment 1.At this moment, via making the laminated sheet of coupling behind sintering, and coupling is connected with separately conductive pattern layer, and optionally forms resistance (pattern) layer 250 and metallic gasket 240 (describing as embodiment 1) before making coupling, and finishes the making element.
Describe as embodiment 1, be arranged in the metallic gasket 240 and the resistive layer 250 of laminated sheet upper space behind the sintering and form via formation and be positioned at joint outside the laminated sheet outer surface (conductive pattern layer of articulamentum pressing plate and resistive layer), laminated chip element is made and is just finished.Yet, opposite with embodiment 1, in the present embodiment the two relative tail ends of first of the 3rd conductive pattern layer section 212a and second section 212b respectively with the 3rd, all round joint 232 and 233 join.
The structure and the embodiment of first, second conductive pattern layer of laminated chip element and resistive layer are identical in the present embodiment, wherein the 3rd, all round joint 232 and 233 join with first, second section 212a of the 3rd conductive pattern layer and two corresponding points of 212b respectively, form common terminal (being grounding electrode).
Be different from the overlapped part between second section 212b of second conductive pattern layer 211 and the 3rd conductive pattern layer 212 in the overlapped part between first section 212a of first conductive pattern layer 210 and the 3rd conductive pattern layer 212.Therefore, have and first conductive pattern layer 210 and first section 212a between the capacitor C1 of electric capacity of overlapped part be different from have and second conductive pattern layer 211 and second section 212b between the capacitor C2 of electric capacity of overlapped part.Therefore, the structure of the chip component in the present embodiment is similar to embodiment 1, and the capacitor C1 and the C2 that are positioned at 250 liang of relative tail ends of resistive layer join with common terminal respectively.Because first section 212a of the 3rd conductive pattern layer can with 210 collaborative works of first conductive pattern layer, and second section 212b of the 3rd conductive pattern layer and 211 collaborative works of second conductive pattern layer; So the common terminal that joins with first section 212a of the 3rd conductive pattern layer with separate with common terminal that second section 212b of the 3rd conductive pattern layer joins, so, under the situation that does not have the phase mutual interference between C1 and the C2, understand frequency characteristic and make possible.
[embodiment 3]
Embodiment 3 as shown in Figure 7, and is identical with embodiment 1 except first, second conductive pattern layer is positioned at independently on the circuit board.
Fig. 7 is for making the production process figure of laminated chip element according to embodiments of the invention, wherein be made as an one chip element with four unit elements are integrated.
The green circuit plate that the expection element is housed adopts the method making identical with embodiment 1.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say that first conductive pattern layer 310 is positioned at the footpath that is in 301 liang of relative tail ends of first circuit board on the first circuit board 301 and makes progress; Second conductive pattern layer 311 is positioned on the second circuit board 302 and is in same direction with first conductive pattern layer 310; The 3rd conductive pattern layer 312 is positioned on the tertiary circuit plate 303 across first conductive pattern layer 310.Meanwhile, make the width of first, second conductive pattern layer 310 and 311 differ from one another.
When a plurality of unit elements are made as an one chip element as four unit elements are integrated, many in first, second conductive pattern layer 310 and 311 put element is parallel to each other, so that every pair of conductive pattern layer all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.The 3rd conductive pattern layer 312 extensions that will be connected with common terminal are distributed on the whole unit element.In addition, first, second conductive pattern layer 310 is connected with 331 with first, second coupling 330 respectively with the outer surface that 311 two opposite ends point is exposed to the lamination element; Outer surface and the 3rd coupling 332 that the two opposite ends point of the 3rd conductive pattern layer 312 is exposed to the lamination element are joined; In addition, outer surface and the 3rd coupling 332 that optionally any end of the 3rd conductive pattern layer 312 is exposed to the lamination element joined.Each of the conductive pattern layer of joining with corresponding coupling partly can not be exposed to the outside of lamination element.
Be positioned at first on the conductive pattern layer separately to the order lamination of tertiary circuit plate (301 to 303), then with on blank circuit board 300 laminations and its according to first circuit board 301, tertiary circuit plate 303, second circuit board 302.In order to make element obtain the expectation capacitance, also optionally carry out lamination with different combinations to the tertiary circuit plate with a plurality of first.For example, first can carry out lamination according to the order of first circuit board 301, tertiary circuit plate 303, first circuit board 301, second circuit board 302, tertiary circuit plate 303 and second circuit board 302 to the tertiary circuit plate.That is to say, can be by control first the lamination number to the tertiary circuit plate, the electric capacity that comes control element is to reach desired value.
After circuit board is through lamination as above, again laminated sheet is carried out the processing identical as embodiment 1, promptly compress, cut into suitable size, roasting and sintering.At this moment, via making the laminated sheet of coupling behind sintering, and coupling is connected with separately conductive pattern layer, and optionally forms resistance (pattern) layer 350 and metallic gasket 340 (describing as embodiment 1) before making coupling, and finishes the making element.
As described in Example 1, when laminated sheet upper metallic gasket 340 with resistive layer 350 and be positioned at the laminated sheet extexine, after the coupling that is used to be connected conductive pattern layer and resistive layer forms, laminated chip element is just made and is finished.
According to above-mentioned manufacture method, four lay respectively on first, second circuit board 301 and 302 of laminated chip element in parallel with each other to first, second conductive pattern layer 310 and 311, and wherein every pair of first, second conductive pattern layer 310 and 311 is within the corresponding single unit elements scope direction towards circuit board 2 opposite end points and extends; The 3rd conductive pattern layer 312 is positioned on the tertiary circuit plate 303 and the cross direction profiles of prolonging circuit board 2 opposite end points; Resistive layer 350 is positioned on the stacked wiring board and along circuit board two opposite end point radial distribution.In addition, for each unit elements, first, second coupling 330 and 331 and an end points of first, second coupling 310 and 311 join, form input and output joints (being signal electrode), it also joins with the two opposite ends point of resistive layer 350 respectively.The two opposite ends point of the 3rd coupling 332 and the 3rd conductive pattern layer 312 joins, and forms common terminal (being grounding electrode).With this understanding, common terminal can be connected with any end points of the 3rd conductive pattern layer 312.
Be different from overlapped part between second conductive pattern layer 311 and the 3rd conductive pattern layer 312 in the overlapped part between first conductive pattern layer 310 and the 3rd conductive pattern layer 312.Therefore, have and first conductive pattern layer 310 and the 3rd conductive pattern layer 312 between the capacitor C1 of electric capacity of overlapped part be different from have and second conductive pattern layer 311 and the 3rd conductive pattern layer 312 between the capacitor C2 of electric capacity of overlapped part.Therefore, the structure of the chip component in the present embodiment is that capacitor C1 and the C2 that is positioned at 350 liang of relative tail ends of resistive layer joins with common terminal respectively.
Although the chip component of present embodiment has the similar character of laminated chip element to embodiment 1 made, but because first conductive pattern layer 310 lays respectively on the different circuit boards with second conductive pattern layer 311, so can determine the conductive pattern layer overlay segment of capacitance size partly can freely design.
[embodiment 4]
Present embodiment removes the conductive pattern layer be connected with common terminal and lays respectively on the independent circuit board shown in Fig. 8 and 9, and with outside first, second conductive pattern layer 410 and 411 is cooperated jointly, other are similar to embodiment 3.
Fig. 8 is for making the production process figure of laminated chip element according to embodiments of the invention, wherein be made as an one chip element with four unit elements are integrated.
The green circuit plate that the expection element is housed adopts the method making identical with embodiment 1.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say, first conductive pattern layer 410 is positioned on the first circuit board 401, along circuit board 2 opposite end points radially; Second conductive pattern layer 411 is positioned on the second circuit board 402 and is on the same direction with first conductive pattern layer 410; The 3rd conductive pattern layer 412 is positioned on the tertiary circuit plate 403 across first conductive pattern layer 410; In addition, the 4th conductive pattern layer 413 is positioned on the 4th circuit board 404 and is on the same direction with the 3rd conductive pattern layer 412.For this reason, first, second conductive pattern layer 410 of making and 411 width differ from one another.
When a plurality of unit elements are made as an one chip element as four unit elements are integrated, many in first, second conductive pattern layer 410 and 411 put element is parallel to each other, every pair of conductive pattern layer all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.To all be distributed on the whole unit element with the 3rd, the 4th conductive pattern layer 412 and 413 that is connected with common terminal (grounding electrode).In addition, first, second conductive pattern layer 410 is connected with 431 with first, second coupling 430 respectively with the outer surface that 411 two opposite ends point is exposed to the lamination element; Three, the 4th conductive pattern layer 412 and 413 two opposite ends point be exposed to the outer surface of lamination element and respectively with the 3rd, all round joint 432 and 433 join; The part of the conductive pattern layer of joining with corresponding coupling can not be exposed to the outside of lamination element.
Be positioned at first to fourth circuit board (401 to 404) on the conductive pattern layer separately according to the order lamination of second circuit board 402, tertiary circuit plate 403, the 4th circuit board 404, first circuit board 401, first circuit board 401, the 4th circuit board 404, tertiary circuit plate 403, second circuit board 402, then with on blank circuit board 400 laminations and its.In order to make element obtain the expectation capacitance, also optionally a plurality of first to fourth circuit boards are carried out lamination with different combinations.For example, first to fourth circuit board lamination is so that the 3rd, the 4th circuit board 403 and 404 can be between first, second circuit board 401 and 402.That is to say, can be by control first the lamination number to the tertiary circuit plate, the electric capacity that comes control element is to reach desired value.
After circuit board is through lamination as above, again laminated sheet is carried out the processing identical as embodiment 1, promptly compress, cut into suitable size, roasting and sintering.At this moment, via making the laminated sheet of coupling behind sintering, and coupling is connected with separately conductive pattern layer, and optionally forms resistance (pattern) layer 450 and metallic gasket 440 (describing as embodiment 1) before making coupling, and finishes the making element.
As described in Example 1, when laminated sheet upper metallic gasket 440 with resistive layer 450 and be positioned at the laminated sheet extexine, after the coupling that is used to be connected conductive pattern layer and resistive layer forms, laminated chip element is just made and is finished.Different with embodiment 1 and 3 is, in the present embodiment the 3rd, the 4th conductive pattern layer 412 and 413 2 opposite end points respectively with the 3rd, all round joint 432 be connected with 433.
According to above-mentioned manufacture method, four lay respectively on first, second circuit board 401 and 402 of laminated chip element in parallel with each other to first, second conductive pattern layer 410 and 411, and wherein every pair of first, second conductive pattern layer 410 and 411 is within the unit elements scope direction towards circuit board 2 opposite end points and extends; Three, the 4th conductive pattern layer 412 and 413 is positioned on the 3rd, the 4th circuit board 403 and 404 and along the first or second conductive pattern layer cross direction profiles; Resistive layer 450 be positioned on the stacked wiring board and with the equidirectional distribution of first or second conductive pattern layer.In addition, for each unit elements, first, second coupling 430 and 431 and an end points of first, second coupling 410 and 411 join, form input and output joints (being signal electrode), it also joins with the two opposite ends point of resistive layer 450 respectively.Three, all round joint 432 and 433 join with the two opposite ends point of the 3rd, the 4th conductive pattern layer 412 and 413 respectively, form common terminal (being grounding electrode).
Just the function that has been had unit elements by the part after the double dot dash line separation.At first as shown in Figure 8, with first to fourth circuit board lamination, exist overlay segment partly between the first and the 3rd conductive pattern layer and between the second and the 4th conductive pattern layer.Meanwhile, because the area of overlay segment differs from one another, have and the capacitor C2 of the electric capacity of overlapped part between the second and the 4th conductive pattern layer so have and be different between the capacitor C1 of the electric capacity of the overlapped part between the first and the 3rd conductive pattern layer.Therefore, the chip component structure in the present embodiment is exactly that the capacitor C1 that is positioned at 150 liang of relative tail ends of resistive layer is connected common terminal respectively with C2.Even mutual alternative between tertiary circuit plate 402 and the 4th circuit board 403 can obtain identical result equally.
Remove because the 3rd conductive pattern layer 412 lays respectively on the different circuit boards with the 4th conductive pattern layer 413, and the common terminal that causes the 3rd conductive pattern layer 412 that connects collaborative first conductive pattern layer 410 is with outside the common terminal that links to each other with the 4th conductive pattern layer 413 that is connected collaborative second conductive pattern layer 411 is separate, adopts the laminated chip element of present embodiment making to have the similar character of laminated chip element to embodiment 3 mades.If connect the conductive pattern layer independence separated from one another of common terminal, it is possible not having to understand frequency characteristic under the mutual interference mutually at C1 and C2 so.In addition, if in each electric capacity the changeless words of sense of current, equivalent series inductance will increase so.
As described in Example 1 the same, metallic gasket 440 lays respectively at the two-end-point that is present in the resistive layer 450 in the laminated chip element, therefore, if accurately controlled distance between the metallic gasket 440, has also just accurately controlled the resistance of resistive layer 450.Also inequality each other because be positioned at the electric capacity of capacitor of input/output terminal again, thus when element during as low pass filter, element owing to have two capacitances its also will have two adjacent from humorous frequency.Therefore, the frequency range that can remove high frequency noise is widened.
[embodiment 5]
Present embodiment shown in Figure 10 and 11, except that conductive pattern layer with common terminal links to each other, other are all similar to embodiment 4.
Figure 10 is for making the production process figure of laminated chip element according to embodiments of the invention, wherein be made as an one chip element with four unit elements are integrated.
The green circuit plate that the expection element is housed adopts the method making identical with embodiment 1.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say that first conductive pattern layer 510 is positioned at the footpath of prolonging 501 liang of opposite end points of circuit board on the first circuit board 501 and makes progress; Second conductive pattern layer 511 is positioned on the second circuit board 502 and is on the same direction with first conductive pattern layer 510; The 3rd conductive pattern layer 512 is positioned on the tertiary circuit plate 503 and is in same direction with first conductive pattern layer 510.For this reason, first, second conductive pattern layer 510 of making and 511 width differ from one another.
When a plurality of unit elements are made as an one chip element as four unit elements are integrated, many in first, second conductive pattern layer 510 and 511 put element is parallel to each other, every pair of conductive pattern layer all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.Three, the 4th conductive pattern layer 512 all is connected with common terminal (grounding electrode) with 513 and is distributed in the whole unit element.In addition, first, second conductive pattern layer 510 is connected with 531 with first, second coupling 530 respectively with the outer surface that 511 two opposite ends point is exposed to the lamination element; The 3rd conductive pattern layer 512 end points are connected to each other, and its outermost end points extends the edge of tertiary circuit plate 503 so that its end points can be exposed to the outer surface of lamination element and join with the 3rd coupling 532 simultaneously.Perhaps, all extensible edge in tertiary circuit plate 503 of the 3rd conductive pattern layer 512 outermost arbitrary end points is so that its end points can be exposed to the outer surface of lamination element and join with the 3rd coupling 532.The part of the conductive pattern layer of joining with corresponding coupling can not be exposed to the outside of lamination element.
Be positioned at first on the conductive pattern layer separately to the order lamination of tertiary circuit plate (501 to 503) according to first circuit board 501, tertiary circuit plate 503, first circuit board 501, second circuit board 502, tertiary circuit plate 503, second circuit board 502, then with on blank circuit board 500 laminations and its, as shown in figure 10.That is, the ground floor pressing plate by two first circuit boards 501 and tertiary circuit plate between two first circuit boards 501 and form; Between two second circuit boards 502 and form, the ground floor pressing plate is positioned at lamination on the second layer pressing plate to second layer pressing plate then by two second circuit boards 502 and tertiary circuit plate 503.Area that it should be noted that the conductive pattern layer on the circuit board that is arranged in the ground floor pressing plate is littler than the area of the conductive pattern layer on the circuit board that is arranged in second layer pressing plate.In order to make element obtain the expectation capacitance, also optionally carry out lamination with different combinations to the tertiary circuit plate with a plurality of first.For example, first press so that tertiary circuit plate 503 can be between first, second circuit board 501 and 502 to the tertiary circuit flaggy.That is to say, can be by control first the lamination number to the tertiary circuit plate, the electric capacity that comes control element is to reach desired value.
After circuit board is through lamination as above, again laminated sheet is carried out the processing identical as embodiment 1, promptly compress, cut into suitable size, roasting and sintering.At this moment, via making the laminated sheet of coupling behind sintering, and coupling is connected with separately conductive pattern layer, and optionally forms resistance (pattern) layer 550 and metallic gasket 540 (describing as embodiment 1) before making coupling, and finishes the making element.
As described in Example 1, when sinter layer pressing plate upper metallic gasket 540 with resistive layer 550 and be positioned at the laminated sheet extexine, after the coupling that is used to be connected conductive pattern layer and resistive layer forms, laminated chip element is just made and is finished.
According to above-mentioned manufacture method, four lay respectively on first, second circuit board 501 and 502 of laminated chip element in parallel with each other to first, second conductive pattern layer 510 and 511, and wherein every pair of first, second conductive pattern layer 510 and 511 is within the unit elements scope along circuit board 2 opposite end points radially; Four the 3rd conductive pattern layer 512 are located parallel on the tertiary circuit plate 503 and are in same direction with first or second conductive pattern layer; Resistive layer 550 is positioned on the stacked wiring board and is in same direction with second conductive pattern layer; Simultaneously, every pair the 3rd conductive pattern layer 512 and resistive layer 550 also all are in each unit elements scope.In addition, for each unit elements, first, second coupling 530 and 531 and an end points of first, second coupling 510 and 511 join, form input and output joints (being signal electrode), it also joins with the two opposite ends point of resistive layer 550 respectively.Common terminal can join with the 3rd conductive pattern layer 512 outermost any end points.
Present embodiment is similar to the embodiment of front, because capacitor is between common terminal and the input and output joint that is connected resistive layer 2 opposite end points, and it has the electric capacity of overlay segment between partly.Yet, as shown in figure 10, first conductive pattern layer 510 in the ground floor pressing plate is connected with input terminal (have between first conductive pattern layer and the 3rd conductive pattern layer less overlay segment partly), and second conductive pattern layer 511 in the second layer pressing plate be connected with outlet terminal (between second conductive pattern layer and the 3rd conductive pattern layer, having bigger lap joints).Therefore, electric capacity and the equivalent inductance of the capacitor C1 of input terminal are bigger, and electric capacity and the equivalent inductance of the capacitor C2 of outlet terminal are less.Can find according to Figure 11, element can have owing to have two capacitances two adjacent from humorous frequency, widen so can remove the frequency range of high frequency noise.
[embodiment 6]
Present embodiment is shown in Figure 12 and 13, and the conductive pattern layer that the electric capacity of element can be by form connecting input, output and common terminal on the same circuit board is modulation in addition.
Figure 12 is for making the production process figure of laminated chip element according to embodiments of the invention, wherein be made as an one chip element with four unit elements are integrated.
The green circuit plate that the expection element is housed adopts the method making identical with embodiment 1.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say, first conductive pattern layer of being made up of first to the 3rd section (partly) 610a to 610c 610 is positioned on the first circuit board 601, first, second section is separated from each other, is positioned at directly making progress of 601 liang of opposite end points of circuit board, the 3rd section 601c be positioned between the two and separate with first, second section and be in 601 liang of opposite end points of circuit board transversely; The 2 opposite end points of the end points of first, second section 601a and 601b and the 3rd section 610c join with coupling.First, second conductive pattern layer 610 and 611 width of making can differ from one another.
In addition, second conductive pattern layer of being made up of the 4th, the 5th section 611a and 611b 611 is to insulate with coupling, be positioned on the second circuit board 602, so first, the 3rd section 610a and the 610c of first conductive pattern layer 610 on the 4th section 611a and the first circuit board 601 are partly overlapping, and second, third section 610b and the 610c part of first conductive pattern layer 610 on the 5th section 611b and the first circuit board 601 are overlapping.
When a plurality of unit elements are assembled into an one chip element as four unit elements are integrated, the the 4th, the 5th section 611a and the 611b that at first will overlap first, second section 610a of first conductive pattern layer 610 and the 610b and second conductive pattern layer 611 are laid parallel more, so the section piece of every cover conductive pattern layer all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.The 3rd section 610c extension of first conductive pattern layer 610 that will be connected with common terminal is dispersed throughout on the whole unit element.
Present embodiment as shown in figure 12, at first with first, second circuit board 601 and 602 laminations, it is in proper order: first circuit board 601, second circuit board 602, second circuit board 602, first circuit board 601, add blank circuit board 600 further laminations behind the lamination.Yet, obtaining the electric capacity of expection in order to make element, the anticipated number that can change first circuit board and second circuit board during lamination arbitrarily also can take various combination to carry out lamination.Therefore, the lamination quantity that controls first, second circuit board 601 and 602 also just can control to desired value with the electric capacity of element.
After circuit board is through lamination as above, again laminated sheet is carried out the processing identical as embodiment 1, promptly compress, cut into suitable size, roasting and sintering.At this moment, via making the laminated sheet of coupling behind sintering, and coupling is connected with separately conductive pattern layer, and optionally forms resistance (pattern) layer 650 and metallic gasket 640 (describing as embodiment 1) before making coupling, and finishes the making element.
As described in Example 1, when sinter layer pressing plate upper metallic gasket 640 with resistive layer 650 and be positioned at the laminated sheet extexine, after the coupling that is used to be connected conductive pattern layer and resistive layer forms, laminated chip element is just made and is finished.
With the laminated units element behind first circuit board 601 and second circuit board 602 laminations, specific explanations is proposed at this.Form first conductive pattern layer 610, make first, second section 610a and 610b radially separate, and the 3rd section 610c and first, second section are separate and be positioned between the two and along the horizontal expansion of 2 opposite end points with circuit board 2 opposite end points; For each unit elements, the end points of first, second section 610a and 610b and first, second coupling 630 and 631 are joined, and form input/output terminal, and it also can be respectively joins with the two opposite ends point of resistive layer 650.The 2 opposite end points of the 3rd section 610c and the 3rd coupling 632 formation common electrode of joining.With this understanding, common terminal can join with any end of the 3rd section 610c.In addition, be manufactured with the second circuit board 602 of second conductive pattern layer of forming by the 4th, the 5th section 611a and 611b 611, and itself and outer terminal are isolated, thereby make that second circuit board 602 can be as drift layer.611, the four sections 611a and first of second conductive pattern layer on the second circuit board 602, the 3rd section 610a and 610c are partly overlapping being arranged in, and the 5th section 611b is overlapping with second, third section 610b and 610c part.
The first, the 3rd section 610a and 610c and the 4th section 611a are partly overlapping, thereby are deformed into two overlay segments partly between them; And second, third section 610b and 610c and the 5th section 611b are partly overlapping, thereby also form two overlay segments partly between them.Because the electric capacity of overlay segment is directly proportional with overlay segment area partly, the first section 610a that joins with input and with the 3rd section 610c that common terminal joins between the formation capacitor C31 of institute and C32 connect, and the second section 610b that joins with output and with the 3rd section 610c that common terminal joins between the formation capacitor C41 of institute and C42 connect.In addition, the resistor that is formed by resistive layer 650 joins with input/output terminal a and b, and the equivalent circuit diagram of its structure as shown in figure 13.
The laminated chip element of making according to above-mentioned steps comprises a plurality of capacitors at input/output terminal, as shown in figure 13.When needs when input/output terminal is installed a plurality of capacitor, this structure is a preferred configuration.As previously mentioned, connect mutually if make at the capacitor of input/output terminal separately by first, second circuit board 601 and 602 of lamination, then equivalent capacity will descend.Therefore, obtain to reduce equivalent series resistance and improve frequency properties such as insertion loss by the quantity that increases the board layer pressing plate under the identical electric capacity.
This shows, although in embodiment 1 to 6, all made the resistive layer that is positioned on the resistance circuit plate with controlling resistance, can a plurality of resistor circuit plates of lamination and the area of resistive layer also can change.
[embodiment 7]
Present embodiment is shown in Figure 14 to 18, and except that the resistive layer on the blank circuit board was replaced by inductance (pattern) layer, other were all identical with embodiment 3.
Figure 14 is for making the production process figure of laminated chip element according to embodiments of the invention, wherein be made as an one chip element with four unit elements are integrated.
The green circuit plate that the expection element is housed adopts the method making identical with embodiment 1.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say that first conductive pattern layer 710 is positioned on the first circuit board 701 radially extends along 701 liang of opposite end points of first circuit board; Second conductive pattern layer 711 is positioned on the second circuit board 702 and is in same direction with first conductive pattern layer 710; The 3rd conductive pattern layer 712 is positioned on the tertiary circuit plate 703 across first conductive pattern layer 710.First, second conductive pattern layer 710 each other can be different with 711 width.
When a plurality of unit elements are made as an one chip element as four unit elements are integrated, many in first, second conductive pattern layer 710 and 711 put element is parallel to each other, every pair of conductive pattern layer all is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.The 3rd conductive pattern layer 712 extensions that will be connected with common terminal are distributed in the whole unit element.In addition, first, second conductive pattern layer 710 is connected with 731 with first, second coupling 730 respectively with the outer surface that 711 two opposite ends point is exposed to the lamination element; Outer surface and the 3rd coupling 732 that the two opposite ends point of the 3rd conductive pattern layer 712 is exposed to the lamination element are joined; In addition, outer surface and the 3rd coupling 732 that optionally any end of the 3rd conductive pattern layer 712 is exposed to the lamination element joined.The part of the conductive pattern layer of joining with corresponding coupling can not be exposed to the outside of lamination element.
Be positioned at first on the conductive pattern layer separately to the order lamination of tertiary circuit plate (701 to 703), then with on blank circuit board 700 laminations and its according to first circuit board 701, tertiary circuit plate 703, second circuit board 702.In order to make element obtain the expectation capacitance, also optionally carry out lamination with different combinations to the tertiary circuit plate with a plurality of first.
When circuit board through after the above-mentioned steps lamination, again laminated sheet is carried out the processing identical as embodiment 1, promptly compress, cut into suitable size, roasting and sintering.
Then, ferrous acid salt deposit 740 is printed on the blank circuit board 700 on sinter layer pressing plate top after, make inductance (pattern) layer 750 more thereon, present the helical form that for example arbitrary end points spreads out and from circuit board 2 opposite end points, shown in Figure 14 (c).For the center end points with spiral inductance layer 750 extends to another opposite endpoint of circuit board, form insulative bridge 780 and connect spiral inductance layers 750 center end points and be connected, shown in Figure 14 (d) with another end points across the circuit board of spiral inductance layer 750.Then, for being connected with another end points of circuit board, spiral inductance layer 750 center end points need on insulative bridge 780, to adorn a bridge shape pattern 770, shown in Figure 14 (e).Figure 15 is the plane graph of spiral inductance layer, in order to ensure being connected of inductor layer 750 and outer terminal, before inductor layer 750 forms, must inductor layer 750 two-end-points and outside first, second corresponding junction of terminal load onto metallic gasket (not marking among the figure).
Spiral inductance layer herein also can be positioned on the independent circuit board.That is, when via adorn an inductor layer on the circuit board with after making inductive circuit plate (forming) by ferrite, with the inductive circuit plate with first to tertiary circuit plate lamination, and then compress, cutting and sintering.Can add that insulation (pattern) layer 760 with protection inductor layer 750, perhaps is put in further lamination on it with a blank circuit board at the upper surface of laminated sheet.
Make the back (shown in Figure 14 (f)) that finishes when the insulating barrier 760 that is used to protect inductor layer 750, form first to the 3rd coupling 730 to 732 and also just finish the laminated chip element making.Meanwhile, the two-end-point with inductor layer 750 is connected with 731 respectively at first, second coupling 730.
In addition, after the coupling that connects conductive pattern layer and inductor layer on the laminated sheet forms,, for example adopt epoxy resin or glass in inductor layer surface printing one deck insulating protective layer again by method of printing such as stencil printing.
Load onto four respectively in parallel with each other to first, second conductive pattern layer 710 and 711 on first, second circuit board 701 and 702 of the laminated chip element of above-mentioned making, wherein every pair of first, second conductive pattern layer 710 and 711 is within the unit elements scope and towards the radially extension of 701 and 702 circuit boards, 2 opposite end points; The 3rd conductive pattern layer 712 is positioned on the tertiary circuit plate 703 and along the horizontal expansion of circuit board 2 opposite end points; Spiral inductance layer 750 is positioned on the stacked wiring board corresponding with the position of each unit elements.In addition, for each unit elements, first, second coupling 730 and 731 and first.Second conductive pattern layer 710 is connected with an end points of 711, forms input/output terminal (being signal electrode), and it 730 also can be connected with the two opposite ends point of inductor layer 750 respectively with 731; The 3rd coupling 732 is connected with the two opposite ends point of the 3rd conductive pattern layer 712, forms common terminal (grounding electrode).With this understanding, common terminal can be connected with arbitrary end points of the 3rd conductive pattern layer 712.
There is overlapped part between first conductive pattern layer 710 and the 3rd conductive pattern layer 712 and between second conductive pattern layer 711 and the 3rd conductive pattern layer 712.Because the area of overlapped part differs from one another, the capacitor C1 that has at the electric capacity of overlapped part between first conductive pattern layer 710 and the 3rd conductive pattern layer 712 is different from the capacitor C2 with electric capacity of overlapped part between second conductive pattern layer 711 and the 3rd conductive pattern layer 712.Therefore, the structure of the chip component in the present embodiment is that the capacitor C1 that is positioned at the inductor two-end-point is connected with common terminal with C2, and its equivalent circuit diagram as shown in figure 16.
Shown in Figure 14 and 15, although inductor layer is spiral in element, the shape of inductor layer can be carried out multiple variation in the present embodiment.For example, shown in Figure 17, when behind printing ferrous acid salt deposit 740 on the blank circuit board on sinter layer pressing plate top, the vertical bar shape conductive pattern layer that can adopt the metal gluing is as inductor layer.
In addition, when a plurality of unit elements are integrated when being made as the one chip element, all inductor layers (wherein each is corresponding to each unit elements) are arranged in the same surface of element laminated sheet, shown in Figure 14,15 and 17.Yet if chip component is very fine and close, the liquid that will make complicated spiral inductance layer so and be unusual difficulty and be used for the inductor layer printing will limit to some extent.In order to address the above problem, can inductor layer all be housed on two surfaces up and down of stacked wiring board, Figure 18 is the bottom and the top perspective of element.As shown in figure 18, when four unit elements were made into the one chip element, the spiral inductance of the first and the 3rd unit elements was placed on the upper surface of stacked wiring board, and the spiral inductance of the second and the 4th unit elements is placed on the lower surface of stacked wiring board.Because of the area of each spiral inductance layer increases, so that the making of inductor layer will become will be easy.
Although element has the conductive pattern layer identical with embodiment 3 in the present embodiment, resistive layer on being positioned at blank circuit board is replaced by inductor layer but also can adopt method with present embodiment, the resistive layer that is positioned on the stacked wiring board among the embodiment 1 to embodiment 6 is all replaced with inductor layer.
Formation by inductor layer and overlapping conductive pattern layer makes laminated chip element be made into to comprise the pi type filter of inductor and capacitor to become possibility.Differ from one another because be in the electric capacity of the capacitor of input/output terminal, when element during as low pass filter, because there are two capacitances, it is two adjacent from humorous frequency that the chip component that is combined with the inductor of present embodiment has.Therefore, the frequency range that can remove high frequency noise is widened.
In addition, the inductor layer that is combined with the chip component of present embodiment inductor can adopt metal material or Ni-Cr and RuO such as Ag, Pt and Pd 2The constant resistance material forms.
[embodiment 8]
Figure 19 is for being combined with the production process figure of the laminated chip element of inductor according to embodiment 8, wherein be made as with the one chip element four unit elements are integrated, and each unit elements that is positioned in this one chip element on the circuit board all has an inductance (pattern) layer.
When with a plurality of unit elements are integrated when being made as the one chip element, present embodiment is preferred embodiment.Be positioned at first on the four unit elements conductive pattern layer to tertiary circuit plate 801 to 803 and adopt the method making identical with embodiment 7.
As described in Example 7, being laminated to first the inductive circuit plate to the laminated sheet of tertiary circuit plate 801 to 803 can be via the inductor layer (being formed by ferrite) that forms on the circuit board.Draw lead by two point unit elements is divided into the one chip element, the circuitous type inductor layer 850a of one of first module element is formed on the first inductive circuit plate 840a away from the unit elements border.Yet the two opposite ends point of inductor layer 850a is positioned at the two opposite ends point of first module element.Similarly, the circuitous type inductor layer 850b to 850d of second to the 4th unit elements is placed on second to the 4th inductive circuit plate 840b to 840d, meanwhile, for guaranteeing being connected between inductor layer 750 and the outer end points, loading onto metallic gasket (not marking among the figure) with the two-end-point of corresponding each inductor layer (850a to 850d), with join with first, second coupling (before inductor layer 850a to 850d makes).
Shown in Figure 19 (a), for the laminated chip element of making according to present embodiment, when with first to tertiary circuit plate (801 to 803) lamination, first to fourth inductive circuit plate (840a to 840d) is laminated to the former above (first to the tertiary circuit plate), then on blank circuit board 800 laminations.
When circuit board through after the above-mentioned lamination step, laminated sheet through compressing, processing such as cutting, roasting and sintering, form coupling (adopting as the identical method of preceding embodiment) again, make and finish laminated chip element.
Be combined with the laminated chip element of inductor and have identical conductive pattern layer with element among the embodiment 7, and the circuitous type inductor layer 850a to 850d that joins with separately input and output (corresponding every unit elements) end.Laminated chip element embodiment 7 in the present embodiment is identical, removing has four inductive circuit plate 840a to 840d on the inductor layer 840a to 840d of each element, when four each unit elements are formed one chip elements, with foregoing circuit plate (840a to 840d) lamination each other, as shown in figure 19.Because each inductor layer is positioned on the circuit board, the laminated chip element in the present embodiment can improve its induction coefficient, thereby makes the inductor layer with expection inductance coefficent that is positioned on the larger area inductor circuit plate easily.
Although the present embodiment element is described an inductor layer and is formed on the inductive circuit plate, if necessary, on an inductive circuit plate, one or more inductor layers can be arranged.The inductive circuit plate can be laminated on the last or lower surface of the stacked wiring board that is formed with conductive pattern layer.
Except that back-shaped inductor layer, the shape of inductor layer can change, as spirality or linear.
Although element have with embodiment 3 in the identical conductive pattern layer of element, resistive layer on being positioned at blank circuit board is replaced by inductor layer, but also can adopt the method with present embodiment, the resistive layer that is positioned on the stacked wiring board among the embodiment 1 to embodiment 6 is all replaced with inductor layer.
[embodiment 9]
Figure 20 is for making the production process figure of the laminated chip element have inductor according to present embodiment, four integrated one chip elements that are made into of unit elements wherein, inductor layer are formed at and use more than the through hole on the inductor circuit plate.
At first, first to the same procedure making of tertiary circuit plate 901 to 903 according to embodiment 8, and the inductive circuit flaggy is pressed on first to the laminated sheet of tertiary circuit plate 901 to 903.
Then, behind the formation inductive circuit plate (as described in Example 7), each inductor layer is formed on each inductive circuit plate.That is to say, form inductor layer 950a on the first inductive circuit plate 940a, make predetermined shape as " U " shape.The end points of inductor layer 950a extends to the border of the circuit board that will join with first coupling, opens through hole at the other end of the inductor layer 950a by the first inductive circuit plate 940a again.Similar to the first inductive circuit plate 940a, inductor layer 950b is placed the second inductive circuit plate 940b, make reservation shape.Another edge second coupling relative with being positioned at first coupling that the end of inductor layer 950b extends circuit board joined, and opens through hole at the other end of the inductor layer 950b by the first inductive circuit plate 940b again.Next, with inductor layer 950c with predetermined fixed in shape on the 3rd inductive circuit plate 940c, and on the opposite endpoint of each inductor layer 950c, open through hole, lead to the 3rd inductive circuit plate 940c.Through hole among the 3rd inductive circuit plate 940c and the through hole that is present among first, second inductive circuit plate 940a and the 940b correspond to each other.For inductor layer 950a and 950b are joined each other, the through hole in the inductive circuit plate has all filled up conducting resinl.Meanwhile, in order to ensure being connected firmly between inductor layer 750 and the coupling, before inductor layer 950a and 950b making, load onto metallic gasket in the inductor layer 950a and the corresponding position of 950b one end points that connect first and second couplings.
In fact, after holding through hole successfully on the green circuit plate, in conducting resinl printed inductance layer, also can fill up through hole with conducting resinl.
Shown in Figure 20 (a), laminated chip element according to the present embodiment making, when first press to the tertiary circuit flaggy after, be opposite to first first to the 3rd inductive circuit plate 940a to 940c to the laminated sheet of tertiary circuit plate again and carry out lamination, its lamination is in proper order: the first inductive circuit plate 940a, the 3rd inductive circuit plate 940c, the second inductive circuit plate 940b, and then blank circuit board 900 is laminated to.When first to the 3rd inductive circuit plate (940a to the 940c) lamination, the inductor layer of adjacent inductors circuit board is interconnected with one another by the conducting resinl that is filled within the corresponding through hole.
After circuit board is according to the above-mentioned steps lamination, again through compressing, cutting, roasting, sintering processes, form coupling (processing method was the same with previous embodiment) afterwards, and finish the laminated chip element making.
A plurality of the 3rd inductive circuit plate 940c are between first, second inductive circuit plate 940a and 940b, and one of them end joins with outer terminal and forms input/output terminal respectively.By controlling the number of the 3rd inductive circuit plate 940c, can obtain the inductance coefficent of expection at an easy rate.
Although the inductor layer in the present embodiment is a buckling curve shape, can change during the shape of its inductor layer.For example, the inductor layer that is positioned at each inductive circuit plate can be vertical element shape, as shown in figure 21.Figure 21 is for revising the laminated chip element exploded perspective view of embodiment 9, and wherein inductor layer is reduced to linear.In addition, laminated chip element can also further be simplified making.
Although the element in the present embodiment has the conductive pattern layer identical with embodiment 3, resistive layer on being positioned at blank circuit board is replaced by inductor layer, but also can adopt the method with present embodiment, the resistive layer that is positioned on the stacked wiring board among the embodiment 1 to embodiment 6 is all replaced with inductor layer.
[embodiment 10]
According to embodiments of the invention 10, Figure 22 to Figure 24 has explained the making of laminated chip element.
Figure 22 is a making schematic diagram of making laminated chip element according to present embodiment.Wherein a plurality of unit elements are made as an one chip element as four unit elements are integrated.
The green circuit buttress of expection element is made according to the method identical with embodiment 1.In the present embodiment, can adopt ferrite green circuit plate as the green circuit plate.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say that according to Figure 22 (a), for the first module element, the first conductive pattern layer 1010a that is made up of first to the 3rd section (partly) (1010a1 to 1010a3) is positioned on the first circuit board 1001a.The first, the 3rd section 1010a1 and 1010a3 are separated from one another and radially extend along circuit board 2 opposite end points; Second section 1010a2 links to each other with 1010a3 with first, the 3rd section 1010a1, and second section 1010a2 makes reservation shape as " U " shape and be positioned at outside the unit elements border, and the inductance coefficent that makes the first conductive pattern layer 1010a obtain to expect.Second conductive pattern layer 1011 is positioned on the second circuit board 1002 along first circuit board 1001a two opposite end point horizontal expansions; A pair of then first and second board layers compacting makes an one chip element.
For four unit elements are formed in the one chip element independently of one another, by adopting the method identical, the first conductive pattern layer 1001b to 1001d is formed at the extra first circuit board 1001b to 1001d that is used for second to the 4th unit elements on the green circuit plate with making respectively with first circuit board 1001a.First, the 3rd section with the first conductive pattern layer 1010a to 1010d lays respectively in the border of units corresponding element, that is to say, each of the first conductive pattern layer 1010a to 1010d separately is in first circuit board 2 opposite end points transversely to first, the 3rd section, so that connect corresponding first, second coupling 1030 and 1031.
In the laminated chip element of making according to present embodiment; at first with first circuit board 1001a to 1001d and second circuit board 1002 laminations in case each among the first circuit board 1001a to 1001d all between two second circuit boards; and then will be used to protect the conductive pattern layer on the outermost layer circuit board blank circuit board 1000 laminations its, shown in Figure 22 (a).Except that blank circuit board, also can on the outermost layer circuit board of laminated sheet, add one deck insulating pattern or layer.
After circuit board is according to the above-mentioned steps lamination, again through compressing, cutting, roasting, sintering processes, form coupling (processing method was the same with previous embodiment) afterwards, and finish the laminated chip element making.
Shown in Figure 22 (c), at first on chip component, make four pairs as first and second couplings 1030 of input and output joint and 1031 and as the 3rd coupling 1032 of common terminal, first, the 3rd section of the first conductive pattern layer 1010a to 1010d on each unit elements is connected with 1031 with corresponding first, second coupling 1030, and 2 opposite end points of second conductive pattern layer 1011 and the 3rd coupling 1032 are joined.Arbitrary end points of second conductive pattern layer 1011 optionally is connected with the 3rd coupling.The section of the conductive pattern layer of joining with corresponding coupling partly can not be positioned on the corresponding circuit board edge separation with circuit board.
So present embodiment is with four integrated laminated chip elements that are made into of unit elements, the first circuit board of each unit elements is laminated between the second circuit board.Because the first conductive pattern layer 1010a to 1010d is positioned at first circuit board inequality on each unit elements, each first conductive pattern layer 1010a to 1010d can prolong the bounds that exceeds unit elements, therefore, even each unit elements has the conductive pattern layer of extension, the chip component of making according to the present invention still can closely be arranged.
Shown in Figure 22, each first conductive pattern layer 1010a to 110d is between two second conductive pattern layer 1011; And the unit elements equivalent circuit diagram of Figure 23 for doing according to a pair of first and second circuit boards in the laminated chip element with structure shown in Figure 22.In circuit diagram, input and output side a and b for first, the 3rd section first, second coupling 1030 and 1031 that is connected of the first conductive pattern layer 1010a, the 3rd coupling 1032 that common terminal (grounding electrode) joins for the two opposite ends point with second conductive pattern layer 1011.
In chip component as shown in figure 22, it is to provide an inductor in order to prolong holding wire in the holding wire of series connection that first conductive pattern layer is designed to prolong shape.Because partly being extended of the electric current homophase in holding wire and earth connection, so the resonance frequency FT of the chip component of present embodiment making 0Resonance frequency FT such as traditional punching element shown in Figure 35 is low, as shown in figure 24.The laminated chip element that adopts present embodiment to make, its noise removal characteristic is improved and the absolute value of insertion loss also improves greatly because the equivalent inductance coefficient of holding wire increases.
[embodiment 11]
Present embodiment is described a lamination chip component shown in Figure 25 to 28, it makes change become possibility according to the equivalent inductance coefficient of the direction of electric current process input/output terminal by changing the shape of the conductive pattern layer of joining with common terminal.
Figure 25 is a making schematic diagram of making laminated chip element according to present embodiment.Wherein will be alone unit elements, as four unit elements, integratedly be made as an one chip element.
The green circuit buttress of expectation element is made according to the method identical with embodiment 1.Adopted ferrite green circuit plate as the green circuit plate in the present embodiment.
Conductive pattern layer is positioned on the green circuit board, for example can adopt that screen plate printing method is printed on conducting glue Ag, Pt and Pd etc. on the green circuit plate, and it can utilize the web plate that had for example before designed the tool internal electrode pattern.This that is to say, at first, makes first conductive pattern layer 1110 and extend along the direction of 1101 liang of opposite side of first circuit board on first circuit board 1101; On second circuit board 1102, make then second conductive pattern layer 1111 and with first conductive pattern layer 1110 in the same way.The two opposite ends point of first conductive pattern layer 1110 extends to the both sides of circuit board 1101 and joins with first, second coupling 1130 and 1130, form input/output terminal, and one of end points of second conductive pattern layer 1111 joins with any or two point modes with common terminal.The part of the conductive pattern layer of joining with corresponding coupling can not extend to the edge of circuit board.
When a plurality of unit elements are made into laminated chip element as four unit elements are integrated, at first first, second conductive pattern layer 1110 and 1111 is formed parallel to each other on first, second circuit board 1101 and 1102 many.Each first conductive pattern layer 1110 all independently is in the scope of each unit elements, and chip component is drawn lead with two point it is separately formed unit elements.But, can preferablely earlier many end points to second conductive pattern layer 1111 be interconnected herein, and then receive on the common terminal.At last, shown in Figure 25 (a), interconnect with an end points with second conductive pattern layer 1111 of first conductive pattern layer 1110 along equidirectional formation a plurality of earlier, the extension of two outermost end of second conductive pattern layer 1111 is joined with the 3rd coupling then.In addition, two outermost end of also extensible second conductive pattern layer 1111 wherein join by any one and the 3rd coupling.
Be laminated at first with two first circuit boards 1101 and two second circuit boards 1102 lamination alternately, and then with blank circuit board 1100.Although but two first circuit boards and two second circuit boards are crosswise laminations in the present embodiment, the lamination quantity of first, second circuit board is also unrestricted.Next, carry out such as treatment steps such as compacting, cutting, roasting, sintering, form coupling, the completing of laminated chip element according to method same among the previous embodiment.
Figure 26 is the equivalent circuit diagram of unit elements in the laminated chip element in the present embodiment.From circuit diagram as can be known, the two opposite ends point of input/output terminal a and b and first, second coupling 1130 and 1131 and first conductive pattern layer 1110 joins, and common terminal (grounding electrode) also the two opposite ends point of i.e. the 3rd coupling 1132 and second conductive pattern layer 1111 join.
With reference to Figure 27 present embodiment is made the explanation of operating about laminated chip element, be readily appreciated that the equivalent inductance coefficient changes along with the direction of first, second coupling of electric current process laminated chip element.If voltage puts on first conductive pattern layer 1110 as holding wire shown in Figure 27 (a), electric current I 1 flow to the lower left to; If the voltage picture puts on first conductive pattern layer 1110 as holding wire shown in Figure 27 (b), electric current I 3 flow to the lower right to.Because an end points of second conductive pattern layer 1111 such as earth connection and common terminal join, thus in Figure 27 (a) and 27 (b), two examples, electric current I 2 and I4 in second conductive pattern layer 1111 all the time towards the lower left to stream.Because the electric current I 1 of signal and earth connection and I2 direction are in the same way, so the equivalent inductance coefficient of the laminated chip element shown in Figure 27 (a) is maximum, and because the electric current I 3 and the I4 direction of signal and earth connection are reverse, so the equivalent inductance coefficient of the laminated chip element shown in Figure 27 (b) is minimum.
In addition, though do not mark in the drawings, if two second circuit boards 1102 between two first circuit boards 1101 because the high frequency noise signal frequency range that can pass through is widened, the insertion loss characteristic will improve.
Figure 28 is the laminated chip element frequency characteristic curve diagram according to 11 embodiment of the present invention and the making of employing prior art.As described above, the equivalent inductance coefficient changes according to sense of current in the present embodiment laminated chip element holding wire.That is to say, because the equivalent inductance coefficient of leftmost cell element reaches maximization among Figure 26, the resonance frequency FT1 of leftmost cell element is lower than the resonance frequency FT of traditional punching element, on the other hand, since among Figure 26 the equivalent inductance coefficient of right unit elements reach and minimize, the resonance frequency FT2 of right unit elements is than the resonance frequency FT height of traditional punching element.Therefore, the direction of element should obviously mark at the outer surface of element as the direction of input, output signal.
In the laminated chip element of present embodiment,, be possible so obtain the desired frequency characteristic because the inductance coefficent of element can be controlled through first, second coupling sense of current by control.
[embodiment 12]
Embodiment 12 is that of embodiment 11 improves embodiment, and shown in Figure 29 to 31, the laminated chip element of this embodiment has high insertion loss, and it is applicable to the circuit of low noise frequency range.
Except that second conductive pattern layer 1211 was distinguished to some extent, embodiment 12 was similar to embodiment 11 on the chip structure.Specifically, first conductive pattern layer 1210 is positioned on the first circuit board 1201 and along 1201 liang of relative edges circle of first circuit board radially extends, and second conductive pattern layer 1211 is positioned on the second circuit board 1202 and with first conductive pattern layer 1210 and is in same direction.In addition, the center end points extension of second conductive pattern layer 1211 is to joining with the 3rd coupling 1231 (being common terminal), and promptly second conductive pattern layer, 1211 centers, two corresponding points are extended down to outward with the 3rd coupling 1231 and join.Perhaps, a contact and the 3rd coupling 1231 that is positioned at second conductive pattern layer, 1211 centers joined.Shown in Figure 29 (a), when a plurality of unit elements are integrated when being made as the one chip element in parallel to each other, second conductive pattern layer 1211 is designed to cross so that can join each other and join with the 3rd coupling 1231 with its center separately.The part of the conductive pattern layer of joining with corresponding coupling can the outer border that be extended down to circuit board.
At first, first, second circuit board 1201 with 1202 and blank circuit board 1200 adopt the identical method lamination of embodiment 11; Then, again through the processing identical with previous embodiment as compress, cutting, roasting, sintering, after forming external end points, make and finish laminated chip element.
The operating process that Figure 30 makes laminated chip element to present embodiment makes an explanation.When first, second coupling that the two opposite ends point that applies voltages to any one first conductive pattern layer 1210 (making holding wire) joins, the electric current I in first conductive pattern layer 1210 will flow to the lower left to, as shown in figure 30.Join with ground contact such as common terminal because be used as second conductive pattern layer, 1211 centers of earth connection, so electric current I a in second conductive pattern layer 1211 and Ib flow to its center.Because the electric current I a of holding wire and earth connection is identical with the direction of Ib, the equivalent inductance coefficient of part reaches maximum so electric current I a flows through; And because the direction of the electric current I a of holding wire and earth connection and Ib is opposite, the flow through equivalent inductance coefficient of part of current Ib then reaches minimum.Because of the equivalent inductance coefficient at two places is offset each other, have only second conductive pattern layer, 1211 centerline to have unique inductance, wherein center line by the part that connects second conductive pattern layer be connected one of second conductive pattern layer outermost end and formed with the part of the 3rd coupling.
In addition, if a plurality of second circuit boards 1202 (are not marked among the figure) between two first circuit boards 1201, because the high frequency noise signal passes through scope broadening, insertion loss character will be improved.
Figure 31 is the laminated chip element frequency characteristic curve diagram according to 11 embodiment of the present invention and the making of employing prior art.As shown in figure 31, the resonance frequency FT3 of the laminated chip element of making according to present embodiment is lower than the resonance frequency FT of traditional punching element, this also is that the inductance of the centerline of second conductive pattern layer 1211 among Figure 29 still is retained in the reason in the element, and traditional punching element is because holding wire and earth connection are 90 degrees to each other the existence that intersection does not almost have equivalent inductance.Therefore, on the basis of keeping with the insertion loss of the identical level of traditional punching element and noise removal characteristic, the laminated chip element that present embodiment is made can preferablely be applicable in the lower circuit of frequency noise scope.
In order to make element obtain the frequency properties of expection, center and the common terminal with second conductive pattern layer 1211 joins in the present embodiment, but another correct position that is positioned at 1211 liang of opposite end points of second conductive pattern layer also can join with common terminal.
[embodiment 13]
Present embodiment is the improvement embodiment of embodiment 11 and embodiment 12.Present embodiment is shown in Figure 32 to 34.The laminated chip element that adopts present embodiment to make has lower resonant frequency and has but kept characteristics such as noise removal character, insertion loss.That is to say that the laminated chip element that present embodiment is made has improved the equivalent inductance coefficient for the character that obtains the front.At last, the conductive pattern layer that connects common terminal is transformed, so that make the electric current of holding wire and earth connection not be subjected to the influence of the input/output terminal sense of current all the time along same direction.
Similar, only different on conductive pattern layer 1311 in the structure of embodiment 13 chips elements and embodiment 11 and 12.
Shown in Figure 32 (a), at first on first circuit board 1301, form first conductive pattern layer 1310 and radially extend along two relative edges of first circuit board 1301; On second circuit board 1302, form second conductive pattern layer 1311 along first conductive pattern layer 1310 equidirectional again.In addition, the making of second conductive pattern layer 1311 also is can join as common terminal with the 3rd coupling 1332 for the 2 opposite end points that make second conductive pattern layer 1311.When a plurality of unit elements were integrated into laminated chip element in parallel with each other as four unit elements, two outermost two opposite endpoint of second conductive pattern layer 1311 connected the second circuit board 1302 that is connected with the 3rd coupling 1332; And the opposite endpoint of the end points of another second conductive pattern layer and adjacent second conductive pattern layer is joined each other.The part of the conductive pattern layer of joining with corresponding coupling can not be extended down to the border of circuit board outward.
At first, first, second circuit board 1301 with 1302 and blank circuit board 1300 adopt the embodiment 11 method lamination identical with 12; Then, again through the processing identical with previous embodiment as compress, cutting, roasting, sintering, form external end points after, make and finish laminated chip element.
The operating process that Figure 33 makes laminated chip element to present embodiment makes an explanation.When first, second coupling that the two opposite ends point that applies voltages to any one first conductive pattern layer 1310 (holding wire) joins, the electric current I in first conductive pattern layer 1310 will flow to the lower left to, as shown in figure 33.Meanwhile, around first conductive pattern layer 1310, will produce magnetic field, and be arranged on first conductive pattern layer 1310 or under second conductive pattern layer 1311 produce and electric current I has the induced current Ii of equidirectional.Because electric current I and Ii are in the same way, the equivalent inductance coefficient reaches maximum.Figure 34 is for being the laminated chip element frequency characteristic curve diagram according to 13 embodiment of the present invention and the making of employing prior art.The resonance frequency FT of the laminated chip element of making according to present embodiment 4Resonance frequency FT than traditional punching element is low.Therefore, on the basis of keeping with the insertion loss of the identical level of traditional punching element and noise removal characteristic, the laminated chip element that present embodiment is made can preferablely be applicable in the lower circuit of frequency noise scope.
In addition, if a plurality of second circuit boards 1302 (are not marked among the figure) between two first circuit boards 1301, because the high frequency noise signal passes through scope broadening, insertion loss character will be improved.
In the foregoing description 1 to 13, all to make rheostatic green circuit plate.If some conductive pattern layer are via using resistive paste such as Ni-Cr and RuO 2Form Deng printing, laminated chip element is then for being associated with the varistor element of resistor.Therefore, when overvoltage acts on circuit, the current direction common terminal in the element and circuit is protected under the condition of overvoltage.Because can adopt some conductive pattern layer of making such as metal material such as Ag, Pt and Pd to improve conductivity, or adopt resistance material such as Ni-Cr and RuO 2The impedance matching of circuit reduces conductivity Deng some conductive pattern layer of making, so can both be easy to adjust.In addition; if conductive pattern layer and resistance pattern layer are formed on the green circuit plate of PTC themistor or NTC themistor; then laminated chip element then becomes the thermistor that has resistor, and it can protective circuit be subjected to overcurrent or temperature is fast-changing influences.
Laminated chip element of the present invention makes control capacitance, resistance and inductance to desired value and improve frequency properties such as noise removal and insertion loss etc. become possibility.In addition, laminated chip element structure of the present invention protects main electronic component such as semiconductor integrated circuit to exempt from the infringement of static and overvoltage effectively.
More very the person is not increasing under any other program step, the invention enables the laminated chip element of resistor or inductor can make fine and closely and frivolous.In addition, also just because of the present invention can simplify the making of laminated chip element, so the expense of production process also decreases.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Should be included in the Korean Patent KR10-2003-0052561 that delivered on July 30th, 2003 and the content of KR10-2003-0052562 with invention, and its whole contents is incorporated reference at this.

Claims (16)

1, a kind of laminated chip element, it comprises a plurality of unit elements, it is characterized in that comprising:
Be formed with at least one first circuit board of first, second how right conductive pattern layer, wherein each right aforementioned first, second conductive pattern layer is separate and be arranged on the two-end-point of aforementioned first circuit board, and each right aforementioned first, second conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one second circuit board of the 3rd conductive pattern layer, wherein aforementioned the 3rd conductive pattern layer laterally is formed on the aforementioned unit elements aforementioned first circuit board two-end-point; And
A plurality of resistance patterns are formed on aforementioned first and second circuit boards corresponding to aforementioned unit elements;
Wherein one of aforementioned first, second conductive pattern layer end points joins with first, second coupling respectively; wherein aforementioned first, second coupling is respectively input and out splice going splice; aforementioned the 3rd conductive pattern layer has at least an end points and the 3rd coupling to join; wherein aforementioned the 3rd coupling is an earth terminal; the two-end-point of each aforementioned resistance pattern joins with aforementioned first, second coupling respectively; and aforementioned first and second circuit boards are by lamination, and a protection insulating barrier is formed at by the top of one of them of laminated circuit plate.
2, a kind of laminated chip element, it comprises a plurality of unit elements, it is characterized in that comprising:
Be formed with at least one first circuit board of first, second how right conductive pattern layer, wherein each right aforementioned first, second conductive pattern layer is separate and be arranged on the two-end-point of aforementioned first circuit board, and each right aforementioned first, second conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one second circuit board of the 3rd conductive pattern layer, wherein aforementioned the 3rd conductive pattern layer laterally is formed on the aforementioned unit elements aforementioned first circuit board two-end-point; And
A plurality of inductive patterns are formed on aforementioned first and second circuit boards corresponding to aforementioned unit elements;
Wherein one of aforementioned first, second conductive pattern layer end points joins with first, second coupling respectively; wherein aforementioned first, second coupling is respectively input and out splice going splice; aforementioned the 3rd conductive pattern layer has at least an end points and the 3rd coupling to join; wherein aforementioned the 3rd coupling is an earth terminal; the two-end-point of each aforementioned inductive patterns joins with aforementioned first, second coupling respectively; and aforementioned first and second circuit boards are by lamination, and a protection insulating barrier is formed at by the top of one of them of laminated circuit plate.
3, a kind of laminated chip element, it comprises a plurality of unit elements, it is characterized in that comprising:
Be formed with at least one first circuit board of a plurality of first conductive pattern layer, wherein aforementioned first conductive pattern layer is formed on the direction of two-end-point of aforementioned first circuit board, and each aforementioned first conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one second circuit board of a plurality of second conductive pattern layer, wherein aforementioned second conductive pattern layer is formed on the direction identical with aforementioned first conductive pattern layer, and each aforementioned second conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one tertiary circuit plate of the 3rd conductive pattern layer, wherein aforementioned the 3rd conductive pattern layer comprise be formed at and the aforementioned first conductive pattern layer equidirectional a plurality of first partly and be connected aforementioned first partly an end points second partly, each aforementioned first partly is set in each aforementioned unit elements, aforementioned second laterally being formed on the aforementioned unit elements at aforementioned first circuit board two-end-point partly; And
A plurality of resistance patterns are formed at aforementioned first to the tertiary circuit plate corresponding to aforementioned unit elements;
Wherein aforementioned first; 2 opposite end points of second conductive pattern layer are respectively with first; second coupling is joined; wherein aforementioned first; second coupling is respectively input and out splice going splice; aforementioned second of aforementioned the 3rd conductive pattern layer partly has at least an end points and the 3rd coupling to join; wherein aforementioned the 3rd coupling is an earth terminal; the two-end-point of each aforementioned resistance pattern is respectively with aforementioned first; second coupling is joined; and aforementioned first to the tertiary circuit plate by lamination so that at least one aforementioned tertiary circuit plate is inserted in aforementioned first; between the second circuit board, and a protection insulating barrier is formed at by the top of one of them of laminated circuit plate.
4, a kind of laminated chip element, it comprises a plurality of unit elements, it is characterized in that comprising:
Be formed with at least one first circuit board of a plurality of first conductive pattern layer, wherein aforementioned first conductive pattern layer is formed on the direction of two-end-point of aforementioned first circuit board, and each aforementioned first conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one second circuit board of a plurality of second conductive pattern layer, wherein aforementioned second conductive pattern layer is formed on the direction identical with aforementioned first conductive pattern layer, and each aforementioned second conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one tertiary circuit plate of the 3rd conductive pattern layer, wherein aforementioned the 3rd conductive pattern layer comprise be formed at and the aforementioned first conductive pattern layer equidirectional a plurality of first partly and be connected aforementioned first partly an end points second partly, each aforementioned first partly is set in each aforementioned unit elements, aforementioned second laterally being formed on the aforementioned unit elements at aforementioned first circuit board two-end-point partly; And
A plurality of inductive patterns are formed at aforementioned first to the tertiary circuit plate corresponding to aforementioned unit elements;
Wherein aforementioned first; 2 opposite end points of second conductive pattern layer are respectively with first; second coupling is joined; wherein aforementioned first; second coupling is respectively input and out splice going splice; aforementioned second of aforementioned the 3rd conductive pattern layer partly has at least an end points and the 3rd coupling to join; wherein aforementioned the 3rd coupling is an earth terminal; the two-end-point of each aforementioned inductive patterns is respectively with aforementioned first; second coupling is joined; and aforementioned first to the tertiary circuit plate by lamination so that at least one aforementioned tertiary circuit plate is inserted in aforementioned first; between the second circuit board, and a protection insulating barrier is formed at by the top of one of them of laminated circuit plate.
5, a kind of laminated chip element, it comprises a plurality of unit elements, it is characterized in that comprising:
Be formed with at least one first circuit board of a plurality of first conductive pattern layer, wherein each aforementioned first conductive pattern layer is partly formed by first to the 3rd, it is aforementioned that first, second is partly separate and be arranged on the two-end-point of aforementioned first circuit board, the aforementioned the 3rd partly with aforementioned first, second partly separate and be formed at aforementioned first circuit board two-end-point transversely, each aforementioned first conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one second circuit board of a plurality of second conductive pattern layer, wherein each aforementioned second conductive pattern layer is made up of with the 5th part institute the 4th separate part, the aforementioned the 4th partly partly overlaps with the aforementioned the first, the 3rd, the aforementioned the 5th partly partly overlaps with aforementioned second, third, and each aforementioned second conductive pattern layer is set in each aforementioned unit elements; And
A plurality of resistance patterns are formed on aforementioned first and second circuit boards corresponding to aforementioned unit elements;
Wherein aforementioned first; one of second part end points is respectively with first; second coupling is joined; wherein aforementioned first; second coupling is respectively input and out splice going splice; the aforementioned the 3rd partly is connected to each other on aforementioned unit elements; the 3rd part that has connected has at least an end points and the 3rd coupling to join; wherein aforementioned the 3rd coupling is an earth terminal; the two-end-point of each aforementioned resistance pattern is respectively with aforementioned first; second coupling is joined; and aforementioned first and second circuit boards are by lamination, and a protection insulating barrier is formed at by the top of one of them of laminated circuit plate.
6, a kind of laminated chip element, it comprises a plurality of unit elements, it is characterized in that comprising:
Be formed with at least one first circuit board of a plurality of first conductive pattern layer, wherein each aforementioned first conductive pattern layer is partly formed by first to the 3rd, it is aforementioned that first, second is partly separate and be arranged on the two-end-point of aforementioned first circuit board, the aforementioned the 3rd partly with aforementioned first, second partly separate and be formed at aforementioned first circuit board two-end-point transversely, each aforementioned first conductive pattern layer is set in each aforementioned unit elements;
Be formed with at least one second circuit board of a plurality of second conductive pattern layer, wherein each aforementioned second conductive pattern layer is made up of with the 5th part institute the 4th separate part, the aforementioned the 4th partly partly overlaps with the aforementioned the first, the 3rd, the aforementioned the 5th partly partly overlaps with aforementioned second, third, and each aforementioned second conductive pattern layer is set in each aforementioned unit elements; And
A plurality of inductive patterns are formed on aforementioned first and second circuit boards corresponding to aforementioned unit elements;
Wherein aforementioned first; one of second part end points is respectively with first; second coupling is joined; wherein aforementioned first; second coupling is respectively input and out splice going splice; the aforementioned the 3rd partly is connected to each other on aforementioned unit elements; the 3rd part that has connected has at least an end points and the 3rd coupling to join; wherein aforementioned the 3rd coupling is an earth terminal; the two-end-point of each aforementioned inductive patterns is respectively with aforementioned first; second coupling is joined; and aforementioned first and second circuit boards are by lamination, and a protection insulating barrier is formed at by the top of one of them of laminated circuit plate.
7,, it is characterized in that the area of overlapped part between the aforementioned conductive pattern layer is different each other according to each described laminated chip element in the claim 1 to 6.
8,, it is characterized in that having two metallic gaskets and isolation mutually, and aforementioned resistance design producing is for connecting aforementioned two metallic gaskets according to each described laminated chip element in the claim 1,3,5.
9,, it is characterized in that having two metallic gaskets and isolation mutually, and aforementioned inductance design producing is for connecting aforementioned two metallic gaskets according to each described laminated chip element in the claim 2,4,6.
10,, it is characterized in that aforementioned protection insulating barrier comprises epoxy resin or glass according to each described laminated chip element in the claim 1 to 6.
11, according to each described laminated chip element in the claim 2,4,6, it is characterized in that the inductive patterns of the aforementioned unit elements of part is formed at the upper surface of aforementioned laminated chip element, and the inductive patterns of the aforementioned unit elements of another part is formed at the lower surface of aforementioned laminated chip element.
12, according to each described laminated chip element in the claim 2,4,6, it is characterized in that aforementioned inductive patterns is spiral, across the spirality inductive patterns an insulative bridge radially arranged, and a bridge shape pattern is formed on the insulative bridge and in order to the central end points that extends inductive patterns to its outside.
13, according to each described laminated chip element in the claim 2,4,6, it is characterized in that one deck ferrous acid salt deposit is arranged on aforementioned laminated chip element, aforementioned inductive patterns then is positioned on the ferrous acid salt deposit.
14,, it is characterized in that aforementioned inductive patterns comprises resistance material such as nickel-chromium (Ni-Cr) or ruthenium-oxide (RuO according to each described laminated chip element in the claim 2,4,6 2).
15, according to each described laminated chip element in the claim 2,4,6, it is characterized in that a plurality of inductive circuit plates are by further lamination, on each aforementioned electric inductive circuit plate an inductive patterns is arranged, the two-end-point of aforementioned inductive patterns joins with the first and second corresponding couplings respectively.
16, according to each described laminated chip element in the claim 2,4,6, it is characterized in that a plurality of inductive circuit plates are by further lamination, on each aforementioned electric inductive circuit plate an inductive patterns is arranged, it is contacted mutually by a series of through hole that is positioned on the aforementioned electric inductive circuit plate each other, and the two-end-point of interconnective inductive patterns joins with first and second couplings respectively.
CN2008101809357A 2003-07-30 2004-07-15 Complex laminated chip element Expired - Fee Related CN101447336B (en)

Applications Claiming Priority (6)

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KR1020030052562 2003-07-30
KR1020030052562A KR100470116B1 (en) 2003-07-30 2003-07-30 Complex laminated chip element
KR1020030052561 2003-07-30
KR10-2003-0052562 2003-07-30
KR1020030052561A KR100470115B1 (en) 2003-07-30 2003-07-30 Laminated chip element with various equivalent inductance
KR10-2003-0052561 2003-07-30

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TWI762837B (en) * 2019-05-23 2022-05-01 大陸商雲谷（固安）科技有限公司 Flexible display mother board and flexible display mother board manufacturing method
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CN103050761A (en) * 2011-10-14 2013-04-17 钰铠科技股份有限公司 Manufacturing process of multi-layer balance-to-unbalance converter
CN108806954A (en) * 2017-05-02 2018-11-13 太阳诱电株式会社 Magnetic coupling type coil component
CN108806954B (en) * 2017-05-02 2023-03-21 太阳诱电株式会社 Magnetic coupling type coil component
TWI762837B (en) * 2019-05-23 2022-05-01 大陸商雲谷（固安）科技有限公司 Flexible display mother board and flexible display mother board manufacturing method
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CN117459021B (en) * 2023-11-17 2024-05-10 华南理工大学 Bulk acoustic wave monolithic hybrid filter integrated with passive device and preparation method thereof

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