CN101442060B - Pixel array and method of manufacturing the same - Google Patents
Pixel array and method of manufacturing the same Download PDFInfo
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- CN101442060B CN101442060B CN2008101905119A CN200810190511A CN101442060B CN 101442060 B CN101442060 B CN 101442060B CN 2008101905119 A CN2008101905119 A CN 2008101905119A CN 200810190511 A CN200810190511 A CN 200810190511A CN 101442060 B CN101442060 B CN 101442060B
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Abstract
The invention provides a pixel array and a method for manufacturing the same. The pixel array comprises a substrate, a plurality of scan lines and data lines, a plurality of active elements, a plurality of first connecting pads and second connecting pads, a plurality of first wirings and second wirings, an insulation layer, an organic flat layer, a plurality of first connecting pad electrodes, a plurality of second connecting pad electrodes, and a plurality of pixel electrodes; the substrate comprises a display zone and a non-display zone; the active elements are arranged in the display zone and electrically connected with the scan lines and the data wires; the first and the second connecting pads are arranged in the non-display zone; the first and the second wirings are arranged in the non-display zone, and connected with the first and the second connecting pads respectively; the organic flat layer covers the insulation layer; and the first and the second connecting pad electrodes are arranged on the organic flat layer in the non-display zone. Under conditions of not adding technical steps and keeping the organic flat layer, the invention effectively solve the problem that the pad connection of a first metal layer and a second metal layer fails due to the disconnection of the connecting pad electrodes generated in the redoing step of bonding of the known chips.
Description
Technical field
The invention relates to a kind of semiconductor device array structure (semiconductor element arraystructure), and particularly relevant for a kind of pel array (pixel array) and manufacture method thereof that can improve the production yield of liquid crystal panel (Liquid Crystal Displaypanel, LCD panel).
Background technology
In general, display panels is made of thin-film transistor array base-plate, liquid crystal layer and colored optical filtering substrates.In the step of making thin-film transistor array base-plate, can on substrate, carry out the making of a plurality of pixels simultaneously earlier usually, and in time in pel array technology, directly on substrate, make connection pad and and measurement circuit.Whether connection pad will be electrically connected with chip follow-up, and the function of measurement circuit mainly is that a test voltage is put on each pel array, can normally operate with the pixel that detects in the pel array.Usually, with after chip join is to substrate, can carry out testing procedure.If it is undesired that test result shows, need carry out heavy industry to chip join so, and repeat testing procedure again.Yet in the design architecture of present pel array, the problem that the heavy industry step of chip join may cause connection pad to lose efficacy is described in detail as follows.
Figure 1A is the generalized section of one of them connection pad of an existing pel array, and Figure 1B is the schematic diagram after the pel array of Figure 1A engages with the chip heavy industry.Please refer to Figure 1A, the connection pad 10 of existing pel array comprises the first metal layer 30 and second metal level 40, a gate insulation layer 50, an insulating barrier 60, one organic flatness layer 70 and a connection pad electrode 80 that is positioned on the substrate 20.Gate insulation layer 50 is between the first metal layer 30 and second metal level 40.Insulating barrier 60 covers the first metal layer 30 and second metal levels 40 with organic flatness layer 70, and insulating barrier 60 and organic flatness layer 70 have first contact openings 72 and second contact openings 74.Connection pad electrode 80 sees through first contact openings 72 and is electrically connected with second metal level 40 with the first metal layer 30 respectively with second contact openings 74.Follow-up chip (not illustrating) will be engaged on the substrate 20, so that chip electrically contacts with connection pad electrode 80.See through connection pad electrode 80, chip can be electrically connected with the first metal layer 30, second metal level 40 of connection pad 10.
Because connection pad electrode 80 is formed on the surface of organic flatness layer 70, and because the adhesion strength deficiency between organic flatness layer 70 and the inorganic insulation layer 70.Therefore when chip join is on connection pad electrode 80 after, as carrying out heavy industry with chip when connection pad electrode 80 is pulled out, organic flatness layer 70 is come off, and then the phenomenon that causes connection pad electrode 80 ' to break from inorganic insulation layer 60.Thus, will make to be electrically connected between the first metal layer 30 and second metal level 40, and cause connection pad 10 to lose efficacy.
Certainly, in other prior aries, produce the phenomenon of connection pad electrode 80 broken strings during for fear of the heavy industry step of carrying out chip join, also have the organic flatness layer 70 on the connection pad 10 is removed.Yet, organic flatness layer 70 be removed and technology need be removed in addition, so will expend more manufacturing cost and time.
Summary of the invention
The invention provides a kind of pel array, in the time of can solving the heavy industry step of carrying out chip join, cause the problem of connection pad inefficacy because of connection pad electrode broken string.
The invention provides a kind of manufacture method of pel array,, solve when carrying out the heavy industry step of chip join, cause the problem of connection pad inefficacy because of connection pad electrode broken string with under the situation that does not increase processing step.
The invention provides a kind of pel array, it comprises a substrate, multi-strip scanning line and many data wires, a plurality of active element, a plurality of first connection pad and a plurality of second connection pads, many first distributions and many second distributions, an insulating barrier, an organic flatness layer, a plurality of first connection pad electrode, a plurality of second connection pad electrodes and a plurality of pixel electrodes.Substrate has a viewing area and a non-display area.Scan line and data line bit are in the viewing area.Active element is arranged in the viewing area and is electrically connected with data wire with scan line.First connection pad and second connection pad are arranged in non-display area, wherein first connection pad and the configuration interlaced with each other of second connection pad, and first connection pad and second connection pad belong to different retes.First distribution is positioned at non-display area with second distribution and is connected with first connection pad and second connection pad respectively, and wherein the material of first distribution is identical with the material of first connection pad, and the material of second distribution is identical with the material of second connection pad.Insulating barrier cover data line, scan line, active element, first connection pad, second connection pad, first distribution and second distribution.Organic flatness layer covers insulating barrier, has a plurality of first contact openings, a plurality of second contact openings and a plurality of the 3rd contact openings in wherein organic flatness layer and the insulating barrier.First contact openings exposes first connection pad, and second contact openings exposes second connection pad, and the 3rd contact openings exposes the part of active element.The first connection pad electrode is positioned on organic flatness layer of non-display area, and the first connection pad electrode is electrically connected with first connection pad by first contact openings.The second connection pad electrode is positioned on organic flatness layer of non-display area, and the second connection pad electrode is electrically connected with second connection pad by second contact openings.Pixel electrode is positioned on organic flatness layer of viewing area, and pixel electrode is electrically connected with active element by the 3rd contact openings.
In one embodiment of this invention, the material of the material of the first above-mentioned connection pad and second connection pad is inequality.
In one embodiment of this invention, the first above-mentioned distribution is electrically connected with data wire with second distribution.
In one embodiment of this invention, the first above-mentioned distribution is electrically connected with scan line with second distribution.
In one embodiment of this invention, some is electrically connected with data wire in the first above-mentioned distribution and second distribution, and another part is electrically connected with scan line.
In one embodiment of this invention, the thickness of the above-mentioned organic flatness layer that is positioned at non-display area is less than the thickness of the organic flatness layer that is positioned at the viewing area.
In one embodiment of this invention, above-mentioned pel array more comprises many first wiring and many second wiring.First wiring and second wiring are arranged in non-display area, and first wiring is electrically connected with first connection pad, and second wiring is electrically connected with second connection pad.
In one embodiment of this invention, above-mentioned at non-display area organic flatness layer and insulating barrier in more comprise a plurality of the 4th contact openings.The 4th contact openings exposes first wiring, and the first connection pad electrode is electrically connected with first wiring by the 4th contact openings.
In one embodiment of this invention, above-mentioned substrate more comprises the test section, and the test section has a plurality of switch elements.Switch element reaches with first wiring and is electrically connected with second wiring.
In one embodiment of this invention, above-mentioned pel array more comprises a plurality of testing elements.Testing element is positioned at the test section, and testing element is electrically connected with switch element.
In one embodiment of this invention, above-mentioned substrate more comprises the test section, and the test section has a plurality of testing elements.Testing element reaches with first wiring and is electrically connected with second wiring.
The present invention proposes a kind of manufacture method of pel array.At first, provide a substrate.Substrate has a viewing area and a non-display area.Then, a plurality of active elements that in the viewing area, form multi-strip scanning line, many data wires and be electrically connected with scan line and data wire.Then, a plurality of first connection pads that in non-display area, form many first distributions simultaneously and be connected with first distribution.Then, a plurality of second connection pads that in non-display area, form many second distributions simultaneously and be connected with second distribution, wherein first connection pad and second connection pad belong to different retes, and first connection pad and the configuration interlaced with each other of second connection pad.Then, on substrate, form an insulating barrier.Insulating barrier cover data line, scan line, active element, first connection pad, second connection pad, first distribution and second distribution.Then, on insulating barrier, form an organic flatness layer, have a plurality of first openings, a plurality of second opening and a plurality of the 3rd opening in wherein organic flatness layer.Then, with organic flatness layer as etch mask etching insulating barrier, to form a plurality of first contact openings, a plurality of second contact openings and a plurality of the 3rd contact openings.First contact openings exposes first connection pad, and second contact openings exposes second connection pad, and the 3rd contact openings exposes the part of active element.Then, on organic flatness layer of non-display area, form a plurality of first connection pad electrodes and a plurality of second connection pad electrode, and on organic flatness layer of viewing area, form a plurality of pixel electrodes.The first connection pad electrode is electrically connected with first connection pad by first contact openings.The second connection pad electrode is electrically connected with second connection pad by second contact openings.Pixel electrode is electrically connected with active element by the 3rd contact openings.
In one embodiment of this invention, the material of the material of the first above-mentioned connection pad and second connection pad is inequality.
In one embodiment of this invention, the first above-mentioned distribution is electrically connected with data wire with second distribution.
In one embodiment of this invention, the first above-mentioned distribution is electrically connected with scan line with second distribution.
In one embodiment of this invention, some is electrically connected with data wire in the first above-mentioned distribution and second distribution, and another part is electrically connected with scan line.
In one embodiment of this invention, the manufacture method of above-mentioned pel array more comprises the local thickness of the organic flatness layer that removes non-display area, so that the thickness of organic flatness layer that is positioned at non-display area is less than the thickness of the organic flatness layer that is positioned at the viewing area.
In one embodiment of this invention, the manufacture method of above-mentioned pel array more is included in and forms many first wiring and many second wiring in the non-display area.First wiring is electrically connected with first connection pad.Second wiring is electrically connected with second connection pad.
In one embodiment of this invention, the manufacture method of above-mentioned pel array more is included in and forms a plurality of the 4th contact openings in organic flatness layer of non-display area and the insulating barrier, and the first connection pad electrode is by the 4th contact openings and be electrically connected with first wiring.
In one embodiment of this invention, above-mentioned substrate more comprises the test section, and method more is included in the test section and forms a plurality of switch elements.Switch element is electrically connected with first wiring and second wiring.
In one embodiment of this invention, the manufacture method of above-mentioned pel array more is included in the test section and forms a plurality of testing elements, and testing element is electrically connected with switch element.
In one embodiment of this invention, above-mentioned substrate has more a test section, and method more is included in the test section and forms a plurality of testing elements.Testing element reaches with first wiring and is electrically connected with second wiring.
Based on above-mentioned, connection pad of the present invention does not need to see through the connection pad electrode and is electrically connected two metal levels, does not therefore have connection pad electrode broken string and cause the problem of connection pad inefficacy when carry out the heavy industry step of chip join.In addition, the manufacture method of pel array of the present invention, can not increase under processing step and the situation that keeps organic flatness layer, effectively solve heavy industry step that known chip engages and have the first metal layer and second metal level cause the connection pad inefficacy because of connection pad electrode broken string problem.
Description of drawings
Figure 1A is the generalized section of one of them connection pad of an existing pel array.
Figure 1B is the schematic diagram after the pel array of Figure 1A engages with the chip heavy industry.
Fig. 2 A be one embodiment of the invention a kind of pel array on look schematic diagram.
Fig. 2 B is the non-display area of Fig. 2 A substrate and the enlarged diagram of test section.
Fig. 2 C is along the line II-II of line I-I, Fig. 2 B of Fig. 2 A and the generalized section that line III-III is illustrated.
Fig. 2 D is the schematic diagram of the non-display area of the chip substrate that is covered in Fig. 2 A.
Fig. 2 E is the schematic diagram of a kind of pel array of another embodiment of the present invention.
Fig. 2 F puts a kind of non-display area of pel array point substrate of another embodiment and the enlarged diagram of test section for the present invention.
Fig. 3 A to Fig. 3 H puts the generalized section of the manufacture method of the fixed a kind of pel array of an embodiment for the present invention.
Drawing reference numeral:
10: connection pad
20: substrate
22: non-display area
30: the first metal layer
40: the second metal levels
50: gate insulation layer
60: insulating barrier
70: organic flatness layer
72: the first contact openings
74: the second contact openings
80,80 ': the connection pad electrode
100: pel array
110: substrate
112: the viewing area
114: non-display area
116: the test section
116a: switch element
116b: first testing element
116c: second testing element
116d: the 3rd testing element
120: active element
130a: first connection pad
130b: second connection pad
140a: first distribution
140b: second distribution
150: insulating barrier
160: organic flatness layer
162: the first openings
162a: first contact openings
164: the second openings
164a: second contact openings
166: the three openings
166a: the 3rd contact openings
168: the four openings
168a: the 4th contact openings
170a: the first connection pad electrode
170b: the second connection pad electrode
180: pixel electrode
190a: first wiring
190b: second wiring
DL: data wire
SL: scan line
A: active layers
C: chip
G: grid
GI: gate insulation layer
S: source electrode
D: drain electrode
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Fig. 2 A be one embodiment of the invention a kind of pel array on look schematic diagram, Fig. 2 B is the non-display area of Fig. 2 A substrate and the enlarged diagram of test section, Fig. 2 C is for along the line II-II of line I-I, Fig. 2 B of Fig. 2 A and the generalized section that line III-III is illustrated.Fig. 2 D is the schematic diagram of the non-display area of the chip substrate that is covered in Fig. 2 A.The non-display area and the test section of following pel array can be same or analogous designs.But the invention is not restricted to this, in other embodiment, the non-display area of data wire side and the element design of test section can be different with the element design of the non-display area of scan line side and test section.
Please also refer to Fig. 2 A, Fig. 2 B and Fig. 2 C, in the present embodiment, pel array 100 comprises a substrate 110, multi-strip scanning line SL and many data wire DL, a plurality of active element 120, a plurality of first connection pad and 130a many second connection pad 130b, many first distribution 140a and many second distribution 140b, an insulating barrier 150, one organic flatness layer 160, a plurality of first connection pad electrode 170a, a plurality of second connection pad electrode 170b and a plurality of pixel electrodes 180.
Specifically, substrate 110 has a viewing area 112 and a non-display area 114.Scan line SL and data wire DL are arranged in viewing area 112.Active element 120 is arranged in viewing area 112 and is electrically connected with data wire DL with scan line SL.In the present embodiment, each active element 120 comprises a grid G, a gate insulation layer GI, an active layers A, one source pole S and a drain D, wherein grid G is positioned on the substrate 110 and gate insulation layer GI cover gate G, active layers A is the double-decker of being formed with amorphous silicon (also being called channel layer) and N type heavily doped amorphous silicon (also being called ohmic contact layer) and is positioned on the gate insulation layer GI that source S and drain D lay respectively at the top of part active layers A.
The first connection pad 130a and the second connection pad 130b are arranged in the non-display area 114 of substrate 110, particularly, and the first connection pad 130a and second connection pad 130b configuration interlaced with each other.In the present embodiment, gate insulation layer GI is positioned at the viewing area 112 and the non-display area 114 of substrate 110, and covers the first connection pad 130a that is positioned on the substrate 110, and the second connection pad 130b is positioned on the gate insulation layer GI.In other words, the first connection pad 130a and the second connection pad 130b belong to different retes.In the present embodiment, the material of the material of the first connection pad 130a and the second connection pad 130b is inequality, but is not limited thereto, and in the embodiment that other do not illustrate, the material of the material of the first connection pad 130a and the second connection pad 130b also can be identical.
The first distribution 140a and the second distribution 140b are positioned at the non-display area 114 of substrate 110, and are connected with the first connection pad 130a and the second connection pad 130b respectively.The material of the first distribution 140a is identical with the material of the first connection pad 130a, and the material of the second distribution 140b is identical with the material of the second connection pad 130b.More specifically, the first distribution 140a belongs to identical rete with the first connection pad 130a, and the second distribution 140b belongs to identical rete with the second connection pad 130b.In the present embodiment, because the first connection pad 130a and the second connection pad 130b belong to different retes, therefore the first distribution 140a and the second distribution 140b that is connected with the first connection pad 130a and the second connection pad 130b respectively also do not belong to same rete.
Insulating barrier 150 cover data line DL, scan line SL, active element 120, the first connection pad 130a, the second connection pad 130b, the first distribution 140a and the second distribution 140b.Organic flatness layer 160 covers insulating barrier 150, has a plurality of first contact openings 162a (only schematically illustrating among Fig. 2 C), a plurality of second contact openings 164a (only schematically illustrating among Fig. 2 C) and a plurality of the 3rd contact openings 166a (only schematically illustrating among Fig. 2 C) in wherein organic flatness layer 160 and the insulating barrier 150.The first contact openings 162a exposes the first connection pad 130a, and the second contact openings 164a exposes the second connection pad 130b, and the 3rd contact openings 166a exposes the part of active element 120.Particularly, in the present embodiment, the thickness of organic flatness layer 160 that is positioned at non-display area 114 is less than the thickness of the organic flatness layer 160 that is positioned at viewing area 112, its purpose is to make things convenient for engage (please refer to Fig. 2 D) of chip C and non-display area 114, can increase the yield that engages of chip C and non-display area 114.
The first connection pad electrode 170a is positioned on organic flatness layer 160 of non-display area 114, and the first connection pad electrode 170a is electrically connected with the first connection pad 130a by the first contact openings 162a.The second connection pad electrode 170b is positioned on organic flatness layer 160 of non-display area 114, and the second connection pad electrode 170b is electrically connected with the second connection pad 130b by the second contact openings 164a.Pixel electrode 180 is positioned on organic flatness layer 160 of viewing area 112, and pixel electrode 180 is electrically connected with active element 120 by the 3rd contact openings 166a.
In addition, refer again to Fig. 2 B, in the present embodiment, pel array 100 more comprises many first wiring 190a and many second wiring 190b.The first wiring 190a and the second wiring 190b are arranged in non-display area 114, and the first wiring 190a is electrically connected with the first connection pad 130a, and the second wiring 190b is electrically connected with the second connection pad 130b.In organic flatness layer 160 of non-display area 114 and insulating barrier 150, more comprise a plurality of the 4th contact openings 168a, wherein the 4th contact openings 168a exposes the first wiring 190a, and the first connection pad electrode 170a is electrically connected with the first wiring 190a by the 4th contact openings 168a.Particularly, the first wiring 190a and the second wiring 190b belong to same rete together.
According to embodiments of the invention, substrate 110 more comprises test section 116, and test section 116 has a plurality of switch element 116a, the first testing element 116b, the second testing element 116c and the 3rd testing element 116d.Switch element 116a reaches with the first wiring 190a respectively and is electrically connected with the second wiring 190b, and the first testing element 116b, the second testing element 116c and the 3rd testing element 116d are electrically connected with switch element 116a.
What deserves to be mentioned is; the present invention does not limit the kenel of test section 116; though the test section 116 that reaches mentioned herein is embodied as a plurality of switch element 116a and the first testing element 116b; the second testing element 116c and the 3rd testing element 116d are electrically connected; but in other embodiment; please refer to Fig. 2 F; also can not need switch element 116a; and directly with the first testing element 116b; the second testing element 116c and the 3rd testing element 116d difference first wiring 190a reach and are electrically connected with the second wiring 190b; still belong to the adoptable technical scheme of the present invention, do not break away from the scope of institute of the present invention desire protection.
In brief, in the present embodiment, the first connection pad 130a and second connection pad 130b configuration interlaced with each other and belong to different retes in the non-display area 114 of substrate 110, and the first connection pad 130a can directly link to each other with chip C (please refer to Fig. 2 D) with the second connection pad 130b, is not electrically connected (commentaries on classics line) two metal levels and do not need to see through the connection pad electrode as known need.Therefore need carry out heavy industry when engaging as chip C, not have known because of the connection pad electrode problem that two metal levels that cause connection pad can't electrically conduct with chip that breaks.In addition, the thickness of the organic flatness layer 160 that is positioned at non-display area 114 of present embodiment is less than the thickness of the organic flatness layer 160 that is positioned at viewing area 112, except keeping under the situation of organic flatness layer 160, outside the connection pad Problem of Failure that connection pad electrode broken string is produced when effectively solving known chip heavy industry joint, also can effectively increase the joint yield of chip.
In this mandatory declaration be, the pel array 100 that present embodiment illustrated is to be applicable to large-sized panel, the first distribution 140a that is positioned at a side of pel array 100 is to be electrically connected with data wire DL with the second distribution 140b, and its first distribution 140a that is positioned at the opposite side of pel array 100 is to be electrically connected with scan line SL with the second distribution 140b, but is not limited thereto.In addition, in another embodiment, only at the interconnected first connection pad 130a and the second connection pad 130b of non-display area 114 designs of data wire DL side, just the first distribution 140a is to be electrically connected with data wire DL with the second distribution 140b for it.And be to design generally not have interconnected bonding pad structure at the non-display area 114 of scan line SL side.In another embodiment, it only designs the interconnected first connection pad 130a and the second connection pad 130b at the non-display area 114 of scan line SL side, and just the first distribution 140a is to be electrically connected with scan line SL with the second distribution 140b.And be to design generally not have interconnected bonding pad structure at the non-display area 114 of data wire DL side.
In addition, the present invention also can be applied in the small size panel pixels array.Can be described in detail as follows only in the side design as the above-mentioned non-display area and the test section of pel array for being used for small size panel pixels array.Please refer to Fig. 2 E, pel array 100 ' only has the first distribution 140a, the second distribution 140b, the first connection pad 130a and the second connection pad 130b in the design of one side.Therefore, some is to be electrically connected with data wire DL among the first distribution 140a and the second distribution 140b, and another part is to be electrically connected with scan line SL among the first distribution 140a and the second distribution 140b.
The above pel array of introducing 100 can be made by following manufacture method.Below will illustrate as an example, and cooperate Fig. 3 A to Fig. 3 H that the manufacture method of pel array 100 of the present invention is described in detail with the structure of the pel array among Fig. 2 A 100.This mandatory declaration be, for convenience of description for the purpose of, Fig. 3 A to Fig. 3 H only schematically illustrates line I-I along Fig. 2 A, the manufacture method of pel array 100 is described along the section of the line II-II of Fig. 2 B and line III-III.
Fig. 3 A to Fig. 3 H is the generalized section of manufacture method of a kind of pel array of one embodiment of the invention.Please refer to Fig. 3 A, the manufacture method about the pel array 100 of present embodiment at first, provides a substrate 110.Substrate 110 has a viewing area 112 and a non-display area 114.
Please also refer to Fig. 3 A, Fig. 2 A and Fig. 2 B, then, in the viewing area 112 of substrate 110, form multi-strip scanning line SL and a plurality of grid G simultaneously, and a plurality of first connection pad 130a that form many first distribution 140a and be connected with the first distribution 140a in the non-display area 114 of substrate 110, wherein scan line SL is electrically connected with grid G.On the practice, grid G can be the some of scan line SL, and certainly, grid G also can be to stretch out by scan line SL to form, and does not painstakingly limit at this.Particularly, in the present embodiment, the first connection pad 130a and the first distribution 140a form in same technology simultaneously, and therefore the material of the first distribution 140a is identical with the material of the first connection pad 130a.
Please refer to Fig. 3 B, then, form a gate insulation layer GI with the grid G of covering viewing area 112 and the first connection pad 130a and the first distribution 140a of non-display area 114.Then, be that the gate insulation layer GI of grid G top goes up formation one active layers A, wherein active layers A is the double-decker of being formed with amorphous silicon (also being called channel layer) and N type heavily doped amorphous silicon (also being called ohmic contact layer).
Please also refer to Fig. 3 C, Fig. 2 A and Fig. 2 B, then, a plurality of second connection pad 130b that while forms many second distribution 140b and is connected with the second distribution 140b in the non-display area 114 of substrate 110, in the viewing area 112 of substrate 110, form data wire DL on gate insulation layer GI, form an one source pole S and a drain D in the top of part active layers A, wherein source S is electrically connected to data wire DL.Simultaneously, in the non-display area 114 of substrate 110, form many first wiring 190a and many second wiring 190b.Particularly, the second wiring 190b directly links together with the second connection pad 130b.Therefore the first wiring 190a and the first connection pad 130a do not have the relation of electrical connection at present as yet because of belonging to different retes.
In addition, because the second connection pad 130b and the second distribution 140b form in same technology simultaneously, therefore the material of the second distribution 140b is identical with the material of the second connection pad 130b.In addition, the first wiring 190a and the second wiring 190b and the above-mentioned second connection pad 130b and the second distribution 140b form in same technology simultaneously, and therefore the material of the first wiring 190a and the second wiring 190b is identical with the material of the second distribution 140b and the second connection pad 130b.
Particularly, in the present embodiment, the first connection pad 130a and the second connection pad 130b belong to different retes, and the first connection pad 130a and second connection pad 130b configuration interlaced with each other.The material of the material of the first connection pad 130a and the second connection pad 130b is inequality, but is not limited thereto, and in the embodiment that other do not illustrate, the material of the material of the first connection pad 130a and the second connection pad 130b also can be identical.So far, the roughly making of scan line SL, data wire DL and the active element 120 that is electrically connected with scan line SL and data wire DL in the viewing area 112 of substrate 110.What deserves to be mentioned is that active element 120 of the present invention and structure thereof serve as to implement example with end lock type structure, but are not limited thereto.In other embodiment, only as long as the order that change first connection pad 130a and active layers A are formed on the substrate 110 can become the top gate type structure.
In addition, in this mandatory declaration be, the first distribution 140a of present embodiment one side is to be electrically connected with data wire DL with the second distribution 140b, and the first distribution 140a of opposite side is to be electrically connected with scan line SL with the second distribution 140b, the formed pel array 100 of juncture of this kind first distribution 140a, the second distribution 140b and data wire DL, scan line SL is to be applicable to large-sized panel, but is not limited thereto.In other embodiment, pel array 100 can also have only the first distribution 140a and the second distribution 140b of a side, and the first distribution 140a is to be electrically connected with data wire DL or scan line SL with the second distribution 140b.Certainly, in other embodiment, the small size of being suitable for panel pixels array 100 ' also can be arranged, some is to be electrically connected with data wire DL among its first distribution 140a and the second distribution 140b, and another part is to be electrically connected with scan line SL among the first distribution 140a and the second distribution 140b, please refer to Fig. 2 E.
Please also refer to Fig. 3 D, Fig. 2 A and Fig. 2 B, then, on substrate 110, form an insulating barrier 150, the wherein first connection pad 130a of cover data line DL, scan line SL, active element 120 and the non-display area 114 of insulating barrier 150 viewing areas 112, the second connection pad 130b, the first distribution 140a and the second distribution 140b.
Please refer to Fig. 3 E, then, on insulating barrier 150, form an organic flatness layer 160.Please refer to Fig. 3 F, then, the organic flatness layer 160 of patterning, in organic flatness layer 160, to form a plurality of first openings 162, a plurality of second opening 164, a plurality of the 3rd opening 166 and a plurality of the 4th opening 168, and remove the local thickness of organic flatness layer 160 of non-display area 114, so that the thickness of organic flatness layer 160 that is positioned at non-display area 114 is less than the thickness of the organic flatness layer 160 that is positioned at viewing area 112.In the present embodiment, the method for the organic flatness layer 114 of patterning for example is by partly transferring mask technique (half-tonemask) to reach.Specifically, in the present embodiment, the thickness of organic flatness layer 160 that is positioned at non-display area 114 is less than the thickness of the organic flatness layer 160 that is positioned at viewing area 112, its purpose is to make things convenient for engage (please refer to Fig. 2 D) of chip C and non-display area 114, can increase the yield that engages of chip and non-display area 114.
Please refer to Fig. 3 G, then, with organic flatness layer 160 as etch mask etching insulating barrier 150, to form a plurality of first contact openings 162a, a plurality of second contact openings 164a, a plurality of the 3rd contact openings 166a and a plurality of the 4th contact openings 168a.Specifically, in the present embodiment, the first contact openings 162a exposes the first connection pad 130a, and the second contact openings 164a exposes the second connection pad 130b, the 3rd contact openings 166a exposes the part of active element 120, and the 4th contact openings 168a exposes the first wiring 190a.
Please refer to Fig. 3 H, then, on organic flatness layer 160 of non-display area 114, form a plurality of first connection pad electrode 170a and a plurality of second connection pad electrode 170b, and on organic flatness layer 160 of viewing area 112, form a plurality of pixel electrodes 180.Specifically, the first connection pad electrode 170a is electrically connected with the first connection pad 130a by the first contact openings 162a.The second connection pad electrode 170b is electrically connected with the second connection pad 130b by the second contact openings 164a.Pixel electrode 180 is electrically connected with active element 120 by the 3rd contact openings 166a.In addition, the first connection pad electrode 170a more is electrically connected with the first wiring 190a by the 4th contact openings 168a.Particularly, in the present embodiment, the first wiring 190a and the second wiring 190b belong to same rete together, and therefore, the first connection pad 130a can make it be electrically connected with the first wiring 190a that is positioned at different retes by the commentaries on classics line of the 4th contact openings 168a.
What deserves to be mentioned is, please refer to Fig. 2 B, in above-mentioned technical process, can form a plurality of switch element 116a and the first testing element 116b, the second testing element 116c and the 3rd testing element 116d in the test section 116 of substrate 110 in the lump.Switch element 116a is electrically connected with the first wiring 190a and the second wiring 190b, and the first testing element 116b, the second testing element 116c and the 3rd testing element 116d are electrically connected with switch element 116a.
What deserves to be mentioned is; the present invention does not limit the kenel of test section 116; though the test section 116 that reaches mentioned herein is embodied as a plurality of switch element 116a and the first testing element 116b; the second testing element 116c and the 3rd testing element 116d are electrically connected; but in other embodiment; please refer to Fig. 2 F; also can not need switch element 116a; and directly form the first testing element 116b; the second testing element 116c and the 3rd testing element 116d; and the first testing element 116b; the second testing element 116c and the 3rd testing element 116d reach with the first wiring 190a and are electrically connected with the second wiring 190b; still belong to the adoptable technical scheme of the present invention, do not break away from the scope of institute of the present invention desire protection.
In brief, in the present embodiment, the first connection pad 130a and second connection pad 130b configuration interlaced with each other and belong to different retes in the non-display area 114 of substrate 110, and the first connection pad 130a can directly link to each other with chip C with the second connection pad 130b.Therefore need carry out heavy industry when engaging as chip C, do not have known because of connection pad electrode broken string cause bonding pad structure two metal levels can't with the problem of the electrical not conducting of chip.In addition, the manufacture method of the pel array of present embodiment, keeping organic flatness layer 160 and do not increasing under the situation of production stage, can cause connection pad electrode broken string when the known chip heavy industry engages and produce the problem that connection pad lost efficacy except can effectively solving, also can increase the yield that engages of chip and substrate.
In sum, first connection pad of pel array of the present invention is with the configuration interlaced with each other of second connection pad and belong to different retes, and first connection pad directly is connected with the connection pad electrode with second connection pad, and does not change the design of line structure.Even therefore when chip carry out heavy industry when engaging the connection pad electrode problem that breaks takes place, can not influence being electrically connected between connection pad and the chip yet.In addition, pel array of the present invention and manufacture method thereof, can not increase processing step and keep under the situation of organic flatness layer, first connection pad and second connection pad produce the problem that connection pad lost efficacy because of the connection pad broken string when effectively solving chip heavy industry joint, and can increase the joint yield of chip.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any affiliated technical field technical staff, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (22)
1. a pel array is characterized in that, described pel array comprises:
One substrate, it has a viewing area and a non-display area;
Multi-strip scanning line and many data wires are arranged in described viewing area;
A plurality of active elements are arranged in described viewing area and are electrically connected with described these data wires with described these scan lines;
A plurality of first connection pads and a plurality of second connection pad are arranged in described non-display area, wherein said these first connection pads and the configuration interlaced with each other of described these second connection pads, and described these first connection pads and described these second connection pads belong to different retes;
Many first distributions and many second distributions, be positioned at described non-display area and be connected with described these first and second connection pads respectively, one of them of wherein said these first distributions is arranged between two adjacent described these second distributions, the material of described these first distributions is identical with the material of described these first connection pads, the material of described these second distributions is identical with the material of described these second connection pads, and the material of the material of described these first connection pads and described these second connection pads is inequality;
One insulating barrier covers described these data wires, described these scan lines, described these active elements, described these first connection pads, described these second connection pads, described these first distributions and described these second distributions;
One organic flatness layer, cover described insulating barrier, have a plurality of first contact openings, a plurality of second contact openings and a plurality of the 3rd contact openings in wherein said organic flatness layer and the described insulating barrier, described these first contact openings expose described these first connection pads, described these second contact openings expose described these second connection pads, and described these the 3rd contact openings expose the part of described these active elements;
A plurality of first connection pad electrodes are positioned on described organic flatness layer of described non-display area, and described these first connection pad electrodes are electrically connected with described these first connection pads by described these first contact openings;
A plurality of second connection pad electrodes are positioned on described organic flatness layer of described non-display area, and described these second connection pad electrodes are electrically connected with described these second connection pads by described these second contact openings; And
A plurality of pixel electrodes are positioned on described organic flatness layer of described viewing area, and described these pixel electrodes are electrically connected with described these active elements by described these the 3rd contact openings.
2. pel array as claimed in claim 1 is characterized in that, the material of the material of described these first connection pads and described these second connection pads is inequality.
3. pel array as claimed in claim 1 is characterized in that, described these first distributions are electrically connected with described these data wires with described these second distributions.
4. pel array as claimed in claim 1 is characterized in that, described these first distributions are electrically connected with described these scan lines with described these second distributions.
5. pel array as claimed in claim 1 is characterized in that, some is electrically connected with described these data wires in described these first distributions and described these second distributions, and another part is electrically connected with described these scan lines.
6. pel array as claimed in claim 1 is characterized in that, the thickness of described organic flatness layer that is positioned at described non-display area is less than the thickness of the described organic flatness layer that is positioned at described viewing area.
7. pel array as claimed in claim 1, it is characterized in that, described pel array more comprises many first wiring and many second wiring, be arranged in described non-display area, and described these first wiring are electrically connected with described these first connection pads, and described these second wiring are electrically connected with described these second connection pads.
8. pel array as claimed in claim 7, it is characterized in that, in described organic flatness layer of described non-display area and described insulating barrier, more comprise a plurality of the 4th contact openings, it exposes described these first wiring, and described these first connection pad electrodes are electrically connected with described these first wiring by described these the 4th contact openings.
9. pel array as claimed in claim 7 is characterized in that described substrate more comprises the test section, and described test section has a plurality of switch elements, and described these switch elements are with described these first wiring and be electrically connected with described these second wiring.
10. pel array as claimed in claim 9 is characterized in that described pel array more comprises a plurality of testing elements, is positioned at described test section, and described these testing elements are electrically connected with described these switch elements.
11. pel array as claimed in claim 7 is characterized in that, described substrate more comprises the test section, and described test section has a plurality of testing elements, and described these testing elements are with described these first wiring and be electrically connected with described these second wiring.
12. the manufacture method of a pel array is characterized in that, described manufacture method comprises:
One substrate is provided, and described substrate has a viewing area and a non-display area;
The a plurality of active elements that in described viewing area, form multi-strip scanning line, many data wires and be electrically connected with described these scan lines and described these data wires;
A plurality of first connection pads that in described non-display area, form many first distributions simultaneously and be connected with described these first distributions;
A plurality of second connection pads that in described non-display area, form many second distributions simultaneously and be connected with described these second distributions, one of them of wherein said these first distributions is arranged between two adjacent described these second distributions, described these first connection pads and described these second connection pads belong to different retes, and described these first connection pads and the configuration interlaced with each other of described these second connection pads, and the material of the material of described these first connection pads and described these second connection pads is inequality;
On described substrate, form an insulating barrier, cover described these data wires, described these scan lines, described these active elements, described these first connection pads, described these second connection pads, described these first distributions and described these second distributions;
On described insulating barrier, form an organic flatness layer, have a plurality of first openings, a plurality of second opening and a plurality of the 3rd opening in wherein said organic flatness layer;
With described organic flatness layer as the described insulating barrier of etch mask etching, to form a plurality of first contact openings, a plurality of second contact openings and a plurality of the 3rd contact openings, described these first contact openings expose described these first connection pads, described these second contact openings expose described these second connection pads, and described these the 3rd contact openings expose the part of described these active elements; And
On described organic flatness layer of described non-display area, form a plurality of first connection pad electrodes and a plurality of second connection pad electrode, and on described organic flatness layer of described viewing area, form a plurality of pixel electrodes, described these first connection pad electrodes are electrically connected with described these first connection pads by described these first contact openings, described these second connection pad electrodes are electrically connected with described these second connection pads by described these second contact openings, and described these pixel electrodes are electrically connected with described these active elements by described the 3rd contact openings.
13. the manufacture method of pel array as claimed in claim 12 is characterized in that, the material of the material of described these first connection pads and described these second connection pads is inequality.
14. the manufacture method of pel array as claimed in claim 12 is characterized in that, described these first distributions are electrically connected with described these data wires with described these second distributions.
15. the manufacture method of pel array as claimed in claim 12 is characterized in that, described these first distributions are electrically connected with described these scan lines with described these second distributions.
16. the manufacture method of pel array as claimed in claim 12 is characterized in that, some is electrically connected with described these data wires in described these first distributions and described these second distributions, and another part is electrically connected with described these scan lines.
17. the manufacture method of pel array as claimed in claim 12, it is characterized in that, described manufacture method more comprises the local thickness of the described organic flatness layer that removes described non-display area, so that the thickness of described organic flatness layer that is positioned at described non-display area is less than the thickness of the described organic flatness layer that is positioned at described viewing area.
18. the manufacture method of pel array as claimed in claim 12, it is characterized in that, described manufacture method more is included in and forms many first wiring and many second wiring in the described non-display area, described these first wiring are electrically connected with described these first connection pads, and described these second wiring are electrically connected with described these second connection pads.
19. the manufacture method of pel array as claimed in claim 18, it is characterized in that, described manufacture method more is included in and forms a plurality of the 4th contact openings in described organic flatness layer of described non-display area and the described insulating barrier, and described these first connection pad electrodes are electrically connected with described these first wiring by described the 4th contact openings.
20. the manufacture method of pel array as claimed in claim 18 is characterized in that, described substrate has more a test section, and described method more comprises:
Form a plurality of switch elements in described test section, and described these switch elements are electrically connected with described these first wiring and described these second wiring.
21. the manufacture method of pel array as claimed in claim 20 is characterized in that, described manufacture method more is included in described test section and forms a plurality of testing elements, and described these testing elements are electrically connected with described these switch elements.
22. the manufacture method of pel array as claimed in claim 18 is characterized in that, described substrate has more a test section, and described method more comprises:
Form a plurality of testing elements in described test section, described these testing elements reach with described these first wiring and are electrically connected with described these second wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101905119A CN101442060B (en) | 2008-12-25 | 2008-12-25 | Pixel array and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101905119A CN101442060B (en) | 2008-12-25 | 2008-12-25 | Pixel array and method of manufacturing the same |
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| CN101442060A CN101442060A (en) | 2009-05-27 |
| CN101442060B true CN101442060B (en) | 2011-04-20 |
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| CN103681488A (en) * | 2013-12-16 | 2014-03-26 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105093729B (en) * | 2015-09-17 | 2018-02-27 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| KR102380331B1 (en) * | 2015-11-30 | 2022-04-01 | 엘지디스플레이 주식회사 | In Plane Switching Type Liquid Crystal Display Having Ultra High Transmittance Rate |
| CN105739200A (en) * | 2016-04-20 | 2016-07-06 | 深圳市华星光电技术有限公司 | Method for binding pins in OLB area |
| CN106873278A (en) * | 2017-04-25 | 2017-06-20 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| TWI718021B (en) * | 2019-08-20 | 2021-02-01 | 友達光電股份有限公司 | Dsiplay panel |
| CN110707100B (en) * | 2019-10-16 | 2021-12-31 | 友达光电（昆山）有限公司 | Display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1556435A (en) * | 2003-12-31 | 2004-12-22 | 友达光电股份有限公司 | Manufacturing method of thin film transistor array substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1556435A (en) * | 2003-12-31 | 2004-12-22 | 友达光电股份有限公司 | Manufacturing method of thin film transistor array substrate |
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