CN101442055A - Improved memory cell for silicon static state stochastic memory of part depletion isolator - Google Patents
Improved memory cell for silicon static state stochastic memory of part depletion isolator Download PDFInfo
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- CN101442055A CN101442055A CNA2007101777883A CN200710177788A CN101442055A CN 101442055 A CN101442055 A CN 101442055A CN A2007101777883 A CNA2007101777883 A CN A2007101777883A CN 200710177788 A CN200710177788 A CN 200710177788A CN 101442055 A CN101442055 A CN 101442055A
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Abstract
The invention provides a storage unit for improving a static random access memory formed on a partially depleted SOI substrate, which relates to the technology of the static random access memory. The SRAM unit comprises six transistors, namely a first access NMOS transistor, a second access NMOS transistor, a first drive NMOS transistor, a second drive NMOS transistor, a first load PMOS transistor and a second load PMOS transistor. When body-area contact processing is carried out, T-type gate technology is not adopted, the NMOS transistors are accessed by an H-type gate body contact, and the load PMOS transistors and the drive NMOS adopt BTS-A type gate body contact. Therefore, not only floating body effect caused by the partially depleted SOI material can be avoided, but also island side creepage caused by a T-type gate structure can be inhibited. Two groups of inverters in the unit are linked in the middle of the unit so as to simplify cabling and reduce area of the unit. The storage unit improves the final performance of a chip.
Description
Technical field
The present invention relates to static random access memory (SRAM) technical field, more specifically, it is a kind of improved part depletion silicon-on-insulator static random access memory memory cell, be used for part depletion silicon-on-insulator (PDSOI, Partial Depleted Silicon on Insulator) static random access memory on the substrate.
Background technology
According to data storage method, semiconductor memory is divided into dynamic random access memory (DRAM), non-volatility memorizer and static RAM (SRAM).SRAM can realize service speed fast in a kind of simple and mode low-power consumption, thereby sets up its special advantages.And, compare with DRAM, because SRAM does not need the periodic refresh canned data, so design and manufacturing are relatively easy.
See Fig. 1, usually, sram cell is made up of two driving transistorss, two load devices and two access transistors.According to the type of contained load device, SRAM itself can be divided into complete CMOS SRAM again, high capacity resistance (High Load Resistor) SRAM and thin-film transistor (ThinFilm Transistor) SRAM.CMOS SRAM uses the PMOS pipe as load device fully, and HLR SRAM uses high capacity resistance as load device, and TFT SRAM uses multi-crystal TFT as load device.
SRAM can realize on different backing materials, such as on body silicon (Bulk Silicon) substrate, forming standard CMOS SRAM, on part depletion silicon-on-insulator (PDSOI, PartialDepletion Silicon on Insulator) substrate, form PDSOI SRAM.The former cellar area is less, obtains the memory of big integrated level easily, but easily latch-up takes place and power consumption is bigger; The latter is owing to well-known reason, can avoid latch-up fully, power consumption is less, if can solve the problem that draw in the tagma preferably, also can suppress " floater effect ", and the performance of PDSOI SRAM in radiation environment is well more a lot of than body silicon CMOS SRAM.
Providing a kind of PDSOI static random access memory (see figure 2) among the invention disclosed CN200510136596_9, its load PMOS pipe and access NMOS pipe all adopt T type grid body contact structure, because " the island side effect " that T type grid exist, can increase electric leakage, easier extra leakage current, the quiescent dissipation of increase chip of causing after particularly irradiated.And the body draw-out area of the driving N MOS of invention among the CN200510136596_9 is positioned at the active area centre position, and promptly the source end is divided into two parts and is positioned at the active area both sides, also is unfavorable for reducing leakage current, need improve.
Summary of the invention
The objective of the invention is to disclose a kind of improved part depletion silicon-on-insulator (PDSOI) static random access memory memory cell, to solve the problem that exists in the prior art.
For achieving the above object, technical solution of the present invention is:
A kind of improved part depletion silicon-on-insulator static random access memory memory cell comprises six transistors that are formed on the part depletion silicon-on-insulator substrate, and it is formed with the first and second access nmos pass transistors; Constitute the first driving N MOS transistor and the first load PMOS transistor of first inverter, this first inverter is driven selectively according to the operation of the first access nmos pass transistor; And the second driving N MOS transistor and the second load PMOS transistor that constitute second inverter, this second inverter is driven selectively according to the operation of the second access nmos pass transistor; Wherein,
First active area is formed on the PD SOI substrate, is used to form first, second driving N metal-oxide-semiconductor and first, second access NMOS pipe;
The second and the 3rd active area is formed on the PD SOI substrate, is used to form the first and second load PMOS transistors;
The source region of the first load PMOS pipe and two individual draw-out areas are positioned at the left side of second active area, constitute BTS-A type grid body deriving structure, and the right side of second active area is the drain region of the first load P pipe;
The source region of the second load PMOS pipe and two individual draw-out areas are positioned at the right side of the 3rd active area, constitute BTS-A type grid body deriving structure, and the left side of the 3rd active area is the drain region of the first load P pipe;
The first and second driving N metal-oxide-semiconductors are positioned at the first half of first active area, and its body draw-out area and source region constitute BTS-A type grid body deriving structure;
The first and second access NMOS manage, and are positioned at the Lower Half of first active area, and the two shared body draw-out area, its body draw-out area and source region all constitute H type grid body deriving structure;
The output of first inverter is connected to the input of second inverter at the middle part, unit, the output of second inverter is connected to the input of first inverter at the middle part, unit.
Described static random access memory memory cell, its described access nmos pass transistor adopts the contact of H type grid body, the body of first, second access nmos pass transistor is drawn TA1-B and TA2-B, is connected with fixed potential with metal wire by contact hole, and this fixed potential is an earth potential.
Described static random access memory memory cell, its described load PMOS transistor adopts the contact of BTS-A type grid body, the transistorized body of first, second load PMOS draw-out area TP1-B and TP2-B, be connected with source end TP1-S, TP2-S respectively with metal wire by contact hole, and being connected to fixed potential, this fixed potential is a power supply potential.
Described static random access memory memory cell, its described driving N MOS transistor adopts the contact of BTS-A type grid body, the draw-out area TN1-B and the TN2-B of first, second driving N MOS transistor, be connected with source end TN1-S, TN2-S respectively with metal wire by contact hole, and being connected to fixed potential, this fixed potential is an earth potential.
Described static random access memory memory cell, its described first active area forms first, second driving N metal-oxide-semiconductor and first, second access NMOS pipe simultaneously, wherein, the drain region of the first driving N metal-oxide-semiconductor and the first access NMOS pipe forms each other on active area and is electrically connected; The drain region of the second driving N metal-oxide-semiconductor and the second access NMOS pipe forms each other on active area and is electrically connected; Share in the tagma of the first access NMOS pipe and the second access NMOS pipe, is connected to earth potential jointly.
Described static random access memory memory cell, it is used on a large scale static memory at random as base unit, or based on the large scale integrated circuit of PDSOI sram cell.
A kind of improved PDSOI static random access memory memory cell of the present invention, wiring is simplified, and cellar area is little, eliminated limit, the island leakage current that T type grid are introduced, avoid floater effect, reduced the power consumption of chip, improved the ability that chip is tackled complicated radiation environment.
Description of drawings
Shown in Fig. 1 is the circuit connection diagram of traditional complete CMOS SRAM, because the body silicon substrate all connects together, so the body end is not carried out special processing;
Shown in Fig. 2 is the six pipe unit structures that have among the invention CN200510136596_9;
Shown in Fig. 3 is PDSOI six transistor memory units after the present invention improves;
Shown in Fig. 4 is the circuit connection diagram of sram cell of the present invention among Fig. 3.
Embodiment
At length content of the present invention is described below by the accompanying drawing image, so that characteristics of the present invention and advantage become more clear, these accompanying drawings comprise:
Shown in Fig. 3 is PDSOI six transistor memory units after the present invention improves, notes six transistorized body outbound courses, particularly the H type grid body deriving structure that adopts of access NMOS pipe.
Shown in Fig. 4 is the circuit connection diagram of sram cell of the present invention among Fig. 3, and each only transistorized tagma all is connected to corresponding fixed potential.
As shown in the figure, a kind of have 6 and be formed at part depletion (partial-depleted, PD) silicon-on-insulator (silicon-on-insulator, SOI) the transistorized CMOS static random access memory cell on the substrate.
This unit is implemented on part depletion silicon-on-insulator (PDSOI) substrate, six transistors all carry out the body contact to be handled, wherein load PMOS pipe and driving N metal-oxide-semiconductor adopt BTS-A type grid body deriving structure, access NMOS pipe adopts H type grid body deriving structure, eliminates because T type grid body is drawn limit, the island leakage current that causes.
The formation of this sram cell has: the first and second access nmos pass transistor TA1, TA2; Constitute the first driving N MOS transistor TN1 and the first load PMOS transistor T P1 of first inverter, this first inverter is driven selectively according to the operation of the first access nmos pass transistor TA1; And the second driving N MOS transistor TN2 and the second load PMOS transistor T P2 that constitute second inverter, this second inverter is driven selectively according to the operation of the second access nmos pass transistor TA2.
On physical structure, this SRAM comprises:
First active area, it is formed on the PD SOI substrate, is used to form first, second driving N metal-oxide-semiconductor and first, second access NMOS pipe;
The second and the 3rd active area, it is formed on the PD SOI substrate, is used to form the first and second load PMOS transistors;
The source region of the first load PMOS pipe and two individual draw-out areas are positioned at the left side of second active area, constitute BTS-A type grid body deriving structure, and the right side of second active area is the drain region of the first load P pipe;
The source region of the second load PMOS pipe and two individual draw-out areas are positioned at the right side of the 3rd active area, constitute BTS-A type grid body deriving structure, and the left side of the 3rd active area is the drain region of the first load P pipe;
The first and second driving N metal-oxide-semiconductors are positioned at the first half of first active area, and its body draw-out area and source region constitute BTS-A type grid body deriving structure;
The first and second access NMOS manage, and are positioned at the Lower Half of first active area, and the two shared body draw-out area, its body draw-out area and source region all constitute H type grid body deriving structure;
The output of first inverter is connected to the input of second inverter at the middle part, unit, the output of same second inverter is connected to the input of first inverter at the middle part, unit.
SRAM memory cell of the present invention further is explained as follows:
The access nmos pass transistor adopts the contact of H type grid body, and TA1-B, TA2-B and TA-B district are H type grid body draw-out areas among Fig. 3, be connected with fixed potential with metal wire by contact hole, and be ground potential GND herein.
The load PMOS pipe adopts the contact of BTS-A type grid body, and TP1-B, TP2-B are BTS-A type grid body draw-out areas among Fig. 3, and be connected with source end TP1-S, TP2-S with metal wire by contact hole, and be connected to fixed potential, be power supply potential VCC herein.
The driving N metal-oxide-semiconductor adopts the contact of BTS-A type grid body, and TN1-B, TN2-B are BTS-A type grid body draw-out areas among Fig. 3, and be connected with source end TN1-S, TN2-S with metal wire by contact hole, and be connected to fixed potential, be ground potential GND herein.
First active area forms first, second driving N metal-oxide-semiconductor and first, second access NMOS pipe simultaneously, and wherein the drain region of the first driving N metal-oxide-semiconductor and the first access NMOS pipe is connected with each other on active area, forms to be electrically connected; The drain region of the second driving N metal-oxide-semiconductor and the second access NMOS pipe is connected with each other on active area, forms to be electrically connected; Share in the tagma of the first access NMOS pipe and the second access NMOS pipe, is connected to earth potential jointly.
The output D1 ' of first inverter is connected to the input D1 ＂ of second inverter at the middle part, unit, the output D2 ' of second inverter is connected to the input D2 ＂ of first inverter at the middle part, unit.
In a word, the present invention has all carried out body to six transistors in the sram cell and has drawn processing, T type grid body deriving structure is improved, access NMOS pipe adopts H type grid body deriving structure, load PMOS pipe and driving N metal-oxide-semiconductor adopt BTS-A type grid body deriving structure, eliminate limit, the island leakage current that T type grid are introduced, can reduce the power consumption of chip, improved the ability of the complicated radiation environment of reply of chip.
Need to prove; though described the present invention in detail with reference to exemplary embodiment; but those are familiar with those of ordinary skill in the art and will understand; under the situation that does not break away from appended claim; the various variations that can at this point make in form and details all should be in the scope of claim protection.
Claims (6)
1. an improved PDSOI static random access memory memory cell comprises six transistors that are formed on the part depletion silicon-on-insulator substrate, and it is formed with the first and second access nmos pass transistors; Constitute the first driving N MOS transistor and the first load PMOS transistor of first inverter, this first inverter is driven selectively according to the operation of the first access nmos pass transistor; And the second driving N MOS transistor and the second load PMOS transistor that constitute second inverter, this second inverter is driven selectively according to the operation of the second access nmos pass transistor; It is characterized in that,
First active area is formed on the PD SOI substrate, is used to form first, second driving N metal-oxide-semiconductor and first, second access NMOS pipe;
The second and the 3rd active area is formed on the PD SOI substrate, is used to form the first and second load PMOS transistors;
The source region of the first load PMOS pipe and two individual draw-out areas are positioned at the left side of second active area, constitute BTS-A type grid body deriving structure, and the right side of second active area is the drain region of the first load P pipe;
The source region of the second load PMOS pipe and two individual draw-out areas are positioned at the right side of the 3rd active area, constitute BTS-A type grid body deriving structure, and the left side of the 3rd active area is the drain region of the first load P pipe;
The first and second driving N metal-oxide-semiconductors are positioned at the first half of first active area, and its body draw-out area and source region constitute BTS-A type grid body deriving structure;
The first and second access NMOS manage, and are positioned at the Lower Half of first active area, and the two shared body draw-out area, its body draw-out area and source region all constitute H type grid body deriving structure;
The output of first inverter is connected to the input of second inverter at the middle part, unit, the output of second inverter is connected to the input of first inverter at the middle part, unit.
2. static random access memory memory cell as claimed in claim 1, it is characterized in that, described access nmos pass transistor adopts the contact of H type grid body, first, second access nmos pass transistor and TA-B district are H type grid body draw-out areas, be connected with fixed potential with metal wire by contact hole, this fixed potential is an earth potential.
3. static random access memory memory cell as claimed in claim 1, it is characterized in that, described load PMOS transistor adopts the contact of BTS-A type grid body, the transistorized body of first, second load PMOS draw-out area TP1-B, TP2-B, by contact hole and metal wire, be connected with source end TP1-S, TP2-S respectively, and be connected to fixed potential, this fixed potential is a power supply potential.
4. static random access memory memory cell as claimed in claim 1, it is characterized in that, described driving N MOS transistor adopts the contact of BTS-A type grid body, body draw-out area TN1-B, the TN2-B of first, second driving N MOS transistor, by contact hole and metal wire, be connected with source end TN1-S, TN2-S respectively, and be connected to fixed potential, this fixed potential is an earth potential.
5. static random access memory memory cell as claimed in claim 1, it is characterized in that, described first active area forms first, second driving N metal-oxide-semiconductor and first, second access NMOS pipe simultaneously, wherein, the drain region of the first driving N metal-oxide-semiconductor and the first access NMOS pipe forms each other on active area and is electrically connected; The drain region of the second driving N metal-oxide-semiconductor and the second access NMOS pipe forms each other on active area and is electrically connected; Share in the tagma of the first access NMOS pipe and the second access NMOS pipe, is connected to earth potential jointly.
6. static random access memory memory cell as claimed in claim 1 is characterized in that, is used on a large scale static memory at random as base unit, or based on the large scale integrated circuit of PDSOI sram cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101777883A CN101442055A (en) | 2007-11-21 | 2007-11-21 | Improved memory cell for silicon static state stochastic memory of part depletion isolator |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2007101777883A CN101442055A (en) | 2007-11-21 | 2007-11-21 | Improved memory cell for silicon static state stochastic memory of part depletion isolator |
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| CN101442055A true CN101442055A (en) | 2009-05-27 |
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| CNA2007101777883A Pending CN101442055A (en) | 2007-11-21 | 2007-11-21 | Improved memory cell for silicon static state stochastic memory of part depletion isolator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034825A (en) * | 2009-09-30 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Embedded sram structure and chip |
| CN112951830A (en) * | 2021-02-01 | 2021-06-11 | 泉芯集成电路制造(济南)有限公司 | Integrated circuit device, memory, and electronic apparatus |
-
2007
- 2007-11-21 CN CNA2007101777883A patent/CN101442055A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034825A (en) * | 2009-09-30 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Embedded sram structure and chip |
| CN102034825B (en) * | 2009-09-30 | 2013-06-12 | 台湾积体电路制造股份有限公司 | Embedded sram structure and chip |
| CN112951830A (en) * | 2021-02-01 | 2021-06-11 | 泉芯集成电路制造(济南)有限公司 | Integrated circuit device, memory, and electronic apparatus |
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Open date: 20090527 |