CN101442048A - Grounding loop structure of radio frequency CMOS integration inductance - Google Patents
Grounding loop structure of radio frequency CMOS integration inductance Download PDFInfo
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- CN101442048A CN101442048A CNA2007100942775A CN200710094277A CN101442048A CN 101442048 A CN101442048 A CN 101442048A CN A2007100942775 A CNA2007100942775 A CN A2007100942775A CN 200710094277 A CN200710094277 A CN 200710094277A CN 101442048 A CN101442048 A CN 101442048A
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- earthing ring
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Abstract
The invention discloses an earthing ring structure in a radio frequency CMOS integrated inductor. The earthing ring consists of an active area and a first layer of metal, wherein the active area and the first layer of metal are disconnected so as to form a disconnected opening of the earthing ring. The earthing ring structure makes the periphery of the inductor not form a closed circuit through disconnecting the active area and the upper connected metal of the earthing ring so as to reduce consumption of energy of a magnetic field on the earthing ring, thereby avoiding substantial descending of Q value. The earthing ring structure ensures a certain Q value without increasing area of the inductor or extra manufacturing cost on the premise that anti-noise capability is improved.
Description
Technical field
The present invention relates to a kind of structure of radio frequency inductive component models, relate in particular to the grounding loop structure in a kind of radio frequency CMOS integration inductance.
Background technology
Radio-frequency (RF) CMOS (complementary metal oxide semiconductors (CMOS)) integrated inductor is one of critical elements of radio-frequency (RF) CMOS integrated circuit, and its substrate is subject to noise jamming and influences the performance index of entire circuit.In the integrated inductor model, introduce the noise resisting ability that ground loop can effectively improve integrated inductor.
The ground loop that adopts in the radio-frequency (RF) component storehouse of using mostly is closed hoop greatly at present.According to Ampere's law, the magnetic field of integrated inductor can produce induced current on the ground loop of closure, cause energy some loss on ground loop, thereby reduced its inductance Q value (quality factor).Q=2 π * energy storage/energy dissipation.If increase the ground loop diameter, make it can reduce the influence of parasitic eddy currents, but can increase the area of inductance like this, thereby increased the chip area of radio frequency integrated circuit away from integrated inductor.
In some RF (radio frequency) technology library of in the industry cycle now having used, the way that disconnects the ground loop metal level is arranged, the ground loop ground floor metal (Metall) of integrated inductor disconnects, but its p type active layer (Diff) does not disconnect, and can form small parasitic eddy currents like this around inductance yet.Some design is placed on ground loop apart from 50 microns places of inductance metal in order to reduce the influence of closed ground loop to the Q value in addition, has so just increased the area of inductance.
Summary of the invention
The technical problem to be solved in the present invention provides the grounding loop structure in a kind of radio frequency CMOS integration inductance, be the substrate noise that brings when radio frequency inductive is worked in order to solve on the one hand, be to cause electromagnetic energy to dissipate on the other hand, thereby when reducing the substrate noise influence, guaranteed certain radio frequency integrated inductor Q value in order to reduce the bigger eddy current effect that conventional ground loop brings.
For solving the problems of the technologies described above, the invention provides the grounding loop structure in a kind of radio frequency CMOS integration inductance, this ground loop is made up of active area and ground floor metal, and described active area and ground floor metal disconnect, and form ground loop and disconnect mouth.
It is identical or opposite with the direction of inductance opening that described ground loop disconnects mouth.
Described ground loop both sides disconnect, and form two and disconnect mouth.Two of described ground loop disconnect a mouthful or level vertical with the inductance opening.
Compare with prior art, the present invention has following beneficial effect: by the structure of suitable design inductance ground loop, is radio frequency integrated inductor ground loop active area and upper strata metal designs discontinuous loop, substrate and the extraneous noise that brings had both been stopped, prevented the magnetic energy loss that the ground loop induced current causes again, guarantee certain inductance Q value, and need not to increase the area of radio frequency inductive, can not introduce extra processes cost.
Description of drawings
Fig. 1 is the vertical view of the grounding loop structure in the radio frequency CMOS integration inductance of the present invention;
Fig. 2 is the sectional view of the grounding loop structure in the radio frequency CMOS integration inductance of the present invention;
Fig. 3 is the reference domain of the grounding loop structure in the radio frequency CMOS integration inductance of the present invention, and wherein, it is opposite with the inductance opening that the ground loop of Fig. 3 (a) disconnects mouth; It is identical with the inductance opening that the ground loop of Fig. 3 (b) disconnects mouth; The ground loop both sides of Fig. 3 (c) disconnect.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
As shown in Figure 1, the present invention proposes the grounding loop structure in a kind of New-type radio-frequency CMOS integrated inductor, promptly by disconnecting ground loop active area and upper strata line metal (Metall thereof, be the ground floor metal), make that can't form closed circuit reduces the loss of magnetic field energy on ground loop to inductance, avoids the Q value to descend significantly on every side.
As shown in Figure 3, grounding loop structure in a kind of radio frequency CMOS integration inductance of the present invention, its ground loop disconnects the direction of mouthful (being the disconnection mouth of ground loop active area and ground floor metal) and inductance opening can be identical or opposite, for example, it is opposite with the direction of inductance opening (see figure 1) that the ground loop of Fig. 3 (a) disconnects mouth, and it is identical with the direction of inductance opening (see figure 1) that the ground loop of Fig. 3 (b) disconnects mouth; And the present invention can disconnect the ground loop both sides, and two of ground loop disconnect mouthful can or level vertical with the inductance opening, and for example, shown in Fig. 3 (c), two of ground loop disconnect mouthful and inductance opening (see figure 1) level.
The realization process of the grounding loop structure in the radio frequency CMOS integration inductance of the present invention and conventional processing step compatibility can only be changed the structure of inductance ground loop mask, need not additionally to increase mask, and as shown in Figure 2, concrete processing step is as follows:
1. make the N trap;
2. carrying out N type (N+) on the N trap injects;
3. fabricating yard oxygen;
4. make contact hole (Contact);
5. deposit ground floor plain conductor;
6. making intermediate dielectric layer;
7. make the top-level metallic inductance.
The present invention is by disconnecting ground loop active area and upper strata line metal thereof, be radio frequency integrated inductor ground loop active area and upper strata metal designs discontinuous loop promptly, make inductance can't form closed circuit on every side, reducing the loss of magnetic field energy on ground loop, thereby avoid the Q value to descend significantly.The advantage of this ground loop is, under the prerequisite that improves anti-substrate noise ability, has guaranteed certain Q value, does not additionally increase the area of inductance again, can additionally not increase cost of manufacture.
Claims (4)
1, the grounding loop structure in a kind of radio frequency CMOS integration inductance, this ground loop is made up of active area and ground floor metal, it is characterized in that, and described active area and ground floor metal disconnect, and form ground loop and disconnect mouth.
2, the grounding loop structure in the radio frequency CMOS integration inductance according to claim 1 is characterized in that, it is identical or opposite with the direction of inductance opening that described ground loop disconnects mouth.
3, the grounding loop structure in the radio frequency CMOS integration inductance according to claim 1 is characterized in that, described ground loop both sides disconnect, and forms two and disconnects mouth.
4, the grounding loop structure in the radio frequency CMOS integration inductance according to claim 3 is characterized in that, two of described ground loop disconnect a mouthful or level vertical with the inductance opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100942775A CN101442048B (en) | 2007-11-23 | 2007-11-23 | Grounding loop structure of radio frequency CMOS integration inductance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100942775A CN101442048B (en) | 2007-11-23 | 2007-11-23 | Grounding loop structure of radio frequency CMOS integration inductance |
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| Publication Number | Publication Date |
|---|---|
| CN101442048A true CN101442048A (en) | 2009-05-27 |
| CN101442048B CN101442048B (en) | 2010-09-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007100942775A Active CN101442048B (en) | 2007-11-23 | 2007-11-23 | Grounding loop structure of radio frequency CMOS integration inductance |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194817A (en) * | 2010-03-03 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device |
| CN102496620A (en) * | 2011-12-30 | 2012-06-13 | 上海集成电路研发中心有限公司 | Semiconductor chip with integration of voltage controlled oscillator and manufacture method thereof |
| CN102709699A (en) * | 2011-07-06 | 2012-10-03 | 中国科学院合肥物质科学研究院 | Leaky wave antenna based on left-right-hand composite transmission line |
| CN104064547A (en) * | 2014-06-26 | 2014-09-24 | 珠海市杰理科技有限公司 | Inductor substrate isolation structure of integrated circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002198490A (en) * | 2000-12-26 | 2002-07-12 | Toshiba Corp | Semiconductor device |
| DE60234775D1 (en) * | 2001-08-09 | 2010-01-28 | Nxp Bv | PLANAR INDUCTIVE COMPONENT AND FLAT TRANSFORMER |
| US7075167B2 (en) * | 2003-08-22 | 2006-07-11 | Agere Systems Inc. | Spiral inductor formed in a semiconductor substrate |
| CN1320647C (en) * | 2003-11-28 | 2007-06-06 | 络达科技股份有限公司 | Integrated circuit chip |
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2007
- 2007-11-23 CN CN2007100942775A patent/CN101442048B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194817A (en) * | 2010-03-03 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device |
| CN102194817B (en) * | 2010-03-03 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device |
| CN102709699A (en) * | 2011-07-06 | 2012-10-03 | 中国科学院合肥物质科学研究院 | Leaky wave antenna based on left-right-hand composite transmission line |
| CN102496620A (en) * | 2011-12-30 | 2012-06-13 | 上海集成电路研发中心有限公司 | Semiconductor chip with integration of voltage controlled oscillator and manufacture method thereof |
| CN102496620B (en) * | 2011-12-30 | 2016-04-06 | 上海集成电路研发中心有限公司 | The semiconductor chip of Integrated VCO and manufacture method thereof |
| CN104064547A (en) * | 2014-06-26 | 2014-09-24 | 珠海市杰理科技有限公司 | Inductor substrate isolation structure of integrated circuit |
| CN104064547B (en) * | 2014-06-26 | 2017-02-15 | 珠海市杰理科技股份有限公司 | Inductor substrate isolation structure of integrated circuit |
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| CN101442048B (en) | 2010-09-08 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131219 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20131219 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |