CN1320647C - Integrated circuit chip - Google Patents
Integrated circuit chip Download PDFInfo
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- CN1320647C CN1320647C CNB2003101188378A CN200310118837A CN1320647C CN 1320647 C CN1320647 C CN 1320647C CN B2003101188378 A CNB2003101188378 A CN B2003101188378A CN 200310118837 A CN200310118837 A CN 200310118837A CN 1320647 C CN1320647 C CN 1320647C
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- 238000007789 sealing Methods 0.000 claims abstract description 126
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 52
- 239000010703 silicon Substances 0.000 claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 47
- 230000001681 protective effect Effects 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 17
- 230000005611 electricity Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000003376 silicon Chemical class 0.000 claims 10
- 230000003321 amplification Effects 0.000 description 22
- 238000003199 nucleic acid amplification method Methods 0.000 description 22
- 230000012447 hatching Effects 0.000 description 18
- 150000004767 nitrides Chemical class 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 108010004350 tyrosine-rich amelogenin polypeptide Proteins 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
The present invention relates to an integrated circuit chip which comprises a silicon base plate, at least one circuit, a fixed sealing ring, a grounding ring and at least one protecting ring, wherein the circuit is formed on the silicon base plate, and the circuit is provided with at least one output / input pad; the fixed sealing ring is formed on the silicon base plate, and the fixed sealing ring encircles the circuit and the output / input pad; the grounding ring is formed between the silicon base plate and the output / input pad, and is electrically connected with the fixed sealing ring; the protecting ring is arranged on the silicon base plate, and the protecting ring encircles the output / input pad to be electrically connected with the fixed sealing ring.
Description
Technical field
The present invention relates to a kind of integrated circuit (integrated circuit, IC) chip (chip), and particularly relate to a kind of integrated circuit (IC) chip with fixed sealing ring (seal ring), ground loop (ground ring) and protective ring (guardring).
Background technology
Semiconductor wafer (wafer) forms several integrated circuit (IC) chip via integrated circuit fabrication process, comprise a plurality of circuit on each integrated circuit (IC) chip, as numeral (digital) circuit, simulation (analog) circuit and radio frequency (radio frequency, RF) circuit.Have a line of cut (scribe) between the two adjacent arbitrarily integrated circuit (IC) chip, be beneficial to integrated circuit (IC) chip and be cut open.In the process of cutting integrated circuit (IC) chip, the cutting stress that is produced can cause the circuit in the integrated circuit (IC) chip to be destroyed.Therefore, design has a fixed sealing ring (seal ring) usually between integrated circuit (IC) chip and line of cut, and the structure with the protection integrated circuit (IC) chip avoids integrated circuit (IC) chip and is damaged in the process that is cut.
Please refer to shown in Figure 1A and Figure 1B, Figure 1A represents the vertical view of traditional integrated circuit (IC) chip, and Figure 1B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 1B-1B ' of Figure 1A.In Figure 1A and Figure 1B, integrated circuit (IC) chip 10 comprises silicon substrate 14, digital circuit 12, radio circuit 13, fixed sealing ring 11 and output/input pad (input/output pad, I/O pad) 12a and 13a, digital circuit 12, radio circuit 13, fixed sealing ring 11 and output/input pad 12a and 13a all form on the silicon substrate 14.Wherein, output/input pad 12a and 13a are electrically connected with digital circuit 12 and radio circuit 13 respectively.Fixed sealing ring 11 is centered around around the integrated circuit (IC) chip 10, and surrounds digital circuit 12, radio circuit 13 and output/input pad 12a and 13a.Shown in Figure 1B, fixed sealing ring 11 comprises P type trap (p well) 15, P type heavily doped layer (P+) 16, metal level 17a, 17b and 17c, dielectric layer 18a, 18b and 18c, through hole 19a, 19b and 19c, sheath 18d and nitride 18e, and P type trap 15 is formed on the silicon substrate 14.P type heavily doped layer (P+) 16 is formed in the P type trap 15, and the surperficial copline of the surface of P type heavily doped layer (P+) 16 and P type trap 15.Dielectric layer 18a～18c, sheath 18d and nitride layer 18e from bottom to top are formed on the surface of P type trap 15 and P type heavily doped layer (P+) 16 in regular turn, metal level 17a～17c is formed at respectively on dielectric layer 18a～18c, and is covered by dielectric layer 18b, 18c and sheath 18d respectively.Through hole 19a～19c is formed at respectively among dielectric layer 18a～18c, and through hole 19a～19c is respectively in order to be electrically connected P type heavily doped layer (P+) 16 and metal level 17a, metal level 17a and 17b and metal level 17b and 17c.
Because fixed sealing ring 11 is the ring-shaped continuous structure, digital circuit 12 is one to be easy to generate the circuit of noise, and radio circuit 13 is one easily by the circuit of noise jamming, the noise that causes digital circuit 12 or output/input pad 12a to be produced will be very easy to pass to radio circuit 13 or output/input pad 13a via fixed sealing ring 11, cause so-called coupling noise (noise coupling) phenomenon, and influence the normal running of radio circuit 13.
In order to solve the phenomenon of above-mentioned coupling noise, the existing multiple settling mode of tradition proposes.Please refer to Fig. 2 A and Fig. 2 B, Fig. 2 A represents the part vertical view of the disclosed integrated circuit (IC) chip of U.S. Patent Publication case US 2003/0122235A1, and Fig. 2 B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 2B-2B ' of Fig. 2 A.In Fig. 2 A and Fig. 2 B, integrated circuit (IC) chip 20 comprises output/input pad 22, ground mat 24, radio circuit 23 and the fixed sealing ring 21a and the 21b of silicon substrate 25, digital circuit.Output/the input pad 22 of digital circuit, ground mat 24, radio circuit 23 and fixed sealing ring 21a and 21b all are formed on the silicon substrate 25, fixed sealing ring 21a and 21b are centered around around the integrated circuit (IC) chip 20, and surround output/input pad 22, ground mat 24 and the radio circuit 23 of digital circuit.Wherein, fixed sealing ring 21a and 21b are discrete circulus, and fixed sealing ring 21b is than output/input pad 22, ground mat 24 and the radio circuit 23 of the more close digital circuit of fixed sealing ring 21a.For the noise that the output/input pad 22 that makes digital circuit is produced can't be passed to radio circuit 23 via fixed sealing ring 21a and 21b, the breach of fixed sealing ring 21a and 21b is staggered, corresponding to fixed sealing ring 21a, ground mat 24 is adjacent to fixed sealing ring 21b via two breach of fixed sealing ring 21a for the output/input pad 22 of digital circuit and radio circuit 23.
The cross-section structure of fixed sealing ring 21a and 21b is identical, is that example explains at this cross-section structure with fixed sealing ring 21b.Shown in Fig. 2 B, fixed sealing ring 21b comprises N type trap 26, P type heavily doped layer (P+) 27, metal silicide layer (salicide) 28, shallow groove isolation layer (shallow trench isolation, STI) 29, dielectric layer 30a～30f, metal level 34a～34f, contact layer 35a～35f, sheath 31, nitride layer 32 and polyimide (polyimide, PI) 33.N type trap 26 is formed on the silicon substrate 25, and P type heavily doped layer (P+) 27 and shallow groove isolation layer 29 are formed in the N type trap 26, the surperficial copline of the surface of P type heavily doped layer (P+) 27 and shallow groove isolation layer 29 and N type trap 26.Wherein, shallow groove isolation layer 29 usefulness are so that the output/input pad 22 of fixed sealing ring 21b and digital circuit, ground mat 24 and radio circuit 23 electricity isolation.Metal silicide layer 28 is formed in the P type heavily doped layer (P+) 27, the surperficial copline of the surface of metal silicide layer 28 and P type heavily doped layer (P+) 27.Dielectric layer 30a～30f, sheath 31, nitride layer 32 and polyimide 33 are from bottom to top to be formed in regular turn on the surface of N type trap 26, metal silicide layer 28 and shallow groove isolation layer 29, metal level 34a～34f is formed at respectively on dielectric layer 30a～30f, and is covered by dielectric layer 30b～30f and sheath 31 respectively.Contact layer 35a～35f is formed at respectively among dielectric layer 30a～30f, and contact layer 35a is in order to be electrically connected metal level 30a and metal silicide layer 28, and contact layer 35b～35f is from bottom to top in regular turn in order to be electrically connected adjacent two metal levels of metal level 30b～30f.
It should be noted that, owing to form a PN junction (PNjunction) between N type trap 26 and the silicon substrate 25, the electric charge that causes being produced in the process with plasma etching manufactured fixed sealing ring 21a and 21b can't be derived via silicon substrate 25, electric charge will accumulate on fixed sealing ring 21a and the 21b, has a strong impact on the electric quality of integrated circuit (IC) chip 20.In addition, because the N type trap 26 of side is not cut open under the breach of fixed sealing ring 21a and 21b, the noise that causes the output/input pad 22 of digital circuit to be produced still may be passed to radio circuit 23 via N type trap 26, produces the phenomenon of coupling noise.In addition, the design of the dicyclo of fixed sealing ring 21a and 21b will increase the size of integrated circuit (IC) chip 20.
Please refer to Fig. 3 A and Fig. 3 B, Fig. 3 A represents the part vertical view of United States Patent (USP) case number 6,492,716 disclosed integrated circuit (IC) chip, and Fig. 3 B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 3B-3B ' of Fig. 3 A.In Fig. 3 A and Fig. 3 B, integrated circuit (IC) chip 40 comprises P type silicon substrate 44, digital circuit 42, radio circuit 43 and fixed sealing ring 41.Digital circuit 42, radio circuit 43 and fixed sealing ring 41 all are formed on the P type silicon substrate 45, and fixed sealing ring 41 is centered around around the integrated circuit (IC) chip 40, and surround digital circuit 42 and radio circuit 43.Wherein, fixed sealing ring 41 is discrete circulus, and has several breach, and as 2 breach, the fixed sealing ring 41 that the fixed sealing ring 41 of feasible part is adjacent to digital circuit 42 and another part is adjacent to radio circuit 43.
Shown in Fig. 3 B, fixed sealing ring 41 comprises N type trap 45, metal silicide layer 46, gate oxide (gate oxide) 47, shallow groove isolation layer 48, polysilicon layer (polysilicon) 49, dielectric layer 50a～50f, metal level 53a～53f, through hole 54a～54f, oxide skin(coating) 51 and nitride layer 52.N type trap 45 and shallow groove isolation layer 48 are formed in the P type silicon substrate 44, and metal silicide layer 46 is formed in the N type trap 45, and gate oxide 47 is formed in the metal silicide layer 46.Wherein, the surperficial copline of the surface of gate oxide 47 and shallow groove isolation layer 48.Dielectric layer 50a～50f, oxide skin(coating) 51 and nitride layer 52 are from bottom to top to be formed in regular turn on the surface of gate oxide 47 and shallow groove isolation layer 48, polysilicon layer 49, metal level 53a～53f are formed at respectively on dielectric layer 50a～50f, and are covered by dielectric layer 50b～50f and oxide skin(coating) 51 respectively.Contact layer 54a～54f is formed at respectively among dielectric layer 50a～50f, and contact layer 54a is in order to be electrically connected metal level 53a and polysilicon layer 49, and contact layer 54b～54f is from bottom to top in regular turn in order to be electrically connected adjacent two metal levels of metal level 53b～53f.
Though polysilicon layer 49 and gate oxide 47 can reduce the coupling noise phenomenon of integrated circuit (IC) chip 40, but the electric charge that causes being produced in the process with plasma etching manufactured fixed sealing ring 41 can't be passed to P type silicon substrate 44, electric charge will accumulate on the problem on the fixed sealing ring 41, and has a strong impact on the electric quality of integrated circuit (IC) chip 40.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of integrated circuit (IC) chip exactly.The design that its fixed sealing ring, ground loop and protective ring are electrically connected mutually, can reduce circuit and output/input pad thereof and extraneous coupling noise degree, and can avoid in the plasma etching processing procedure, producing the phenomenon of electric charge accumulation, to promote the electric quality of integrated circuit (IC) chip.
According to purpose of the present invention, a kind of integrated circuit (IC) chip is proposed, comprise a silicon substrate, at least one circuit, a fixed sealing ring, a ground loop and at least one protective ring.Circuit is formed on the silicon substrate, and circuit has at least one output/input pad.Fixed sealing ring is formed on the silicon substrate, and around circuit and output/input pad.Ground loop is formed between silicon substrate and the output/input pad, and is electrically connected with fixed sealing ring.Protective ring is arranged on the silicon substrate, and around output/input pad, in order to be electrically connected with fixed sealing ring.
According to purpose of the present invention, a kind of fixed sealing ring is proposed, be centered around around the integrated circuit (IC) chip, integrated circuit (IC) chip has a silicon substrate.Fixed sealing ring comprises a P type trap, a N type alloy, a P type heavily doped layer (P+), a separator, several dielectric layers and several metal levels.P type trap is formed on the silicon substrate, and has one first opening.N type doped layer is formed in first opening, and is positioned on the silicon substrate.P type heavily doped layer (P+) is formed on the P type trap, and has one second opening, and second opening is corresponding to N type doped layer.Separator forms in second opening, and is positioned on the N type doped layer.These a little dielectric layers are formed on the P type heavily doped layer (P+), and each metal level is formed on each corresponding dielectric layer, and are electrically connected with P type heavily doped layer (P+).These a little metal levels have a breach, the surface of the separator of this breach expose portion.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.
Description of drawings
Figure 1A represents the vertical view of traditional integrated circuit (IC) chip.
Figure 1B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 1B-1B ' of Figure 1A.
Fig. 2 A represents the part vertical view of the disclosed integrated circuit (IC) chip of U.S. Patent Publication case US 2003/0122235A1.
Fig. 2 B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 2B-2B ' of Fig. 2 A.
Fig. 3 A represents the part vertical view of United States Patent (USP) case number 6,492,716 disclosed integrated circuit (IC) chip.
Fig. 3 B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 3B-3B ' of Fig. 3 A.
Fig. 4 represents the vertical view according to the integrated circuit (IC) chip of the present invention's preferred embodiment.
Fig. 5 A represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 5A-5A ' of Fig. 4.
Fig. 5 B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 5B-5B ' of Fig. 4.
Fig. 6 represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 6-6 ' of Fig. 4.
Fig. 7 represents along near the part amplification plan view of the integrated circuit (IC) chip the breach of Fig. 4.
Fig. 8 A represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 8A-8A ' of Fig. 4.
Fig. 8 B represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 8B-8B ' of Fig. 4.
The amplification plan view of the integrated circuit (IC) chip of the part of Fig. 9 presentation graphs 4.
The drawing reference numeral explanation
10,20,40,70: integrated circuit (IC) chip
11,21a, 21b, 41,71: fixed sealing ring
12,42,73: digital circuit
12a, 13a, 73a, 74a: output/input pad
13,24,43,74: radio circuit
14,25,57: silicon substrate
15,58:P type trap
16,27:P type heavily doped layer (P+)
17a, 17b, 17c, 34a, 34b, 34c, 34d, 34e, 34f, 53a, 53b, 53c, 53d, 53e, 53f, 61a, 61b, 61c, 61d, 61e, 61f: metal level
18a, 18b, 18c, 30a, 30b, 30c, 30d, 30e, 30f, 50a, 50b, 50c, 50d, 50e, 50f, 60a, 60b, 60c: dielectric layer
18d, 31: sheath
18e, 32,52,60d: nitride layer
19a, 19b, 19c, 54a, 54b, 54c, 54d, 54e, 54f: through hole
22: the output/input pad of digital circuit
23: ground mat
26,45:N type trap
28,46: metal silicide layer
29,48: shallow groove isolation layer
33: polyimide
35a, 35b, 35c, 35d, 35e, 35f, 62a, 62b, 62c, 62d, 62e, 62f: contact layer
44:P type silicon substrate
47: gate oxide
49: polysilicon layer
51,60d: oxide skin(coating)
55,56: protective ring
55a: the first base closed zone
56a: the second base closed zone
58a: a P type trap
58b: the 2nd P type trap
58c, 59c: opening
59a: a P type heavily doped layer (P+)
59b: the 2nd P type heavily doped layer (P+)
71a, 71b: breach
71c: first fixed sealing ring
71d: second fixed sealing ring
72: ground loop
72a: first ground loop
72b: second ground loop
63:N type doped layer
64: separator
65a, 65b: active region
90: power ring
Embodiment
Please be simultaneously with reference to the 4th～6 figure, Fig. 4 represents the vertical view according to the integrated circuit (IC) chip of the present invention's preferred embodiment, the 5th figure represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 5-5 ' of Fig. 4, and Fig. 6 represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 6-6 ' of Fig. 4.In the 4th～6 figure, integrated circuit (IC) chip 70 comprises a silicon substrate 57, fixed sealing ring (seal ring) 71, ground loop (ground ring) 72, at least one circuit and one output/input pad (input/output pad, I/O pad) and at least one protective ring (guard ring), for example be digital circuit 73, radio circuit 74 and protective ring 55 and 56.Wherein, digital circuit 73 and radio circuit 74 have an output/input pad 73a and a 74a respectively.Fixed sealing ring 71, ground loop 72, digital circuit 73, radio circuit 74, output/input pad 73a and 74a and protective ring 55 and 56 all are formed on the silicon substrate 57.Fixed sealing ring 71 is in order to being centered around around the integrated circuit (IC) chip 70, and surrounds digital circuit 73, radio circuit 74 and output/input pad 73a and 74a.Be fixed seal ring 71 of ground loop 72 is surrounded and is electrically connected with fixed sealing ring 71.Fixed sealing ring 71 and ground loop 72 are all discrete circulus, all has at least one breach, as breach 71a and 71b, make fixed sealing ring 71 be divided into the first fixed sealing ring 71c and the second fixed sealing ring 71d, ground loop 72 also is divided into the first ground loop 72a and the second ground loop 72b.Wherein, the second fixed sealing ring 71d and the second ground loop 72b just like as same U type structure, and the first fixed sealing ring 71c and the first ground loop 72a are just like as the U type structure of same handstand.In addition, digital circuit 73 and output/input pad 73a are adjacent to the first fixed sealing ring 71c and the first ground loop 72a, and radio circuit 74 and output/input pad 74a are adjacent to the second fixed sealing ring 71d and the second ground loop 72b.Protective ring 55 is arranged at the contiguous first fixed sealing ring 71c place, and is electrically connected with the first fixed sealing ring 71c.Protective ring 55 is essentially U type structure, and centers on formation one first base closed zone 55a with the first fixed sealing ring 71c.In like manner, protective ring 56 is arranged at the contiguous second fixed sealing ring 71d place, and is electrically connected with the second fixed sealing ring 71d.Protective ring 56 also is U type structure basically, and centers on formation one second base closed zone 56a with the second fixed sealing ring 71d.Output/input pad 73a is formed in the 55a of first base closed zone, and output/input pad 74a is formed in the 56a of second base closed zone.
Please refer to Fig. 5 A, the part amplification profile of the integrated circuit (IC) chip that its expression is looked along the hatching 5A-5A ' of Fig. 4.In Fig. 5 A, the first fixed sealing ring 71c be centered around in mode along the part periphery extension of silicon substrate 57 Fig. 4 part integrated circuit (IC) chip 70 around, the first fixed sealing ring 71c comprises P type trap (p well) 58a, P type heavily doped layer (P+) 59a, several dielectric layers, several metal levels and several contact layers, for example is dielectric layer 60a～60c, metal level 61a～61c and contact layer 62a～62c.The one P type trap 58a is formed on the silicon substrate 57, and P type heavily doped layer (P+) 59a is formed among the P type trap 58a, the surperficial copline of the surface of P type heavily doped layer (P+) 59a and a P type trap 58a.Dielectric layer 60a～60c from bottom to top is formed on the surface of a P type trap 58a and P type heavily doped layer (P+) 59a in regular turn, metal level 61a～61c is formed at respectively on dielectric layer 60a and the 60b, and metal level 61a and 61b are covered by dielectric layer 60b and 60c respectively.Wherein, the first ground loop 72a can be electrically connected with the metal level 61b of the first fixed sealing ring 71a.Contact layer 62a～62c is in order to be electrically connected P type heavily doped layer (P+) 59a and metal level 61a, metal level 61a and 61b and metal level 61b and 61c respectively.Wherein, contact layer 62a～62c can be through hole (via) or connector (plug).It should be noted that integrated circuit (IC) chip 70 also comprises monoxide layer 60d and mononitride layer 60e, oxide skin(coating) 60d is formed on the dielectric layer 60c, and covers metal level 61c.Nitride layer 60e is formed on the oxide skin(coating) 60d, and oxide skin(coating) 60d and nitride layer 60e i.e. the sheath of what is called.In addition, a metal level 61a and P type heavily doped layer (P+) 59a are extended toward the both sides of output/input pad 73a of Fig. 4 by the first fixed sealing ring 71c place, to form the protective ring 55 of Fig. 4.
Please refer to Fig. 5 B, the part amplification profile of the integrated circuit (IC) chip that its expression is looked along the hatching 5B-5B ' of Fig. 4.In Fig. 5 B, the second fixed sealing ring 71d be centered around in mode along the periphery extension of silicon substrate 57 Fig. 4 part integrated circuit (IC) chip 70 around, the second fixed sealing ring 71d comprises the 2nd P type trap 58b, the 2nd P type heavily doped layer (P+) 59b, dielectric layer 60a～60c, metal level 61d～61f and contact layer 62d～62f.The 2nd P type trap 58b is formed on the silicon substrate 57, and the 2nd P type heavily doped layer (P+) 59b is formed among the 2nd P type trap 58b, the surperficial copline of the surface of the 2nd P type heavily doped layer (P+) 59b and the 2nd P type trap 58b.Dielectric layer 60a～60c, oxide skin(coating) 60d and nitride layer 60e from bottom to top are formed on the surface of the 2nd P type trap 58b and the 2nd P type heavily doped layer (P+) 59b in regular turn, metal level 61d～61f is formed at respectively on dielectric layer 60a～60c, and is covered by dielectric layer 60b, 60c and oxide skin(coating) 60d.Wherein, the second ground loop 72b can be electrically connected with the metal level 61e of the second fixed sealing ring 71d.Contact layer 62d～62f is in order to be electrically connected the 2nd P type heavily doped layer (P+) 59b and metal level 61d, metal level 61d and 61e and metal level 61e and 61f respectively.Wherein, contact layer 62d～62f can be through hole or connector.It should be noted that metal level 61d and the 2nd P type heavily doped layer (P+) 59b are extended toward the both sides of output/input pad 74a of Fig. 4 by the second fixed sealing ring 71d place, to form the protective ring 56 of Fig. 4.
Please be simultaneously with reference to Fig. 6 and Fig. 7, Fig. 6 represents the part amplification profile of the integrated circuit (IC) chip of being looked along the hatching 6-6 ' of Fig. 4, Fig. 7 represents along near the part amplification plan view of the integrated circuit (IC) chip the breach of Fig. 4.In Fig. 6 and Fig. 7, fixed sealing ring 71 also comprises a N type doped layer 63 and a separator 64, and has an opening 58c between a P type trap 58a and the 2nd P type trap 58b.N type doped layer 63 is formed among the opening 58c, and is positioned on the silicon substrate 57, isolated P type trap 58a of N type doped layer 63 electricity and the 2nd P type trap 58b.Has an opening 59c between the one P type heavily doped layer (P+) 59a and the 2nd P type heavily doped layer (P+) 59b, with corresponding to N type doped layer 63.Separator 64 forms among the opening 59c, and is positioned on the N type doped layer 63, isolated P type heavily doped layer (P+) 59a of separator 64 electricity and the 2nd P type heavily doped layer (P+) 59b.Has breach 71a between metal level 61a～61c and contact layer 62a～62c and metal level 61d～61f and the contact layer 62d～62f, the surface of the separator 64 of breach 71a expose portion.Wherein, dielectric layer 60a～60c from bottom to top forms the top that is arranged in breach 63 separators 64 in regular turn, makes that metal level 61a～61c and contact layer 62a～62c and metal level 61d～61f and contact layer 62d～62f electricity is isolated.Under the first fixed sealing ring 71c on breach 71a side the side active region (active region) 65a and the second fixed sealing ring 71d under the side active region 65b separated by N type doped layer 63.N type doped layer 63 can be N type trap (N well) or N type epitaxial loayer (N-epi), and separator 64 can for shallow groove isolation layer (shallowtrench isolation, STI) or field oxide (field oxide).
Can understand that by the explanation of Fig. 6 the present invention's fixed sealing ring 71 comprises a P type trap 58a, the 2nd P type trap 58b, N type doped layer 63, P type heavily doped layer (P+) 59a, the 2nd P type heavily doped layer (P+) 59b, separator 64, metal level 62a and 62b and dielectric layer 60a at least.The one P type trap 58a is formed on the silicon substrate 57, and the 2nd P type trap 58b is formed at a contiguous P type trap 58a place.N type doped layer 63 is formed between a P type trap 58a and the 2nd P type trap 58b, makes a P type trap 58a and the 2nd P type trap 58b electricity isolated.The one P type heavily doped layer (P+) 59a is formed on the P type trap 58a, and the 2nd P type heavily doped layer (P+) 59b is formed on the 2nd P type trap 58b.Separator 64 is formed between P type heavily doped layer (P+) 59a and the 2nd P type heavily doped layer (P+) 59b, makes P type heavily doped layer (P+) 59a and the 2nd P type heavily doped layer (P+) 59b electricity isolated.Metal level 61a directly or indirectly is formed on P type heavily doped layer (P+) 59a, and is electrically connected with P type heavily doped layer (P+) 59a.Metal level 61d directly or indirectly is formed on the 2nd P type heavily doped layer (P+) 59b, and is electrically connected with the 2nd P type heavily doped layer (P+) 59b.Dielectric layer 60a is formed between metal level 61a and the 61d, makes metal level 61a and 61d electricity isolated.
Please refer to Fig. 6, because the N type doped layer 63 of side is formed between a P type trap 58a and the 2nd P type trap 58b under the breach 71a, in breach 71a respectively with the intersection of the first fixed sealing ring 71c and the second fixed sealing ring 71d, form 2 PN junctions (junction) that oppositely link to each other between a N type doped layer 63 and a P type trap 58a and the 2nd P type trap 58b, and make noise can't be sent to the second fixed sealing ring 71d of breach 71a opposite side via N type doped layer 63 from the first fixed sealing ring 71c of breach 71a one side.So, the noise that can avoid digital circuit 73 to be produced effectively is sent to radio circuit 74 via fixed sealing ring 71.In addition, the electric charge that is produced with plasma etching manufactured fixed sealing ring 71 time can be respectively passes to silicon substrate 57 via P type heavily doped layer (P+) 59a and a P type trap 58a and the 2nd P type heavily doped layer (P+) 59b and the 2nd P type trap 58b, to avoid electric charge to accumulate on the fixed sealing ring 71, can keep the electric quality of integrated circuit (IC) chip 70.
Please refer to Fig. 8 A, the part amplification profile of the integrated circuit (IC) chip that its expression is looked along the hatching 8A-8A ' of Fig. 4.Please also refer to Fig. 5 A and Fig. 6, in Fig. 8 A, the first ground loop 72a is formed between silicon substrate 57 and the output/input pad 73a, and protective ring 55 is electrically connected by a metal level 61a and P type heavily doped layer (P+) 59a and forms, and around output/input pad 73a.
Please refer to Fig. 8 B, the part amplification profile of the integrated circuit (IC) chip that its expression is looked along the hatching 8B-8B ' of Fig. 4.Please also refer to Fig. 5 B and Fig. 6, in Fig. 8 B, the second ground loop 72b is formed between silicon substrate 57 and the output/input pad 74a, and protective ring 56 is electrically connected by metal level 61d and the 2nd P type heavily doped layer (P+) 59b and forms, and around output/input pad 74a.
Owing to have capacity effect between the P type trap 58a of output/input pad 73a and below thereof, and has capacity effect between the 2nd P type trap 58b of output/input pad 74a and below thereof, so when output/input pad 73a and 74a received noise, noise coupling earlier laid respectively at a P type trap 58a and the 2nd P type trap 58b square under output/input pad 73a and the 74a.Then, be sent to the first fixed sealing ring 71c and the first ground loop 72a and the second fixed sealing ring 71d and the second ground loop 72b respectively via the protective ring 55 and 56 around output/input pad 73a and the 74a.So, can get rid of output/input pad 73a and the received noise of 74a effectively.In addition, from protective ring 55 and 56 peripheral transfers and the noise that comes can also be sent to the first fixed sealing ring 71c and the first ground loop 72a and the second fixed sealing ring 71d and the second ground loop 72b respectively via protective ring 55 and 56, to avoid interference output/input pad 73a and 74a.Thus, protective ring 55 and 56 can be promptly conducts to earth terminal with the noise of protective ring 55 and 56 near zones, so that output/input pad 73a and 74a avoid noise jamming.For two adjacent output/input pads, its peripheral protective ring more can avoid these two adjacent output/input pads to produce wrong signal feedback path.
Please refer to Fig. 9, the amplification plan view of the integrated circuit (IC) chip of the part of its presentation graphs 4.In Fig. 9, integrated circuit (IC) chip 70 also comprises power ring (power ring) 90, the power ring 90 and the first ground loop 72a partly are formed at the below of output/input pad 55, and half of the bottom surface of each approximately corresponding output/input pad 73a of power ring 90 and the first ground loop 72a.Wherein, the power ring 90 and the first ground loop 72a are except the conventional use of the ground connection that can be used as circuit and power supply, these two can be used as the output/input pad 73a of the 8th figure and the shielding between the P type trap 58a as the power ring 90 of becket and the configuration of the first ground loop 72a, stop the phase mutual interference of noise each other.In like manner, another power ring and the second ground loop 72b are formed at the below of output/input pad 74a, can be used as the shielding between output/input pad 74a and the 2nd P type trap 58b, stop the phase mutual interference of noise each other.
The disclosed integrated circuit (IC) chip of the above embodiment of the present invention, the design that its fixed sealing ring, ground loop and protective ring are electrically connected mutually can reduce the coupling noise degree, and can avoid producing the phenomenon of electric charge accumulation, to promote the electrical characteristics of integrated circuit (IC) chip.
In sum; though the present invention discloses as above in conjunction with a preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention should be looked the accompanying Claim person of defining and is as the criterion.
Claims (25)
1. integrated circuit (IC) chip comprises:
One silicon substrate;
At least one circuit is formed on this silicon substrate, and this circuit has at least one output/input pad (input/output pad, I/O pad);
One fixed sealing ring (seal ring) is formed on this silicon substrate, and around this circuit and this output/input pad;
One ground loop (ground ring) is formed between this silicon substrate and this output/input pad, and is electrically connected with this fixed sealing ring; And
At least one protective ring (guard ring) is arranged on this silicon substrate, and around this output/input pad, in order to be electrically connected with this fixed sealing ring.
2. integrated circuit (IC) chip as claimed in claim 1, wherein this protective ring is electrically connected the protective ring that forms by a P type heavily doped layer (P+) and a metal level.
3. integrated circuit (IC) chip as claimed in claim 1, wherein this circuit is a digital circuit.
4. integrated circuit (IC) chip as claimed in claim 1, wherein this circuit is an analog circuit.
5. integrated circuit (IC) chip as claimed in claim 1, wherein this circuit is a radio circuit.
6. a fixed sealing ring extends in around the silicon substrate, and this fixed sealing ring comprises:
One P type trap (P well) is formed on this silicon substrate, and has one first opening;
One N type doped layer is formed in this first opening, and is positioned on this silicon substrate;
One P type heavily doped layer (P+) is formed on this P type trap, and has one second opening, and this second opening is corresponding to this N type doped layer;
One separator forms in this second opening, and is positioned on this N type doped layer;
A plurality of dielectric layers are formed on this P type heavily doped layer (P+); And
A plurality of metal levels, respectively this metal level is formed on respectively this dielectric layer of correspondence, and is electrically connected with this P type heavily doped layer (P+), and those metal levels have a breach, this separator of this breach expose portion.
7. fixed sealing ring as claimed in claim 6, wherein this fixed sealing ring also comprises:
A plurality of contact layers, respectively this contact layer is formed in respectively this dielectric layer of correspondence, one contact layer is in order to be electrically connected this P type heavily doped layer (P+) and to be adjacent to this metal level of this P type heavily doped layer (P+), and respectively this contact layer of all the other those contact layers is in order to be electrically connected two adjacent these metal levels.
8. fixed sealing ring as claimed in claim 7, wherein those contact layers are a plurality of through holes (via).
9. fixed sealing ring as claimed in claim 7, wherein those contact layers are a plurality of connectors (plug).
10. fixed sealing ring as claimed in claim 6, wherein the size of this second opening is more than or equal to the surface area of this N type doped layer.
11. fixed sealing ring as claimed in claim 6, the wherein surperficial copline of the surface of this N type doped layer and this P type trap.
12. fixed sealing ring as claimed in claim 6, the wherein surperficial copline of the surface of this separator and this P type heavily doped layer (P+).
13. fixed sealing ring as claimed in claim 6, wherein this N type doped layer is a N type trap (Nwell).
14. fixed sealing ring as claimed in claim 6, wherein this N type doped layer is a N type epitaxial loayer (N-epi).
15. fixed sealing ring as claimed in claim 6, wherein this separator be shallow groove isolation layer (shallow trench isolation, STI).
16. fixed sealing ring as claimed in claim 6, wherein this separator is field oxide (fieldoxide).
17. an integrated circuit (IC) chip comprises:
One silicon substrate;
One first fixed sealing ring is extended along this silicon substrate periphery;
One first protective ring is arranged at contiguous this first fixed sealing ring place and is electrically connected with this first fixed sealing ring, this first protective ring be essentially the U type and and this first fixed sealing ring between around formation one first base closed zone; And
One first output/input pad is formed in this first base closed zone.
18. integrated circuit (IC) chip as claimed in claim 17, wherein this first protective ring has one first end points, and this first end points extends to this silicon substrate periphery and is electrically connected with this fixed sealing ring.
19. integrated circuit (IC) chip as claimed in claim 17, wherein this integrated circuit (IC) chip also comprises:
One second fixed sealing ring is extended along this silicon substrate periphery, and isolated with this first fixed sealing ring electricity;
One second protective ring is arranged at contiguous this second fixed sealing ring place and is electrically connected with this second fixed sealing ring, this second protective ring be essentially the U type and and this second fixed sealing ring between around formation one second base closed zone; And
One second output/input pad is formed in this second base closed zone.
20. integrated circuit (IC) chip as claimed in claim 19, wherein this first output/input pad is linked to a radio circuit, and this second output/input pad is linked to a digital circuit.
21. a fixed sealing ring extends in around the silicon substrate, this fixed sealing ring comprises:
One the one P type trap is formed on this silicon substrate;
One the 2nd P type trap is formed at a contiguous P type trap place;
One N type doped layer is formed between a P type trap and the 2nd P type trap, makes a P type trap and the 2nd P type trap electricity isolated;
One the one P type heavily doped layer is formed on the P type trap;
One the 2nd P type heavily doped layer is formed on the 2nd P type trap;
One separator is formed between a P type heavily doped layer and the 2nd P type heavily doped layer, makes a P type heavily doped layer and the 2nd P type heavily doped layer electricity isolated;
One the first metal layer directly or indirectly is formed on the P type heavily doped layer, and is electrically connected with a P type heavily doped layer;
One second metal level directly or indirectly is formed on the 2nd P type heavily doped layer, and is electrically connected with the 2nd P type heavily doped layer; And
One dielectric layer is formed between this first metal layer and this second metal level, makes this first metal layer and this second metal level electricity isolated.
22. fixed sealing ring as claimed in claim 21, wherein this fixed sealing ring also comprises:
One first dielectric layer and one first contact layer are formed between this first metal layer and the P type heavily doped layer, and this first metal layer is electrically connected with a P type heavily doped layer by this first contact layer; And
One second dielectric layer and one second contact layer are formed between this second metal level and the 2nd P type heavily doped layer, and this second metal level is electrically connected with the 2nd P type heavily doped layer by this second contact layer.
23. fixed sealing ring as claimed in claim 22, wherein this first contact layer is a connector or a through hole.
24. fixed sealing ring as claimed in claim 22, wherein this second contact layer is a connector or a through hole.
25. fixed sealing ring as claimed in claim 21, wherein this separator is a shallow groove isolation layer or a field oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101188378A CN1320647C (en) | 2003-11-28 | 2003-11-28 | Integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101188378A CN1320647C (en) | 2003-11-28 | 2003-11-28 | Integrated circuit chip |
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| Publication Number | Publication Date |
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| CN1622324A CN1622324A (en) | 2005-06-01 |
| CN1320647C true CN1320647C (en) | 2007-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101188378A Expired - Lifetime CN1320647C (en) | 2003-11-28 | 2003-11-28 | Integrated circuit chip |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8587023B2 (en) * | 2005-05-25 | 2013-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Guard rings with local coupling capacitance |
| CN101442048B (en) * | 2007-11-23 | 2010-09-08 | 上海华虹Nec电子有限公司 | Grounding loop structure of radio frequency CMOS integration inductance |
| US8188578B2 (en) * | 2008-05-29 | 2012-05-29 | Mediatek Inc. | Seal ring structure for integrated circuits |
| TWI632568B (en) * | 2017-12-12 | 2018-08-11 | 絡達科技股份有限公司 | On-chip balun transformer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492716B1 (en) * | 2001-04-30 | 2002-12-10 | Zeevo, Inc. | Seal ring structure for IC containing integrated digital/RF/analog circuits and functions |
| US6537849B1 (en) * | 2001-08-22 | 2003-03-25 | Taiwan Semiconductor Manufacturing Company | Seal ring structure for radio frequency integrated circuits |
| CN1437257A (en) * | 2002-02-06 | 2003-08-20 | 台湾积体电路制造股份有限公司 | Wafer structure |
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2003
- 2003-11-28 CN CNB2003101188378A patent/CN1320647C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492716B1 (en) * | 2001-04-30 | 2002-12-10 | Zeevo, Inc. | Seal ring structure for IC containing integrated digital/RF/analog circuits and functions |
| US6537849B1 (en) * | 2001-08-22 | 2003-03-25 | Taiwan Semiconductor Manufacturing Company | Seal ring structure for radio frequency integrated circuits |
| CN1437257A (en) * | 2002-02-06 | 2003-08-20 | 台湾积体电路制造股份有限公司 | Wafer structure |
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| CN1622324A (en) | 2005-06-01 |
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