CN101441556A - DRAM controller and implementing method thereof - Google Patents
DRAM controller and implementing method thereof Download PDFInfo
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- CN101441556A CN101441556A CNA2008102032622A CN200810203262A CN101441556A CN 101441556 A CN101441556 A CN 101441556A CN A2008102032622 A CNA2008102032622 A CN A2008102032622A CN 200810203262 A CN200810203262 A CN 200810203262A CN 101441556 A CN101441556 A CN 101441556A
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Abstract
The invention provides an optimal DRAM controller and a realization method thereof. The DRAM controller optimizes periodical operation, cures an instruction of the periodical operation into an ROM memory, and simulates a control signal of the prior DRAM controller through the on-chip ROM memory, so as to reduce use of logical resources and the power consumption and the area of a chip. Moreover, compared with the prior DRAM controller, the optimal DRAM controller reduces the difficulty of system integration.
Description
Technical field
The present invention relates to dynamic RAM (Dynamic Random-Access Memory is called for short DRAM) design field, particularly a kind of dram controller and its implementation.
Background technology
DRAM is a kind of high-density storage, dram controller in the market has two kinds, be respectively synchronous dynamic random access memory (Synchronous Dynamic Random-Access Memory, be called for short SDRAM) and the dynamic storer of double-speed (Double Data Rate Dynamic Random-Access Memory is called for short DDR DRAM).Because DRAM can only preserve the very short time with data, so must refresh once every a period of time.Its all operations mode is divided into initialization operation, uses required read-write operation (abbreviation application operating) and self refresh operation.The aforesaid operations mode all is to change by the address wire of DRAM and the level on the control line to realize, the sequential relationship that these level change is determined, can arrive by the data check that DRAM manufacturer provides.When DRAM is used for a kind of periodical operation, refer to promptly that at set intervals just need carry out identical operations one time to the DRAM storer, this operation can be an operational order, also can be the combination of many operational orders.Both can be the same the interval time of two operations, also can be different, but must be less than the self-refresh cycle length of DRAM.If use general dram controller at present this moment, promptly adopt the method for finite state machine to realize control, then need outside to dram controller input corresponding instruction, could start the corresponding operating of dram controller, this implementation method need be used a large amount of logical resources, thereby has increased power consumption.
Summary of the invention
The purpose of this invention is to provide a kind of dram controller and its implementation, the DRAM control of described controller and the applicable periodical operation of implementation method.Write down the state of each control signal of each constantly general dram controller output by time-scale, and preserve; Call the initialization operation code of storage in advance then, the application operating code, the self refresh operation code is simulated the signal of general dram controller and is exported, and reads in order at every turn, realizes once complete periodical operation.The present invention can reduce the use of logical resource by this method, and no longer needs outside input instruction.
In order to solve the problems of the technologies described above, the present invention has adopted following technological means: a kind of dram controller, be used for transmitting control signal to a DRAM, and described dram controller comprises a state generation module, wherein, described state generation module is made up of ROM storer and address generator; Described address generator receives the startup enable signal of an outside input and the state enable signal that the ROM storer sends, and read enable signal and read address signal to ROM storer output, described ROM storer is read enable signal and is read address signal output corresponding D RAM control signal according to described.
Described ROM storer be divided between two connected storages by the address and two free areas between, deposit DRAM initialization operation code time sequence status table between first connected storage, the entry address is the setup code entry address; Deposit application operating code time sequence status table and self refresh operation code time sequence status table between second connected storage, the entry address is application operating code entry address; Alternately arrange between described connected storage and between described free area.
Described address generator is made up of a totalizer and an exclusive disjunction device, the input signal of address generator is that starting impulse and state enable, both generate to start enable signal after by the exclusive disjunction device and input to totalizer, and totalizer is exported its calculated result as reading the address.
The enable signal of reading of described address generator output is 0 o'clock, and the DRAM control signal of ROM storer output is complete 1, and described DRAM does not have corresponding operating; The enable signal of reading of described address generator output is 1 o'clock, and the operation code of the operation code time sequence status table correspondence of address sensing is read in the output of ROM storer, promptly exports corresponding D RAM control signal.
When DRAM was dual rate, described dram controller also comprised a two/single-rate converter, and the I/O data of dram controller are carried out rate transition.
Another program of the present invention has provided a kind of implementation method of dram controller, and in order to realize the periodical operation to DRAM, described method specifically realizes by following steps:
Step 2, initialization operation code time sequence status table is kept at the initialization operation code interval of ROM storer, start address is the setup code entry address; Application operating code time sequence status table and self refresh operation code time sequence status table combine, and are kept at the application operating interval of ROM storer, and start address is application operating code entry address;
Step 3, startup is enabled to enable to act on address generator with state, generation is read enable signal and is exported the ROM storer to, totalizer in the address generator, its initial value is the setup code entry address, when the startup enable signal was available state, totalizer was carried out the operation that adds up, when the startup enable signal is invalid attitude, totalizer is reset to application operating code entry address, and described address generator is exported as reading the address with the value of totalizer;
After step 4, ROM storer were received and read to enable and read address signal, when reading to enable to effective status, the operation code of the operation code time sequence status table correspondence pointed to the address was read in the output of ROM storer, promptly exports corresponding D RAM control signal; When reading to enable to invalid attitude, export entirely 1, DRAM does not have corresponding operating.
In the above method when DRAM is the dual rate storer, described method also comprises the step of the I/O data of dram controller being carried out two/single-rate conversion, with two of transmission/reception monolateral along the data input two/the single-rate modular converter, form bilateral along data.
The present invention makes it compared with prior art owing to adopted above-mentioned technical scheme, has following advantage and good effect:
1. compare general dram controller, the present invention uses the ROM storer, can reduce the use of logical resource in a large number, because the power consumption of ROM storer and power consumption and the area that area all is less than logical circuit, thereby has reduced the power consumption and the area of chip;
2. general dram controller needs input instruction, and the present invention has preserved the instruction that will carry out in advance, so reduced the application difficulty, is convenient to the system integration;
3. for the different application mode, only need to revise the memory contents of ROM storer, do not need to do the change on the hardware, be convenient to safeguard and upgrading.
Description of drawings
Dram controller of the present invention and its implementation are provided by following embodiment and accompanying drawing.
Fig. 1 is a dram controller structural representation of the present invention;
Fig. 2 is the ROM memory allocation synoptic diagram of dram controller in the concrete embodiment of the present invention;
Fig. 3 is address generating structure synoptic diagram in the dram controller in the concrete embodiment of the present invention;
Fig. 4 is the structural representation of dram controller in the concrete embodiment of the present invention.
Embodiment
Below will be described in further detail dram controller of the present invention and its implementation.
The dram controller apparatus structure in the present embodiment and the connected mode of each module are as shown in Figure 4.This device has three parts and forms: ROM storer, address generator and two/single-rate converter; Wherein ROM storer and address generator constitute state generation module jointly.The inner space of ROM storer be divided between two connected storages by the address and two free areas between, as shown in Figure 2, deposit DRAM initialization operation code time sequence status table between first connected storage, the entry address is 0x0100, deposit application operating code time sequence status table and self refresh operation code time sequence status table between second connected storage, the entry address is 0x0000, and the address is 0x00FF between first free area, and the address is 0x1FFF between second free area.In order to reach the purpose of periodically controlling the DRAM operation, initialization operation code time sequence status table, operation code time sequence status table and self refresh operation code time sequence status table in the ROM storer, have been stored in advance, as shown in Figure 2, these time sequence status table records each state of each control signal that need export of dram controller constantly, read initialization operation code, application operating code, the self refresh operation code of storage in advance then in order according to the address, the signal output of analog D RAM controller can realize once complete periodical operation.Wherein, the ROM storer be output as general dram controller the output control signal wire (A0～A12, BA0～BA1, CKE, CK/CK, CS, WE, CAS, RAS) and a state enable signal.Above-mentioned three modules all are integrated on the XC3S100E-4VQG100 chip of Xilinx company, and the DRAM device is the DDR RAM device of Micron company: MT46V16M16P-5B:F.
Referring to Fig. 3, described ROM address generation module is by one 13 bit accumulator, one two input exclusive disjunction device is formed, the generation startup enabled after the starting impulse of outside input and state enable pass were crossed two input exclusive disjunctions, the initial value of totalizer is 0x0100, when totalizer when startup enables to available state, carry out once from adding 1 operation; When startup enables to invalid attitude, be reset to 0x0000, the state value of totalizer is output as reads the address, starts to enable to be output as to read enable signal.
Two registers in the described pair/single-rate converter are respectively just along register and negative edge register, two two bits that register is imported in the synchronization sampling, clock be output in 0 o'clock just along the value of register, be the value of 1 o'clock output negative edge register at clock.
Another program of the present invention has provided a kind of implementation method of dram controller, and in order to realize the periodical operation to DRAM, this method realizes by following steps:
Step 2, initialization operation code time sequence status table is kept at the initialization operation code interval, start address is setup code entry address 0x0100; Application operating code time sequence status table and self refresh operation code time sequence status table combine, and are kept at the application operating interval, and start address is application operating code entry address 0x0000;
Step 3, startup is enabled to enable to act on address generator with state, generation reads to enable, totalizer in the address generator, its initial value is the setup code entry address, when the startup enable signal was available state, totalizer was carried out the operation that adds up, when the startup enable signal is invalid attitude, totalizer is reset to application operating code entry address, and the state value of totalizer is as reading address output;
After step 4, ROM storer were received and read to enable and read address signal, when reading to enable to effective status, the operation code of the operation code time sequence status table correspondence pointed to the address was read in the output of ROM storer, promptly exports corresponding D RAM control signal; When reading to enable to invalid attitude, export entirely 1, DRAM does not have corresponding operating.
In the above method when DRAM is the dual rate storer, two of transmission monolateral along the data input two/the single-rate modular converter, form bilateral along data; When if DRAM is the single-rate storer, then do not need to import two/single-rate modular converter, directly input and output.
In sum, adopt dram controller and its implementation of optimization of the present invention, can satisfy the demand of periodical operation, reduced chip area and power consumption again simultaneously, reduced system integration difficulty.
Claims (7)
1, a kind of dram controller is used for transmitting control signal to a DRAM, and described dram controller comprises a state generation module, it is characterized in that: described state generation module is made up of ROM storer and address generator; Described address generator receives the startup enable signal of an outside input and the state enable signal that the ROM storer sends, and read enable signal and read address signal to ROM storer output, described ROM storer is read enable signal and is read address signal output corresponding D RAM control signal according to described.
2, dram controller as claimed in claim 1, it is characterized in that: described ROM storer be divided between two connected storages by the address and two free areas between, deposit DRAM initialization operation code time sequence status table between first connected storage, the entry address is the setup code entry address; Deposit application operating code time sequence status table and self refresh operation code time sequence status table between second connected storage, the entry address is application operating code entry address; Alternately arrange between described connected storage and between described free area.
3, dram controller as claimed in claim 1, it is characterized in that: described address generator is made up of a totalizer and an exclusive disjunction device, the input signal of address generator is that starting impulse and state enable, both generate to start enable signal after by the exclusive disjunction device and input to totalizer, and totalizer is exported its calculated result as reading the address.
4, dram controller as claimed in claim 3 is characterized in that: the enable signal of reading of described address generator output is 0 o'clock, and the DRAM control signal of ROM storer output is complete 1, and described DRAM does not have corresponding operating; The enable signal of reading of described address generator output is 1 o'clock, and the operation code of the operation code time sequence status table correspondence of address sensing is read in the output of ROM storer, promptly exports corresponding D RAM control signal.
5, dram controller as claimed in claim 1 is characterized in that: when DRAM was dual rate, described dram controller also comprised a two/single-rate converter, and the I/O data of dram controller are carried out rate transition.
6, a kind of implementation method of dram controller as claimed in claim 1 is characterized in that: described method specifically realizes by following steps:
Step 1, according to time sequencing, generate application operating code time sequence status table, initialization operation code time sequence status table and the self refresh operation code time sequence status table of dram controller respectively;
Step 2, initialization operation code time sequence status table is kept at the initialization operation code interval of ROM storer, start address is the setup code entry address; Application operating code time sequence status table and self refresh operation code time sequence status table combine, and are kept at the application operating interval of ROM storer, and start address is application operating code entry address;
Step 3, startup is enabled to enable to act on address generator with state, generation is read enable signal and is exported the ROM storer to, totalizer in the address generator, its initial value is the setup code entry address, when the startup enable signal was available state, totalizer was carried out the operation that adds up, when the startup enable signal is invalid attitude, totalizer is reset to application operating code entry address, and described address generator is exported as reading the address with the value of totalizer;
After step 4, ROM storer were received and read to enable and read address signal, when reading to enable to effective status, the operation code of the operation code time sequence status table correspondence pointed to the address was read in the output of ROM storer, promptly exports corresponding D RAM control signal; When reading to enable to invalid attitude, export entirely 1, DRAM does not have corresponding operating.
7, the implementation method of dram controller as claimed in claim 6, it is characterized in that: when DRAM is the dual rate storer, described method also comprises the step of the I/O data of dram controller being carried out two/single-rate conversion, with two of transmission/reception monolateral along the data input two/the single-rate modular converter, form bilateral along data.
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| CNA2008102032622A CN101441556A (en) | 2008-11-24 | 2008-11-24 | DRAM controller and implementing method thereof |
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| CNA2008102032622A CN101441556A (en) | 2008-11-24 | 2008-11-24 | DRAM controller and implementing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811047A (en) * | 2014-02-17 | 2014-05-21 | 上海新储集成电路有限公司 | Low-power-consumption refreshing method based on block DRAM (dynamic random access memory) |
| CN111522753A (en) * | 2019-12-11 | 2020-08-11 | 中国船舶重工集团公司第七0九研究所 | SDRAM (synchronous dynamic random access memory) control method and system based on state machine |
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- 2008-11-24 CN CNA2008102032622A patent/CN101441556A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811047A (en) * | 2014-02-17 | 2014-05-21 | 上海新储集成电路有限公司 | Low-power-consumption refreshing method based on block DRAM (dynamic random access memory) |
| CN103811047B (en) * | 2014-02-17 | 2017-01-18 | 上海新储集成电路有限公司 | Low-power-consumption refreshing method based on block DRAM (dynamic random access memory) |
| CN111522753A (en) * | 2019-12-11 | 2020-08-11 | 中国船舶重工集团公司第七0九研究所 | SDRAM (synchronous dynamic random access memory) control method and system based on state machine |
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Open date: 20090527 |