CN101430737A - Wavelet transformation-improved VLSI structure design method - Google Patents

Abstract

The invention discloses a method for designing a super-large-scale integrated circuit VLSI structure used for lifting wavelet transformation, which mainly solves the problem of long time delay of a critical path and high hardware consumption in the prior art. The designing process comprises the following steps: changing an arithmetic sequence for lifting the wavelet transformation, so that operations of intermediate values are in different paths; carrying out parallel arithmetic on the intermediate values on different paths by a delay register; selecting a longest path in the different paths as a critical path, and adding a pipeline register on the critical path; regarding a multistage pipeline structure, respectively adding a selector at the input end of a system and a multiplier, returning an intermediate value which is subject to primary wavelet lifting to the input end, alternately selecting intermediate values in different lifting stages by the selector, and storing results in the added register. The method of the invention effectively reduces critical path time delay of the system, and reduces hardware resource overhead, so that the utilization rate of the hardware can reach 100 percent. The method is applicable to design realization of VLSI.

Description

The VLSI construction design method of lifting wavelet transform

Technical field

The invention belongs to VLSI (very large scale integrated circuit) VLSI design field, be specifically related to a kind of realization lifting wavelet transform structure Design method.

Background technology

Wavelet transform has been widely used in fields such as signal Processing, compression of images, Video processing, and has been adopted by the JPEG2000 Standard of image compression owing to have good time-frequency local characteristics.Therefore the VLSI structure of discrete wavelet transformation has great importance.The VLSI structure of present existing realization wavelet transform can reduce: based on the structure of convolution algorithm with based on the structure of boosting algorithm.Compare with structure, have remarkable advantages at computation complexity and required aspects such as memory resource, become the focus of research at present based on the structure of boosting algorithm based on convolution algorithm.

People such as J.M.Jou article " Efficient VLSI architectures for the biorthogonal wavelettransform by filter bank and lifting scheme; " Proc.IEEE Int.Sym.Circuits Syst., 2001, a kind of direct organization that realizes Lifting Wavelet has been proposed among the pp.529-532..This structural design is simple, be easy to hardware realizes, takies a large amount of hardware resources but the shortcoming of this structure is the running water line, and this structure is the direct mapping of 9/7 small echo, and corresponding two-stage promotes operation.For 5/3 small echo, because it has only one-level to promote, thereby this moment, the hardware utilization factor had only 50%.In order to reduce the hardware resource expense, to improve the hardware utilization factor, C.J.Lian etc. on the basis of above-mentioned direct organization in calendar year 2001 article " Lifting based discrete wavelettransform architecture for JPEG2000; " in Proc.IEEE Int.Sym.Circuits Syst., Sydney, Australia, 2001, a kind of Folded structure has been proposed among the pp.445-448..This structure promotes operation based on the one-level of 5/3 small echo, and for the two-stage lifting operation of 9/7 small echo, it turns back to input end with first order operation result and then carries out promoting the second time operation.This structure has reduced the consumption of hardware resource to a great extent, makes that its required arithmetic resource only is half of direct organization.With respect to direct organization certain reduction has been arranged again but the shortcoming of this structure is its maximum operation frequency, and required storer number is still many.Shortcoming in view of above structure existence, C.T.Huang equal 2004 article " Flipping structure:an efficientVLSI architecture for lifting based discrete wavelet transform; " IEEE Trans.SignalProcess., vol.52, no.4, pp.1080-1089 has proposed a kind of improvement boosting algorithm that improves frequency of operation under the situation that does not increase hardware resource among the Apr.2004..The main thought of this algorithm is that multiply operation is transferred on the compute node from the input node, has eliminated multiply operation on the feasible path of adding up, thereby the time-delay of shortening critical path improves the system works frequency.On the basis of this algorithm, the author has proposed a kind of Flipping structure that realizes Lifting Wavelet.Afterwards people such as B.F.Wu in 2005 article " A high-performance andmemory-efficient pipeline architectures for the 5/3 and9/7 discrete wavelet transformof JPEG2000 codec; " IEEE Trans.Circuits Syst Video Technol., vol.15, no.12, pp.1615-1628 has also proposed a kind of improved boosting algorithm among the Dec.2005..The main thought of this algorithm is that prediction in the lifting process and renewal are merged into a step, thereby improves the system works frequency and reduce hardware resource consumption.But all there is the high and necessary problem of considering round-off error of implementation complexity in above-mentioned two kinds of structures based on the improvement algorithm, and practical application has certain degree of difficulty.

Summary of the invention

The objective of the invention is to overcome the defective and the deficiency that exist in the above-mentioned background technology, a kind of frequency of operation height is provided, hardware resource consumption is few, the hardware utilization factor is high and simple in structure, be easy to the lifting wavelet transform VLSI construction design method realizing and expand.

Realize the technical scheme of the object of the invention, comprise the steps:

(1) order of operation of change Lifting Wavelet algorithm makes the calculating of some intermediate values be in different paths;

(2) by delay time register, the intermediate value that is on the different paths is carried out concurrent operation;

(3) select path the longest in the different paths as critical path, and on this critical path, add pipeline register;

(4) for the pipeline organization of two-stage Lifting Wavelet, input end at system and first order multiplier adds selector switch, to turn back to input end through the intermediate value of first order Lifting Wavelet,, the result will be stored in the register of interpolation by the different intermediate values that promote level of selector switch alternate selection.

Described improved Lifting Wavelet algorithm carries out in such a way:

First order Lifting Wavelet algorithm changes into:

$d_i^1=d_i^0+\mathrm{\α}\×(s_i^0+s_{i+1}^0)\⇒d_i^1=(d_i^0+\mathrm{\α}\×s_i^0)+\mathrm{\α}\×s_{i+1}^0,$

$s_i^1=s_i^0+\mathrm{\β}\×(d_{i-1}^1+d_i^1)\⇒s_i^1=(s_i^0+\mathrm{\β}\×d_{i-1}^1)+\mathrm{\β}\×d_i^1.$

Second level Lifting Wavelet algorithm changes into:

$d_i^2=d_i^1+\mathrm{\γ}\×(s_i^1+s_{i+1}^1)\⇒d_i^2=(d_i^1+\mathrm{\γ}\×s_i^1)+\mathrm{\γ}\×s_{i+1}^1,$

$s_i^2=s_i^1+\mathrm{\δ}\×(d_{i-1}^2+d_i^2)\⇒s_i^2=(s_i^1+\mathrm{\δ}\×d_{i-1}^2)+\mathrm{\δ}\×d_i^2.$

Wherein constant alpha is the predictor of first order Lifting Wavelet, and β is the renewal factor of first order Lifting Wavelet, and γ is the predictor of second level Lifting Wavelet, and δ is the renewal factor of second level Lifting Wavelet, $d_i^0=x_{2n+1},$ $s_i^0=x_{2n},$ x _iBe the input of system, x _2n+1The value of odd number sequence in the expression input, x _2nThe value of even number sequence in the expression input,

The high frequency output that expression l level promotes,

The low frequency output that expression l level promotes.

The present invention compares with classic method has following advantage:

1) because the present invention has adopted parallel processing technique and pipelining simultaneously, so system is input to the time-delay of the required critical path of output and shortens, and the frequency of operation of system is greatly improved;

2), make and realize that the required hardware resource of lifting wavelet transform reduces that the hardware utilization factor almost reaches 100% because the present invention has adopted the resource time-sharing multiplexing technology;

3) add technology by displacement and replace multiply operation, further reduced operand, reduced hardware spending with shift register and totalizer;

4) because the present invention is to improving the direct mapping of Lifting Wavelet algorithm, the improvement Lifting Wavelet algorithm that proposes among the present invention simultaneously can expand to other wavelet transformations easily, therefore have simplicity of design, rule, be easy to characteristics such as expansion, be very suitable for VLSI (very large scale integrated circuit) VLSI design realization.

Description of drawings

Fig. 1 is the process flow diagram of implementation method of the present invention;

Fig. 2 is string and the modular converter block diagram of realizing with the inventive method;

Fig. 3 is the small echo main transformer die change piece block diagram of realizing with the inventive method;

Fig. 4 realizes and string conversion and normalization module block diagram with the inventive method.

Embodiment

The present invention is described in detail below in conjunction with drawings and Examples.

What use in an embodiment of the present invention is wavelet filter-CDF 5/3 and 9/7 biorthogonal wavelet that adopts in the JPEG2000 standard, but is not limited to use this two kinds of wavelet filters.

With reference to Fig. 1, the present invention is based on the VLSI Architecture of Discrete Wavelet Transformation method for designing of boosting algorithm, may further comprise the steps:

Step 1: will import serial sequence x (i) and split into corresponding odd sequence x _(2n+1)With even sequence x _(2n), for small echo main transformer die change piece provides input.In design, adopt as shown in Figure 2 a delay time register D and two on-off circuit K ₁And K ₂Realize the odd even separation of list entries.

Step 2: change the order of operation of Lifting Wavelet algorithm, make the intermediate value that was in same paths and sequential operation originally be in different paths.The order of described improvement Lifting Wavelet algorithm is carried out in such a way:

First order Lifting Wavelet algorithm is changed into:

$d_i^1=d_i^0+\mathrm{\α}\×(s_i^0+s_{i+1}^0)\⇒d_i^1=(d_i^0+\mathrm{\α}\×s_i^0)+\mathrm{\α}\×s_{i+1}^0,---\left(1\right)$

$s_i^1=s_i^0+\mathrm{\β}\×(d_{i-1}^1+d_i^1)\⇒s_i^1=(s_i^0+\mathrm{\β}\×d_{i-1}^1)+\mathrm{\β}\×d_i^1.---\left(2\right)$

Second level Lifting Wavelet algorithm is changed into:

$d_i^2=d_i^1+\mathrm{\γ}\×(s_i^1+s_{i+1}^1)\⇒d_i^2=(d_i^1+\mathrm{\γ}\×s_i^1)+\mathrm{\γ}\×s_{i+1}^1,---\left(3\right)$

$s_i^2=s_i^1+\mathrm{\δ}\×(d_{i-1}^2+d_i^2)\⇒s_i^2=(s_i^1+\mathrm{\δ}\×d_{i-1}^2)+\mathrm{\δ}\×d_i^2.---\left(4\right)$

Wherein constant alpha is the predictor of first order Lifting Wavelet, and β is the renewal factor of first order Lifting Wavelet, and γ is the predictor of second level Lifting Wavelet, and δ is the renewal factor of second level Lifting Wavelet, $d_i^0=x_{2n+1},$ $s_i^0=x_{2n},$ x _iBe the input of system, x _2n+1The value of odd number sequence in the expression input, x _2nThe value of even number sequence in the expression input,

The high frequency output that expression l level promotes,

The low frequency output that expression l level promotes.

Step 3:, the intermediate value that is on the different paths is carried out concurrent operation by delay time register.The elder generation of the algorithm after the change order of operation is with the intermediate value in (1) formula

(2) intermediate value in the formula (3) intermediate value in the formula

(4) intermediate value in the formula

Be on the different paths, again by on each paths, adding the first delay time register D as shown in Figure 3 ₁, the second delay time register D ₂, the 3rd delay time register D ₃With the 4th delay time register D ₄Realization is carried out concurrent operation to the intermediate value that these are on the different paths.

Step 4: select the longest in each paths of concurrent operation one as critical path, and on critical path, add pipeline register.In the present embodiment by between Lifting Wavelet at different levels prediction, step of updating and the input end of system add the first pipeline register P ₁, the second pipeline register P ₂, the 3rd pipeline register P ₃, the 4th pipeline register P ₄, the 5th pipeline register P ₅With the 6th pipeline register P ₆Realize the three class pipeline structure, as shown in Figure 3,, further improve the concurrency of system to realize the pipeline organization design.

Step 5: for the pipeline organization of two-stage Lifting Wavelet, multiplier input in system and first order lifting computing adds selector switch, to turn back to input end through the intermediate value of first order Lifting Wavelet, by the different intermediate values that promote level of selector switch alternate selection, the result is stored in the register of interpolation.In design, add first selector S by input end in system ₁With second selector S ₂, to select to be input to system's initial value or promote the value that computing is returned through the first order, two multiplier inputs that promote computing in the first order add selector switch third selector S respectively ₃With the 4th selector switch S ₄, be respectively applied for and select the first order and partial Lifting Wavelet coefficient, as shown in Figure 3.The pipeline organization of She Ji Lifting Wavelet can be saved the original second level and promote the required hardware configuration of computing in this way, has reduced hardware resource consumption, has improved resource utilization.

Described multiplier is realized with shift register and totalizer.Here be example with the factor alpha in 9/7 Lifting Wavelet, introduce the concrete grammar and the process that replace multiply operation with shift register and totalizer.The binary mode of this wavelet coefficient α is: α=(1.586134342) ₁₀=(1.1001011000001) ₂, when an intermediate value N multiplies each other with it,, therefore get the complement code N of N earlier because α is a negative, then:

α×N＝N+N>>1+N>>4+N>>6+N>>7+N>>13.　　　　　　　　　　　(5)

Further extract the minimum common factor in the expression formula (5), then have:

α×N＝(N+N>>6)+(N+N>>6)>>7+(N+N>>3)>>1.。

Step 6: to two outputs of high and low frequency of the wavelet transformation that obtains through above step, by the 5th selector switch S ₅Translation function is finished and is gone here and there in the output of this high and low frequency of alternate selection, and by the 6th selector switch S ₆Select normalization coefficient 1/K or K to realize the normalization that high frequency or low frequency are exported, finally obtain the wavelet transformation y (i) of x (i), as shown in Figure 4.

With reference to Fig. 3, as follows with the principle of work of the small echo main transformer die change piece of the inventive method design:

A.5/3 the course of work of small echo:

Because only comprising one-level, 5/3 small echo promotes computing, therefore the 5th pipeline register P ₅With the 6th pipeline register P ₆The data of output do not need to turn back to input end, simultaneously in order to ensure correct lifting process, need bypass to fall the 3rd delay time register D ₃With the 4th delay time register D ₄, wavelet coefficient is selected the coefficient of 5/3 small echo by third and fourth selector switch.The concrete course of work is: the input that odd sequence after string and the conversion and even sequence change as the small echo main transformer, even number point multiplied each other with selected 5/3 filter coefficient earlier and promptly added realization with being shifted this moment, was stored in the first delay time register D with the odd point addition again ₁In.During next even number point input, still multiply each other with 5/3 filter coefficient earlier, more respectively with the odd point and the first delay time register D that import this moment ₁The intermediate value addition of middle storage, and be input to the first delay time register D respectively ₁With the 3rd pipeline register P ₃, this moment P ₃In value be exactly to the value after last odd point prediction, the 4th pipeline register P ₄In the storage be exactly original even number point.Follow-up processing is similar to said process, only with the 3rd pipeline register P ₃Odd point after the middle prediction upgrades the 4th pipeline register P ₄In original even number point.After forecast updating is finished, realize that high and low frequency is exported and the string conversion,, realize the normalization operation of high frequency or low frequency output at last through selector switch selection normalization coefficient 1/K or K and serial output multiplication through selector switch.

B.9/7 the course of work of small echo:

Because 9/7 wavelet transformation process comprises two-stage lifting computing, after one-level lifting computing is finished, the 5th pipeline register P ₅With the 6th pipeline register P ₆The data of output will turn back to register P respectively ₁And P ₂Do the second level and promote computing, select the corresponding coefficient of 9/7 small echo afterwards by selector switch, make the first order lifting and the second level promote computing and hocket.The input similar with 5/3 small echo calculating process, that odd sequence after string and the conversion and even sequence change as the small echo main transformer, the second pipeline register P at this moment ₂The 9/7 wavelet coefficient α that the even number point of output is chosen with selector switch earlier multiplies each other and promptly adds realization with being shifted, more respectively with the first pipeline register P ₁The odd point and the 3rd delay time register D of output ₃The intermediate value addition of output is stored in the first delay time register D respectively ₁With the 3rd pipeline register P ₃In, this P ₃The value of middle storage is exactly the value after a certain odd point process one-level promotes computing.This moment, input end was by first selector S ₁With the 2nd S ₂Selection is from the 5th pipeline register P ₅With the 6th pipeline register P ₆Value after the first order lifting computing of returning is to the first pipeline register P ₁With the second pipeline register P ₂Next moment, this P ₂Output from the 6th pipeline register P ₆The first order of returning promotes the value after the computing and passes through third selector S ₃The 9/7 wavelet coefficient γ that chooses multiplies each other, more respectively with the first pipeline register P ₁The value and the 3rd delay time register D of middle output ₃The last one intermediate value addition of calculating gained constantly according to rreturn value of middle output outputs to the first delay time register D respectively ₁With the 3rd pipeline register P ₃, this moment this P ₃In value be exactly prediction to some odd points, the 4th pipeline register P ₄In storage be exactly that corresponding with it one-level promotes even number point after the computing.Follow-up processing is similar to said process.That supposes that the small echo main transformer changes is input as

With

The concrete course of work of 9/7 wavelet transformation is as shown in table 1.Wherein $d_i^0=x_{2n+1},$ $s_i^0=x_{2n},$

With

The result that expression l level promotes.After two-stage promotes and finishes, through the 5th selector switch S ₅Realize the also string conversion of high and low frequency output, at last through the 6th selector switch S ₆Select normalization coefficient 1/K or K and serial output multiplication, realize the normalization operation of high frequency or output.

Data stream under the table 1 CDF-9/7 small echo mode of operation (* expression invalid data)

Effect of the present invention can further specify by comparing with existing wavelet transformation structure:

As can be seen from Figure 3, the structure of the inventive method design only needs 3 multipliers, 4 totalizers, 4 delay time registers and 6 pipeline registers.The structure that proposes in this structure and the background technology is carried out performance relatively, and the result is as shown in table 2.

The performance of table 2 present embodiment structure and other structure is (is example with the CDF-9/7 small echo) relatively

As can be seen from Table 2, the structure in the present embodiment is occupied minimum arithmetic resource, and promptly the number by multiplier and totalizer determines, and the critical path time-delay only is T _m+ T _a, T wherein _mFor multiplier postpones, T _aBe the totalizer time-delay, though this critical path time-delay is than the long T of structure of the full level production line of existing Jou+, Huang+5 level production line and Wu _aBut the structure that the present invention proposes only needs 10 registers, is better than this three kinds of structures.In addition, the advantage that structure of the present invention has simplicity of design, is easy to expand is suitable for the VLSI design and realizes.

Claims (5)

1. the VLSI construction design method of a lifting wavelet transform comprises the steps:

(1) order of operation of change Lifting Wavelet algorithm makes the calculating of some intermediate values be in different paths;

(2) by delay register, the intermediate value that is on the different paths is carried out concurrent operation;

(3) select path the longest in the different paths as critical path, and on this critical path, add pipeline register;

(4) for multi-stage pipeline arrangement, input end at system and multiplier adds selector switch, to turn back to input end through the intermediate value of first order Lifting Wavelet,, the result will be stored in the register of interpolation by the different intermediate values that promote level of selector switch alternate selection.

2. the method for claim 1, the described change Lifting Wavelet of step (1) algorithm order of operation wherein, carry out in such a way:

First order Lifting Wavelet algorithm is changed into:

$d_i^1=d_i^0+\mathrm{\α}\×(s_i^0+s_{i+1}^0)\⇒d_i^1=(d_i^0+\mathrm{\α}\×s_i^0)+\mathrm{\α}\×s_{i+1}^0,$

$s_i^1=s_i^0+\mathrm{\β}\×(d_{i-1}^1+d_i^1)\⇒s_i^1=(s_i^0+\mathrm{\β}\×d_{i-1}^1)+\mathrm{\β}\×d_i^1.$

Second level Lifting Wavelet algorithm is changed into:

$d_i^2=d_i^1+\mathrm{\γ}\×(s_i^1+s_{i+1}^1)\⇒d_i^2=(d_i^1+\mathrm{\γ}\×s_i^1)+\mathrm{\γ}\×s_{i+1}^1,$

$s_i^2=s_i^1+\mathrm{\δ}\×(d_{i-1}^2+d_i^2)\⇒s_i^2=(s_i^1+\mathrm{\δ}\×d_{i-1}^2)+\mathrm{\δ}\×d_i^2.$

Wherein constant alpha is the predictor of first order Lifting Wavelet, and β is the renewal factor of first order Lifting Wavelet,

Be the predictor of second level Lifting Wavelet, δ is the renewal factor of second level Lifting Wavelet, $d_i^0=x_{2n+1},$ $s_i^0=x_{2n},$ x _iBe the input of system, x _2n+1The value of odd number sequence in the expression input, x _2nThe value of even number sequence in the expression input,

The high frequency output that expression l level promotes,

The low frequency output that expression l level promotes.

3. the method for claim 1, wherein step (3) is described adds pipeline register on this critical path, be between the Lifting Wavelet at different levels after changing order of operation and system input adds.

4. method as claimed in claim 2, the multiply operation in the boosting algorithms wherein at different levels realizes by shift register and totalizer.

5. method as claimed in claim 4, wherein said operation by shift register and totalizer realization multiplication, carry out as follows:

1) be binary mode with the Lifting Wavelet coefficient quantization;

2) by the displacement of described intermediate value being realized wavelet coefficient and this real number of binary mode multiply each other, the fraction part with real number of promptly respectively the integral part of real number the being moved to left addition behind the i position that moves to right, wherein i is to be 1 position in the scale-of-two;

3) the minimum common factor in the expression formula after the extraction addition is with the expression formula addition once more behind the minimum common factor of extraction.

Images