CN101430665A - Write-protection prevention method for basic input/output system - Google Patents
Write-protection prevention method for basic input/output system Download PDFInfo
- Publication number
- CN101430665A CN101430665A CNA2007101669728A CN200710166972A CN101430665A CN 101430665 A CN101430665 A CN 101430665A CN A2007101669728 A CNA2007101669728 A CN A2007101669728A CN 200710166972 A CN200710166972 A CN 200710166972A CN 101430665 A CN101430665 A CN 101430665A
- Authority
- CN
- China
- Prior art keywords
- block
- write
- level
- basic input
- output system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a write protection method of a basic input-output system, and is applicable to a programmable memory which is provided with a first block and a second block. The write protection method comprises the following steps: firstly, generating a first signal according to a conduction state of a jumper switch; reading the first signal to judge whether the first block is in a write protection state; and converting level of a second signal into a first level to perform the write protection on the second block when the first block is in the write protection state. Therefore, the first block and the second block of the programmable memory can be in the write protection state at the same time, so the data in the basic input-output system can be effectively protected.
Description
Technical field
The invention relates to a kind of Write-protection prevention method, and particularly relevant for a kind of Write-protection prevention method of Basic Input or Output System (BIOS).
Background technology
In general, Basic Input or Output System (BIOS) (Basic Input Output System is hereinafter to be referred as BIOS) is stored in the programmable storage (programmable memory), and occupies critical role in computer system.In order to guarantee the stability of computer system, and do not wish, and cause computer system to use because some maloperations make BIOS upgrade mistake.Therefore, the user must prevent writing to the programmable storage of storage BIOS, with the data of protection BIOS.
Just store the programmable storage of BIOS at present; for example be chip SST49LF080A; this chip is to utilize write protection (Write Protect; hereinafter to be referred as WP#) signal, top start locking (Top BootLock; hereinafter to be referred as TBL#) signal, whether the data of controlling BIOS need to prevent writing.Wherein, the TBL# signal is used for protecting the data of programmable storage top 64KB, and the WP# signal then is used for protecting programmable storage top 64KB data in addition.
Specifically, in order to the start block (boot block) of storage BIOS, its shared memory size usually can be greater than 64KB in the programmable storage.Therefore, in conventional art, the Write-protection prevention method of BIOS can be made as logical one with the level of WP# signal, and the data beyond the 64KB of top continue to be in the non-anti-state of writing in the programmable storage to cause.As for the part of top 64KB in the storer, then decide it whether to be in and prevent writing state, because the connected mode of wire jumper can switch to the level of TBL# signal logical zero or logical one by the last wire jumper of mainboard (motherboard) (jumper).It should be noted that size when the start block during, depend merely on the TBL# signal and just can't realize protection fully the block of starting shooting greater than 64KB.
Summary of the invention
The invention provides a kind of Write-protection prevention method of Basic Input or Output System (BIOS), can protect the data in the storer of storing Basic Input or Output System (BIOS) by this perfectly.
The present invention proposes a kind of Write-protection prevention method of Basic Input or Output System (BIOS), is applicable to programmable storage, and this programmable storage has first block and second block.Above-mentioned Write-protection prevention method comprises the following steps: the conducting state according to a jumper switch, produces first signal.Read first signal.Judge whether first block is in the anti-state of writing.When first block is in anti-ly when writing state, be first level with the level conversion of secondary signal, so that second block is carried out Write-protection prevention.
In an embodiment of the present invention, above-mentioned Write-protection prevention method also comprises: the original state of secondary signal is set at second level.In addition, when above-mentioned first level was logical zero, second level then was a logical one.Or when above-mentioned first level is logical one, and second level then is a logical zero.
In an embodiment of the present invention, above-mentioned Write-protection prevention method also comprises: when first block is in non-anti-ly when writing state, upgrade the data in the programmable storage.In addition, first signal can see through the first general transmission interface and transmit, and secondary signal can transmit through the second general transmission interface.In addition, above-mentioned programmable storage for example is Erasable Programmable Read Only Memory EPROM (erasable programmable read only memory, EPROM), programmable read only memory (programmable read only memory, PROM) or flash memory (flash memory).
The present invention judges by reading first signal that jumper switch produces whether first block of programmable storage is in the anti-state of writing.When first block of programmable storage is in anti-ly when writing state, then adjust the level of secondary signal, so that second block of programmable storage is also carried out Write-protection prevention.Thus, first block of programmable storage and second block promptly can be fully by Write-protection preventions, and needn't worry when the shared storer of start block big or small excessive, and the data of start block can't be fully protected.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates the part circuit block diagram into the computer system of one embodiment of the invention.
Fig. 2 illustrates the Write-protection prevention method process flow diagram into the Basic Input or Output System (BIOS) of one embodiment of the invention.
Embodiment
Before spirit of the present invention being described, suppose that at first the Write-protection prevention method of Basic Input or Output System (BIOS) of the present invention is applicable to various types of computer systems with embodiment.For instance, Fig. 1 illustrates the system block diagrams into general computer system, and wherein computer system 100 comprises jumper switch 110, South Bridge chip 120 and programmable storage 130, and programmable storage 130 comprises first block and second block.
In whole start, first block of programmable storage 130 can determine whether to carry out Write-protection prevention by the level of the first signal TBL.For example, when the first signal TBL is enabled, when just the level of the first signal TBL is switched to first level, then the data of first block of programmable storage 130 will be in the anti-state of writing, otherwise first block of programmable storage 130 will be in the non-anti-state of writing.In addition, second block of programmable storage 130 also can determine whether to carry out Write-protection prevention by the level of secondary signal WP.For example, when secondary signal WP is enabled, when just the level of secondary signal WP is switched to first level, then second block of programmable storage 130 will be in the anti-state of writing.To be familiar with this operator and more to understand spirit of the present invention in order to allow, the computer system 100 that Fig. 1 illustrated of below will arranging in pairs or groups illustrates the Write-protection prevention method of Basic Input or Output System (BIOS) of the present invention.
Fig. 2 illustrates the Write-protection prevention method process flow diagram into the Basic Input or Output System (BIOS) of one embodiment of the invention.Please be simultaneously with reference to Fig. 1 and Fig. 2, at first, in step S202, South Bridge chip 120 can see through general transmission interface (general purpose input/output, GPIO) 150, the original levels of the secondary signal WP of programmable storage 130 is set at second level, makes second block of programmable storage 130 be in the non-anti-state of writing.
Then, in step S204, computer system 100 produces the first signal TBL according to the conducting state of jumper switch 110.For instance, when jumper switch 110 enables (that is jumper switch 110 conductings), then produce the first signal TBL with first level.Otherwise, when jumper switch 110 forbidden energy (that is jumper switch 110 not conductings), then produce the first signal TBL with second level.
Afterwards, in step S206, South Bridge chip 120 sees through general transmission interface 140 and reads the first signal TBL.Then, in step S208, South Bridge chip 120 judges according to the level of the first signal TBL whether first block of programmable storage 130 is in the anti-state of writing.For instance, when the level of the first signal TBL switches to first level, first block of programmable storage 130 will be in the anti-state of writing, that is the South Bridge chip 120 of this moment can't write data to the first block.Otherwise when the level of the first signal TBL switched to second level, then first block of programmable storage 130 was in the non-anti-state of writing, that is the South Bridge chip 120 of this moment can write data to the first block at any time.
Please continue with reference to Fig. 1 and Fig. 2.When first block of programmable storage 130 is in anti-ly when writing state, then carry out step S210.In step S210, South Bridge chip 120 can be with level conversion to the first level of secondary signal WP, and sees through general transmission interface 150 and be sent to programmable storage 130.At this moment, second block of programmable storage 130 will be in to be prevented writing state, makes that the data in second block can't be changed.
On the other hand, when first block of programmable storage 130 during, then carry out step S212 not by Write-protection prevention.At this moment, because the level of secondary signal WP also maintains second level, that is second block of programmable storage 130 is not by Write-protection prevention.Therefore, in step S212, computer system 100 just can be upgraded the data in the programmable storage 130.That is to say,, then can write to programmable storage 130 at any time, so that carry out the more action of new data if computer system 100 detects newer BIOS more during new data.
What deserves to be mentioned is that in the present embodiment, when the first signal TBL is detected when switching to first level, the level of secondary signal WP will be switched immediately to first level.In other words, first block of programmable storage 130 and second block can be in the anti-state of writing simultaneously.Therefore, if the size of first block of programmable storage 130 is 64KB, and the size that is stored in the start block of programmable storage 130 is when surpassing 64KB, and computer system 100 still can be protected the data of start block effectively.
In addition, in the above-described embodiments, first level of secondary signal WP and second level are example with logical zero and logical one respectively, but present embodiment is not limited thereto.And this area has and knows the visual demand of the knowledgeable usually, first level of secondary signal is made as logical one, and second level of secondary signal is made as logical zero.In addition, in the above-described embodiments, programmable storage 130 for example is Erasable Programmable Read Only Memory EPROM (erasableprogrammable read only memory, EPROM), programmable read only memory (programmableread only memory, PROM) or flash memory (flash memory).
In sum, the present invention judges by reading first signal that jumper switch produces whether first block of programmable storage is write by anti-.When first block is in anti-ly when writing state, then adjust the level of secondary signal, so that second block of programmable storage is also carried out Write-protection prevention.By this, first block of programmable storage and second block can be in simultaneously to be prevented writing state, makes that the data in the Basic Input or Output System (BIOS) can be protected effectively.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (8)
1. the Write-protection prevention method of a Basic Input or Output System (BIOS) is applicable to a programmable storage, and this programmable storage comprises one first block and one second block, and this Write-protection prevention method comprises the following steps:
Conducting state according to a jumper switch produces one first signal;
Read this first signal;
Judge according to the level of this first signal whether this first block is in the anti-state of writing; And
When this first block is in anti-ly when writing state, be one first level with the level conversion of a secondary signal, so that this second block is carried out Write-protection prevention.
2. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 1 is characterized in that, also comprises:
The original levels of this secondary signal is set at one second level.
3. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 2 is characterized in that, this first level is a logical zero, and this second level is a logical one.
4. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 2 is characterized in that, this first level is a logical one, and this second level is a logical zero.
5. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 1 is characterized in that, also comprises:
When this first block is in non-anti-ly when writing state, upgrade the data in this programmable storage.
6. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 1 is characterized in that, also comprises:
See through one first general transmission interface and transmit this first signal.
7. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 1 is characterized in that, also comprises:
See through one second general transmission interface and transmit this secondary signal.
8. the Write-protection prevention method of Basic Input or Output System (BIOS) as claimed in claim 1 is characterized in that, this programmable storage is an Erasable Programmable Read Only Memory EPROM, a programmable read only memory or a flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101669728A CN101430665A (en) | 2007-11-08 | 2007-11-08 | Write-protection prevention method for basic input/output system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101669728A CN101430665A (en) | 2007-11-08 | 2007-11-08 | Write-protection prevention method for basic input/output system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101430665A true CN101430665A (en) | 2009-05-13 |
Family
ID=40646072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101669728A Pending CN101430665A (en) | 2007-11-08 | 2007-11-08 | Write-protection prevention method for basic input/output system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101430665A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194065A (en) * | 2010-03-16 | 2011-09-21 | 研祥智能科技股份有限公司 | Basic input output system (BIOS) lock and BIOS set permission control method |
| US20130173831A1 (en) * | 2011-12-29 | 2013-07-04 | Guo-Yi Chen | Protecting circuit for basic input output system chip |
| CN103927492A (en) * | 2013-01-14 | 2014-07-16 | 联想(北京)有限公司 | Data processing device and data protecting method |
| CN107817981A (en) * | 2017-11-23 | 2018-03-20 | 合肥联宝信息技术有限公司 | The control method and electronic equipment of a kind of embedded controller |
| CN108733586A (en) * | 2017-04-19 | 2018-11-02 | 北京兆易创新科技股份有限公司 | A kind of guard method and device |
-
2007
- 2007-11-08 CN CNA2007101669728A patent/CN101430665A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194065A (en) * | 2010-03-16 | 2011-09-21 | 研祥智能科技股份有限公司 | Basic input output system (BIOS) lock and BIOS set permission control method |
| CN102194065B (en) * | 2010-03-16 | 2015-01-07 | 研祥智能科技股份有限公司 | Basic input output system (BIOS) lock and BIOS set permission control method |
| US20130173831A1 (en) * | 2011-12-29 | 2013-07-04 | Guo-Yi Chen | Protecting circuit for basic input output system chip |
| US8930600B2 (en) * | 2011-12-29 | 2015-01-06 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Protecting circuit for basic input output system chip |
| CN103927492A (en) * | 2013-01-14 | 2014-07-16 | 联想(北京)有限公司 | Data processing device and data protecting method |
| CN103927492B (en) * | 2013-01-14 | 2018-01-23 | 联想(北京)有限公司 | A kind of data processing equipment and data guard method |
| CN108733586A (en) * | 2017-04-19 | 2018-11-02 | 北京兆易创新科技股份有限公司 | A kind of guard method and device |
| CN107817981A (en) * | 2017-11-23 | 2018-03-20 | 合肥联宝信息技术有限公司 | The control method and electronic equipment of a kind of embedded controller |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101918928B (en) | Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method | |
| CN101329632B (en) | Method and apparatus for starting CPU by BOOT | |
| CN100412894C (en) | Memory card and its initial setting method | |
| US20110099325A1 (en) | User device and mapping data management method thereof | |
| US7953913B2 (en) | Peripheral device locking mechanism | |
| CN101430665A (en) | Write-protection prevention method for basic input/output system | |
| KR20040027284A (en) | Memory system allowing fast operation of processor while using flash memory incapable of random access | |
| CN101501639A (en) | Flash memory access circuit | |
| KR20100092752A (en) | Nonvolatile memory device having a buffer ram and boot code management method thereof | |
| US20150052290A1 (en) | Data storage device and operating method thereof | |
| CN110543435B (en) | Mixed mapping operation method, device and equipment of storage unit and storage medium | |
| CN113485672B (en) | Information generation method, device, equipment and medium based on FIFO memory | |
| CN103064800A (en) | Power failure protection system and implementation method thereof | |
| US20090164740A1 (en) | Device and method for extracting memory data | |
| CN111143898B (en) | Data protection method for pluggable memory device | |
| KR100640588B1 (en) | Non-volatile memory storage device using SATA interface and ATA interface selectively | |
| CN1937080A (en) | NAND FLASH memory device | |
| EP2194458A2 (en) | Request processing device, request processing system, and access testing method | |
| KR20100067905A (en) | Interfacing unit and electric system including the same | |
| JP2009176147A (en) | Electronic equipment and method for determining permission of access to memory of electronic equipment | |
| US20090235365A1 (en) | Data access system | |
| CN113297581A (en) | Electronic device and secure firmware updating method thereof | |
| CN208240009U (en) | Data storage device and system | |
| CN113448401B (en) | Mainboard and server | |
| CN101097555B (en) | Method and system for processing data on chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090513 |