CN101425333A - High density resistor conversion memory and memory operation method thereof - Google Patents

Abstract

The invention belongs to the field of integrated circuit technology and in particular relates to a resistance-conversion memory and a method of conducting memory operations to the memory. The invention adopts binary or over-binary complex metal oxides (such as CuxOs with x being more than 1 and less than or equal to 2, WOxs with x being more than 2 and less than or equal to 3, titanium oxides, nickel oxides, zirconium oxides, aluminum oxides, niobium oxides, tantalum oxides and the like) as memory resistors, each memory module comprises two or more memory resistors, the first electrode of each memory resistor is connected with the same gating device, and the second electrode of each memory resistor is coupled with different bit lines, thus a structure that a plurality of memory resistors share the same gating device in the same memory module is formed. The memory operation comprises a method of write operation and a method of read operation. The memory can improve the integrated memory density significantly and the memory operation fails to interfere with the other modules.

Description

A kind of high density resistor transit storage and methods of storage operating thereof

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of electric resistance transition memory and reach the method for sort memory being carried out storage operation.

Background technology

Storer occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But because the requirement of stored charge, FLASH can not expand with the technology generation development is unrestricted, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.Recently electric resistance transition memory (resistive switching memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has phase-change material ^[1], the SrZrO that mixes ₃ ^[2], ferroelectric material PbZrTiO ₃ ^[3], ferromagnetic material Pr _1-xCa _xMnO ₃ ^[4], the binary metal oxide material ^[5], organic material ^[6]Deng.Binary metal oxide is (as Nb ₂O ₅, Al ₂O ₃, Ta ₂O ₅, Ti _xO, Ni _xO ^[5], Cu _xO ^[7]Deng) because accurately control at component, and ic process compatibility and cost aspect potential advantages especially paid close attention to.

Fig. 1 is the characteristic synoptic diagram of I-V of the resistive memory cell that has been in the news ^[7], be to adopt polarity different voltage to carry out conversion between high resistant and low-resistance (a), curve 101 has represented that primary state is the IV curve of high resistant, the voltage scanning direction increases to V when voltage since 0 to forward as shown by arrows gradually _T1The time, electric current can increase rapidly suddenly, shows that memory resistor is mutated into low resistive state from high resistant, and the electric current increase is not unconfined in the synoptic diagram, but be subjected to the constraint of current limiting element in the loop, no longer increase after arriving maximal value (hereinafter referred to as the value of clamping down on) with voltage.Curve 100 has represented that primary state is the state of low-resistance, gradually increases to V by 0 to negative sense when voltage _T2The time, electric current can reduce rapidly suddenly, shows that memory resistor is mutated into high-impedance state from low-resistance.High resistant is represented different data modes respectively with low-resistance, and this change is repeatedly reversible, can realize data storage thus.(b) be to adopt the identical voltage of polarity to carry out the situation of high resistant and low-resistance conversion, curve 101 and 100 represent respectively to adopt forward voltage make memory resistor by high resistant to low-resistance conversion (being called set operation) with by the process of low-resistance to high resistant conversion (being called reset operation), and 201 and 200 respectively expression adopt negative voltage make memory resistor by high resistant to the low-resistance conversion with by the process of low-resistance to the high resistant conversion.

Fig. 2 reports at present to Cu _xO resistance applies the mode of voltage when carrying out read-write operation.To Cu _xThe monopulse that it is 300ns that O resistance applies a pulsewidth when carrying out set behaviour and reset operation records Cu like this _xThe result of the number of times (hereinafter referred to as erasable number of times) that O resistance is changed between high resistant or resistance back and forth ^[7]Have about 600 times..

The binary metal oxide storer of report mainly adopts two kinds of structures at present ^{[5] [7]}: a kind of is the structure that a traditional gating device adds a memory resistor (1T1R), and another kind is crossed array (cross-point) structure.

Fig. 3 (a) (b) shows the circuit structure diagram and the physical arrangement diagrammatic cross-section of traditional 1T1R storage unit respectively.A memory resistor 200 and a gating device 100 are arranged in each storage unit 110, and memory resistor 200 directly is connected with an end 102 of gating device 100, and TE and BE represent the top electrode and the bottom electrode of resistance 200 respectively among the figure b.Gating device 100 adopts MOSFET (MOS (metal-oxide-semiconductor) memory) device in the diagram, and 200 the other end links to each other with bit line (being abbreviated as BL) 102.Bit line 102 just chooses the single resistance 200 of infall to carry out storage operation with word line 101 actings in conjunction.Gating device 100 make electric signal only to be coupling in word line-bit line intersect between single resistance operate, do not crosstalk and can not produce to other storage unit.The characteristics of this structure are between the different storage unit, and the phase mutual interference in storage operation is little, but gating device must be produced on the silicon chip substrate, takies silicon area.And 1 gating device can only be controlled a memory resistor.

Fig. 4 is the structural representation of a part of array that comprises the storer of a plurality of 1T1R storage unit, a plurality of storage unit repeated arrangement, it wherein in the frame of broken lines 100 a typical storage unit, contain a gating device 300 and a memory resistor that is attached thereto 200, the gating device that is arranged in the different storage unit of delegation links to each other with same word line WL, for example, gating device in the different storage unit in first row all links to each other with WL0, other is gone, all link to each other and be arranged in a same end that lists the resistance of different storage unit with same bit lines, for example, one end of the memory resistor in first row in the different storage unit all links to each other with bit line BL0, and other leu is analogized.Word line links to each other with 502 with line decoder 501, the effect of line decoder is to choose delegation, bit line links to each other with 602 with column decoder 601, the effect of column decoder is to choose row, the storage unit of row and column infall is exactly to choose the unit that will operate, and each row all links to each other with 702 with corresponding sense amplifier and driving 701.The effect of sense amplifier and driving 701 is to read and provide the electric signal that memory resistor is operated to the logic state of selected memory resistor.

Fig. 5 (a) (b) shows intersection (cross-point) array synoptic diagram, M ₁, M ₂, M ₃Represent first, second and third layer metal wire, the adjacent two layers metal wire links to each other by metal closures, and the metal closures while is as the bottom electrode of memory resistor.The interleaved array is characterised in that and is not used as the gating device of isolating between the storage unit that memory resistor directly is couple on orthogonal two metal line ^[8]The point of crossing that this two metal line is right and a storage unit are associated.The shortcoming of interleaved array is owing to do not isolate between the storage unit, so parasitic current (sneak current) is bigger, when causing selected cell operated, can cause maloperation to not producing serious disturbance between the selected cell.This shortcoming has reduced reliability, has increased the complexity of circuit design, has caused storer to read speed and has descended.But the advantage of interleaved array also clearly, and it can improve integration density greatly, and owing to reduced the gating device that need take silicon area, thereby can carry out stackedly in vertical direction, forms three-dimensional storage array.

Summary of the invention

The electric resistance transition memory spare that the object of the present invention is to provide a kind of high density, low operation to disturb reaches corresponding methods of storage operating, can realize high-density applications, and produces the not maloperation of selected cell can prevent storage operation the time.

The electric resistance transition memory spare that the present invention proposes, as memory resistor, comprise m bar word line, the n bit lines with binary or the multi-element metal oxide more than the binary, and several storage unit, each storage unit is positioned at each zone of intersection of a word line and several bit lines; All comprise the memory resistor that two or more are above-mentioned in each storage unit, first electrode of these memory resistor all is connected with same gating device, this gating device can be bipolar transistor (bipolar transistor) or mos field effect transistor (MOSFET) or diode, and is coupled by this gating device and the lead that is called word line; Second electrode of these memory resistor is coupled with the different leads that is called bit line, is formed on the structure of the shared same gating device of several memory resistor in the same storage unit.Here, m, n are not had too much restriction, can be 2≤m, n≤2 usually ¹⁰

In the said structure, different memory resistor in the same storage unit can be positioned on the multilayer interconnection metal line layer, the layer at each layer interconnect metallization lines layer and the storage medium place that is attached thereto constitutes a composite bed, the different composite layer carries out stacked in vertical direction, connect by the metal closures that is arranged in through hole between adjacent composite bed, form three-dimensional storage array.

In the structure of the present invention, in the same storage unit, the different memory resistor that first electrode links to each other with same gating device, different gating devices in its second electrode and the MUX connect, these gating devices can be bipolar transistor (bipolartransistor) or mos field effect transistor (MOSFET), and further connect, thereby realize memory resistor second electrode and being coupled of corresponding lines not with different bit line by these gating devices that are attached thereto.

The above multi-element metal oxide of binary of the present invention or binary can be Cu _xO (1＜x≤2), WO _xThe oxide of the oxide of the oxide of (2≤x≤3), nickel, titanyl compound, zirconium, the oxide of aluminium, niobium, the oxide of tantalum, the oxide of hafnium, the oxide of molybdenum, the oxide of zinc, SrZrO ₃, PbZrTiO ₃Or Pr _1-xCa _xMnO ₃It is pointed out that for above storage medium material because preparation technology and performance requirement can change to some extent, this should not regard limitation of the present invention as on stoichiometric proportion.Should also be noted that with the oxide material to be Main Ingredients and Appearance, carry out the small amount of impurities element doping therein improving performance,, should not regard limitation of the present invention as in the oxide of the oxide of the oxide of molybdenum or aluminium or zirconium, mixing trace copper.

The present invention proposes above storer is carried out the method for write operation.Read in advance before the write operation that data are gone in the data in the storage unit and formulation and compare, identical if data are gone in the data in the storage unit and formulation, do not carry out write operation, it is different to go into data as if the data in the storage unit and formulation, then carries out write operation.

The present invention proposes above storer is carried out the method for write operation.Be positioned at the same storage unit that lists and form a memory cell block, when initial all storage unit all are written as high resistant, write operation is unit with the memory cell block, when one in the memory cell block or several memory resistor need be rewritten as high resistant, choose all gating devices in the piece earlier, all memory resistor two ends are all added from low-resistance become the required electric signal of high resistant, memory resistor all in the piece all is erased to high resistant, be called overall erase status, choose the memory resistor that need be rewritten as low-resistance then successively, the two ends of these memory resistor are added from high resistant become the required electric signal of low-resistance, corresponding memory resistor is written as low-resistance, is called the condition programming state.When having only one or several memory resistor to be rewritten as low-resistance in the memory cell block and not having memory resistor to be rewritten as high resistant, skip overall erase status, directly the entry condition programming state is chosen the memory resistor that needs rewriting one by one, is rewritten into low-resistance one by one.

The concrete grammar that changes the data in the said memory cells is: low resistance state and high-impedance state all have distribution range.When will making resistance become high resistant by low-resistance, when the value of target memory resistor minimum value greater than the high resistant distribution range, think that then write operation is successful, when will making resistance become low-resistance by high resistant, when the value of target memory resistor maximal value, then think the write operation success less than the low-resistance distribution range.

In above-mentioned storer, memory resistor is a two terminal device, when carrying out write operation, adopts the voltage of opposite polarity to carry out by high resistant to low-resistance operation (reset operation) with by the operation (set operation) of low-resistance to high resistant.

The present invention proposes above storer is carried out the method for write operation.For the memory resistor two ends apply a plurality of pulses that write, the amplitude that writes pulse raises step by step during write operation.Each, the memory resistor two ends verify by read operation whether the resistance value of memory resistor has reached formulation and gone into the desired distribution of resistance scope of data after writing pulse for applying, if reaching formulation goes into the desired resistance value of data then stops write operation, do not go into the desired resistance value of data if reach formulation, then continue as the memory resistor two ends apply amplitude higher write pulse.

The present invention proposes to select the size of rational memory cell block to prevent that leakage current from not producing the method for maloperation to choosing memory resistor: according to the ratio of memory resistor high-impedance state resistance value and low resistive state resistance value

And the ratio M that may make the voltage of not choosing memory resistor generation maloperation and write operation voltage, in a memory cell block, choose the value of the number k of the value of the line number Y that satisfies following condition and the memory resistor in each storage unit: $\frac{1}{\frac{(Y-2)+(\mathrm{kY}-Y+2)*\frac{R}{r}}{k*(k-1)*\frac{R}{r}*\frac{R}{r}}+1}<M$ And $\frac{1}{\frac{(k-2)+(\mathrm{kY}-k+2)*\frac{R}{r}}{Y*(Y-1)*\frac{R}{r}*\frac{R}{r}}+1}<M.$

The method that the present invention's proposition is carried out read operation to above storer.The restriction maximal value (be provided with and clamp down on electric current) that the electric current by storage unit can arrive during read operation, the data of storage unit can not be changed under the effect of read signal like this, and this causes in the time of can being avoided reading to miss and writes.

The method that the present invention's proposition is carried out read operation to above storer.When carrying out read operation the data output state is divided into several parts, when the data in one of them part are sent to data output, all the other each several part data output states data that then acquisition will be output from sense amplifier.

The present invention also provides a kind of system that comprises electric resistance transition memory of the present invention, and it comprises a processor, and with the input and output of described processor communication, and the memory device that is coupled to this processor; Said memory device is an electric resistance transition memory spare provided by the invention.Comprise: several storage unit, all comprise two or more memory resistor in each storage unit, first electrode of these memory resistor all is connected with same gating device, these gating devices can be bipolar transistor (bipolar transistor) or mos field effect transistor (MOSFET) or diode, and be coupled by this gating device and the lead that is called word line, second electrode of memory resistor is coupled with the different leads that is called bit line, form several memory resistor and share the structure of same gating device, or the like.

The system that is provided can also comprise the wave point that is coupled to this processor.

Description of drawings

Fig. 1 is the I-V family curve of the electric resistance transition memory of present report.

Fig. 2 reports at present to Cu _xO resistance applies the mode of voltage when carrying out read-write operation.(this figure wants, and is unified with the front).

Fig. 3 is based on traditional 1T1R storage unit, its equivalent circuit diagram (a) and section of structure (b) for the electric resistance transition memory of reporting at present.

Fig. 4 is traditional memory array architecture based on the 1T1R storage unit.

The Cross-Point storage array of Fig. 5 binary metal oxide storer.

Fig. 6 is an embodiment diagram of electric resistance transition memory of the present invention.

Fig. 7 is the structural profile of 1TKR storage unit embodiment.

Fig. 8 is the partial circuit figure of the storage array of 1TKR storage unit formation.

Fig. 9 carries out the process flow diagram of write operation for electric resistance transition memory spare.

Figure 10 is the logic diagram of the embodiment of storing data state for a change.

Figure 11 is an embodiment diagram of judging stored data states in the write operation process.

Figure 12 carries out the embodiment diagram of writing driving circuit of programming operation for adopting the opposed polarity electric signal.

The embodiment that the electric resistance transition memory spare that Figure 13 proposes the present invention carries out addressing operation.

Figure 14 is the exemplary plot of leakage current among 1TkR of explanation.

Figure 15 (a) is the equivalent circuit diagram when among the 1TkR a certain memory resistor being operated.

Figure 15 (b) provides the embodiment that a storage unit block size is followed the example of.

Figure 16 applies the embodiment diagram of algorithm for the write operation pulse.

Figure 17 is the sequential diagram of write operation.

Figure 18 is the embodiment diagram of the design of sensor amplifier input stage.

Figure 19 clamps down on the empirical curve of electric current to the electric signal of memory resistor state change.

Figure 20 is the embodiment diagram of read operation method.

Figure 21 is a memory resistor and relative two embodiment ((a) and (b)) of through hole and interconnection line.

Figure 22 is the part diagram of system according to an embodiment of the invention.

Figure 23 is the part diagram of system according to still another embodiment of the invention.

Number in the figure: 100,101,102,103 are respectively the voltage scanning curve under the different conditions, 104 is the reference resistance of low-resistance, 105 is the reference resistance of high resistant, 100 is gating device, 101 is the gating device control end, 102 is the other end of gating device, 103 is an end of resistance 201,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216 is memory resistor, 301,302,303 is the com line, 600 is storage unit, 501,502 is line decoder, 601,602 is column decoder, 701,702 is sense amplifier/driver, 801 is the local bitline code translator, 802,803,804,805 is gate tube, 900 to 920 is the write operation flow process, 1000,1001,1002,1003,1004 is gating device, 1201,1202 is d type flip flop, 1300 is layer address, 1301 is column address, 1302 is row address, curve 1501, curve 1502, curve 1503, the embodiment that curve 1504 is followed the example of for the memory cell block array size, 1601,1603,1605,1607,1609 are read-after-write checking pulse, 1602,1604,1606,1608,1610 is write pulse, 1701 is overall erase status signal, 1702 is condition programming state signal, 1703 is data-signal to be written, 1704 is the input buffer signal, 1705,1706 is programming signal, 1707 is the sensor amplifier output signal, 1708 is that the final state signal is write in control, 1800,1801,1802,1803 are the PMOS pipe, 1804,1805,1806,1807,1808 are the NMOS pipe, 2000,2001,2002 are the PMOS pipe, 1603,1604,1605,1606,1607 are the NMOS pipe, 2011,2012,2021,2022 is output state, 2051,2052,2061,2062 is the NMOS transfer tube, 211a, 211b, 211c is respectively insulating medium layer, 213+ is the upper copper lead-in wire, 213-is lower floor's copper lead-in wire, 215a and 215b are the block dielectric layer, 217 is through hole, 218 are following embolism, 219 is the restraining barrier, 2200 is system, 2201 is controller, and 2203 is storer, and 2204 is I/O (I/O), 2205 is bus, 001 is data buffering, 002 is the programming Control module, and 003 is logic control, and 004 is impact damper, 005 is sensor amplifier, 006 is reference voltage, and 007 is the column decoder output signal, and 008 is the line decoder output signal.

Embodiment

Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.On the contrary, provide these embodiment, scope of the present invention is passed to those skilled in the relevant art fully so that this openly is completely and completely.

At this reference diagram is the synoptic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure.

Should be appreciated that when claiming an element when " on another element " or " on another element, extending ", this element can be directly at " on another element " or directly " on another element, extending ", or also may have insertion element.On the contrary, when claiming an element, there is not insertion element directly at " on another element " or directly when " on another element, extending ".When claiming an element with " another element is connected " or " coupling " with another element, this element can directly connect or be couple to another element, or also can there be insertion element, on the contrary, when claiming an element, there is not insertion element directly with " another element is connected " or direct " coupling " with another element.

The present invention relates to share as 1 above memory resistor in storage medium and the storage unit electric resistance transition memory and the methods of storage operating thereof of same gating device with binary or the multi-element metal oxide more than the binary.。The notion of storage unit described here is meant gating device and the compound storage unit that memory resistor constituted that is attached thereto.For ease of setting forth, the agreement storage unit is meant this duplex.

Accompanying drawing (1～5) is explained in the invention technical background.

1 embodiment of the electric resistance transition memory spare that the present invention proposes is described below with reference to Fig. 6.Fig. 6 shows the equivalent circuit diagram of storage unit 600, comprise 1 gating device 100 and k memory resistor, memory resistor is 201,202 according to this ..., k, gating device 100 adopts mos field effect transistor (MOSFET) in diagram, this gating device also can be bipolar transistor (bipolar transistor) or diode, first electrode of k memory resistor all directly links to each other with the same end S of gating device 100, second electrode then respectively with different bit line BL-1, BL-2 ..., BL-k is coupled.Gating device and word line WL_0 are coupled, and are that the control end 601 by MOSFET links to each other with word line in the present embodiment.Each intersection of word line-bit line is associated with an independent storage unit.Formed k memory resistor like this and shared the structure of same gating device, corresponding to traditional 1T1R structure, below we to be called for short this structure be the 1TkR structure.Notice that T represents gating device, rather than specially refers to transistor here.The variation of the kind of gating device should not regarded limitation of the present invention as.Adopt this structure, can under same piece of silicon area situation, improve the density of storer.

The above multi-element metal oxide of above-mentioned binary or binary can be Cu _xO1＜x≤2) ^[7], WO _x2≤x≤3), the oxide NiO of nickel ^[5]/ NiOx ^[9], titanyl compound TiO ₂ ^[5]/ TiO _x ^[9], zirconium oxide ZrO ₂ ^[5]/ ZrOx ^[10], aluminium oxide Al ₂O ₃ ^{[11] [12]}, niobium oxide Nb ₂O ₅ ^[10], tantalum oxide Ta ₂O ₅ ^[12], hafnium oxide HfO ₂ ^[5], molybdenum oxide M oOx ^{[11] [12]}, zinc oxide ZnO ^{[11] [12]}, SrZrO ₃ ^[2], PbZrTiO ₃ ^[3], Pr _1-xCa _xMnO ₃ ^[4]It is pointed out that for above storage medium material because preparation technology and performance requirement can change to some extent, this should not regard limitation of the present invention as on the stoichiometric proportion of element.Should also be noted that with the oxide material to be main component, carry out the small amount of impurities element doping therein improving performance, as in the oxide of the oxide of the oxide of molybdenum or aluminium or zirconium, mixing trace copper ^[11], in the oxide of zinc, mix aluminium ^[11], at SrZrO ₃In mix C _r ^[2], and for example at PbZrTiO ₃In mix La ^[13], this should not regard limitation of the present invention as.

Fig. 7 has provided the section of structure of two embodiment of 1TkR storage unit, and a plurality of memory resistor of setting forth in the storage unit by this figure can be positioned on the different interconnection line metal flats.4 memory resistor 201 in 1 storage unit shown in Fig. 7 (a), 202,203,204 share the situation of same gating device 100 (being MOSFET among the figure), memory resistor is positioned at the top of through hole and directly is connected with the upper strata metal wire, be respectively in the both sides of through hole, the layer at memory resistor place layer and connected metal wire place is defined as a composite bed, memory resistor in the same storage unit can be positioned on the different composite beds, 4 resistance are positioned on two composite beds among the figure, for example the connected upper strata of the layer metal lead wire layer at memory resistor 201 and 202 places constitutes second composite bed, and memory resistor 203, connected upper strata, the plane at 204 places metal lead wire layer constitutes first composite bed.Composite bed is stacked in vertical direction, constitutes three-dimensional structure.The different composite interlayer connects by the metal closures in the through hole.Fig. 7 (b) shows the situation of 8 memory resistor 201 to 208 shared same gating devices 100 in 1 storage unit, memory resistor is positioned at the bottom of through hole and directly is connected with the lower metal line, list in the one-sided of through hole, the layer at memory resistor place layer and metal wire direct-connected with it place is defined as a composite bed.Memory resistor 205,206,207,208 place layers and connected lower metal trace layer constitute first composite bed, memory resistor 201,202,203,204 place layers and connected lower metal trace layer constitute second composite bed, per 41 group of 8 resistance, be respectively on two composite beds, constitute three-dimensional structure, one end of 8 memory resistor all is connected (gating device adopts MOSFET in the present embodiment) by through hole with gating device 300 with metal wire, 8 then different with 8 respectively bit line BL0 to BL7 of the memory resistor other end connect.Should be noted that memory resistor number and should not regard limitation of the present invention as with respect to the variation of the geometry arrangement position of through hole.Adopt three-dimensional structure of the present invention can improve the density of storer.

Fig. 8 has provided the circuit diagram that adopts 1TkR structure storage unit to form the part of electric resistance transition memory array among embodiment of storer of the present invention.K=4 among the embodiment.The electric resistance transition memory array comprises the bit line that word line that the n bar is parallel to each other and m bar are parallel to each other, and word line is vertical mutually with bit line.The bit line that the m bar is parallel to each other is divided into the global bit line GBL0 that the m bar is parallel to each other, GBL1, GBL2 ... the local bitline LBL0 that GBLm and m bar are parallel to each other, LBL1, LBL2 ... LBLm, global bit line and local bitline are connected to the two ends of gate tube respectively, and the control end of gate tube is connected to the local bitline code translator, middle as shown global bit line GBL0 and local bitline LBL0 are connected to the two ends of gate tube 802, and the control end of gate tube 802 is connected to local bitline code translator 801.Storage unit is positioned at the zone of intersection of a word line and 4 local bitline, and middle as shown storage unit 600 is positioned at word line WL0 and local bitline LBL0, LBL1, LBL2, the zone of intersection that LBL3 forms.The set of sharing the storage unit of local bitline in the electric resistance transition memory array is defined as memory cell block, same listing shared local bitline LBL0 as shown, LBL1, LBL2, the storage unit of LBL3 has 600,610,620,630, they constitute a memory cell block, have just comprised m/4 memory cell block like this in the electric resistance transition memory array.The following describes the concrete connected mode of storage unit, storage unit shown in the figure 600, different memory resistor in the storage unit connect with different local bitline, and wherein an end of memory resistor 201 to 204 all is connected with gating device 100, and are connected with word line WL0 by gating device 100.The other end of memory resistor 201 to 204 then is connected with gate tube 802 to 805 respectively, and the control end of gate tube 802 to 805 is connected with local bitline code translator 801.Memory resistor 201 to 204 connects with different global bit line GBL0 to GBL3 respectively by gate tube 802 to 805 like this.Each word line-corresponding memory resistor of local bitline intersection.So that being operating as example, memory resistor 201 describes, gating device 100 drives conducting under the control of 501 output signals at row decoding, local bitline code translator 801 is deciphered, and 801 output is opened gating device 802, gating device 803,804,805 all turn-offs, column decoder 601 makes gating device 802,803,804,805 with sense amplifier/driver 702 between be communicated with, thereby the path of operating current is: gating device 802, target memory resistor 201, gating device 100.Operate with regard to the resistance 201 of selected word line WL0 and local bitline LBL0 point of crossing correspondence like this.The memory resistor that is positioned on the same bit line can be shared gate tube, and for example, the memory resistor on bit line LBL0 can be shared gate tube 802.

Fig. 9 has provided the flow process of above-mentioned storer being carried out write operation.(when dispatching from the factory) all is written as high resistant with all memory resistor when initial.Be that unit is operated with the memory cell block during write operation, carry out write operation with the memory cell block that storage unit such as storage unit among Fig. 8 600,610,620,630 are constituted below and be illustrated.There is n capable in the example, k=4.When the one or more memory resistor in the memory cell block need be write as high resistant, earlier choose gating devices all in the row of being chosen simultaneously with behavior unit, it is conduction device 100,802,803,804,805, make the selected line 113_1 of institute go up all memory resistor two ends and all add from low-resistance and become the required electric signal of high resistant, row 113_1 is gone up all memory resistor all be erased to high resistant, use the same method then going a 113_2,113_3......, the last all memory resistor of 113_n all are erased to high resistant, so just all memory resistor in the memory cell block all are written as high resistant, more than this process we be called the overall situation and wipe.Choose the gating device at the memory resistor place that need be rewritten as low-resistance then successively, the two ends of these memory resistor are added from high resistant become the required electric signal of low-resistance, these memory resistor are written as low-resistance singly.We are called the condition programming this process.When in the memory cell block do not have memory resistor to be write as high resistant the time, when promptly having only memory resistor to be rewritten as low-resistance, then skip the overall situation and wipe, directly entry condition programming.Choose the memory resistor that need be rewritten as low-resistance one by one, be rewritten into low-resistance one by one.

Figure 10 provides the logic function block diagram of an embodiment of write operation method.The resistance states that it is characterized in that operated memory resistor can be coupled on the logic control element 003, thereby whether the control programming operation stops.The input signal erase signal of programming Control module 002 and programme signal indicate current write operation to be in overall erase status or condition programming state, and these two signals are provided by outside sequential circuit, do not provide here.The principle of work that overall erase status during below respectively with regard to write operation and condition programming state are sketched embodiment respectively:

(1) overall erase status, it is high level that outside sequential control circuit makes the erase signal, and the programme signal is a low level, and device 1003 ends like this, device 1004 conductings, because under the overall erase status, data to be written are 0, so the A input port of logic control element 003 is a low level, when the data that data output buffers 004 outputs to the B input port of logic control element 003 when reading in advance or verifying are 0, logic control element 003 output low level is ended device 1002, stops to write.When the data that data output buffers 004 outputs to the B input port of logic control element 003 when reading in advance or verifying are 1, logic control element 003 output high level, make device 1002 conductings, allow to write, this moment, the signal of programming Control module 002 output made MUX 860,870 select to write 0 signal, and the signal of programming Control module 002 output is irrelevant with input data buffering 001.With memory resistor in the eraseable memory unit piece 600 201,202,203,204 is example, line decoder makes gate tube 100 conductings, and the local bitline code translator makes gate tube 802,803,804,805 all conductings are write 0 signal like this and are added to simultaneously on all memory resistor in the storage unit 600, realize wiping simultaneously a memory resistor in the storage unit, to the method for deleting of other storage unit in the memory cell block similarly, difference is that line decoder makes the gate tube conducting on the different rows.After all storage unit in the memory cell block were all finished erase operation, overall erase status finished.

(2) at the condition programming state, it is low level that outside sequential control circuit makes the erase signal, the programme signal is a high level, device 1003 conductings like this, device 1004 ends, and the level of the A input port of logic control element 003 is identical with input data buffering 001, data output buffers 004 outputs to the data of B input port of logic control element 003 when identical when reading in advance or verifying, logic control element 003 output low level is ended device 1002, stops to write.When reading in advance or verifying data output buffers 004 output to logic control element 003 the B input port data not simultaneously, logic control element 003 output high level, make device 1002 conductings, allow to write, if data are 1 o'clock in the input this moment data buffering, the signal of programming Control module 002 output makes MUX 860,870 select to write 1 signal.With memory resistor memory resistor in the memory cells piece 600 201 is example, line decoder makes gate tube 100 conductings, the local bitline code translator makes gate tube 802 conductings, gate tube 803,804,805 turn-off, and write 1 signal like this and are added on the memory resistor 201, realize the operation of program storage resistance one by one.

In fact write operation comprises two processes of pre-read and write, as shown in figure 10, at pre-read phase, applies read signal on operated memory resistor, and read signal is little electric signal, can not change the data mode of memory resistor.The output of sensor amplifier 005 is the current data mode of memory resistor, deposit in the data output buffer 004, output to a port of logic control 003, A input port data with logic control 003 compare then, if output identical then by logic control 003 make gating device 1002 by, thereby write operation stops, if it is different, then apply and write voltage on the operated memory resistor of needs, with respect to read-out voltage, writing voltage is big electric signal, can change the data mode of memory resistor.Apply and add for behind the write pulse memory resistor two ends to read voltage, sensor amplifier 005 is the data mode of output storage unit synchronously, when the data consistent of the A input port of the data mode of memory resistor and logic control 003, output by logic control 003 make gating device 1002 by, thereby write operation stops, otherwise continue to add write pulse, above process is write back checking (verifyafter write) exactly.This method can be avoided causing erasable number of times to descend to memory resistor excessive operation (over-programming).

An embodiment of the concrete grammar of the data mode of judgement memory resistor as shown in figure 11 in the write operation process, in actual applications, memory resistor is when low-resistance or high-impedance state, its resistance all can have certain distribution range, A ' A, B ' B represent the resistance distribution range of low-resistance and high resistant respectively among Figure 11, and A and B represent the maximal value and the minimum value of low-resistance and high resistant distribution range respectively.The resistance of Destination Storage Unit can need be written to when writing within the scope of high-impedance state or low resistance state distribution, avoid again the memory resistor excessive operation simultaneously.In an embodiment, when writing high-impedance state, when the value of target memory resistor greater than the B value, then think the write operation success, when writing low resistance state, when the value of target memory resistor less than the A value,, then think the write operation success.According to B and the A value set, can determine the reference voltage of sensor amplifier 005 among Figure 10.

Figure 12 has provided according to Figure 10 and Figure 11 and has adopted the opposed polarity electric signal to carry out a specific embodiment writing driving circuit of write operation, and this just in order to set forth the method for operating that the present invention proposes more fully, should not be considered to physical circuit and only limit to this embodiment.For setting forth its principle of work,, discuss in two kinds of situation: (1) overall erase status according to the write operation pattern that preamble is mentioned; (2) condition programming state.

At overall erase status, the erase signal is a high level, the programme signal is a low level, because the erase signal is received the reset terminal R end of d type flip flop 1201, the output DataQ of d type flip flop 1201 is a low level, and is irrelevant with DataIn, the P-Control signal is a high level like this, the n-Control signal is a low level, and this moment, transistor Mp0 turn-offed, the Mp3 conducting.Signal programme is a low level, and this moment, Mn5 ended the Mn2 conducting.Can see and form a reverse loop by this, path 2 as shown in figure 12.

At the condition programming state, the erase signal is a low level, and the programme signal is a high level, if DataIn is 1, the output DataQ of d type flip flop 1201 is a high level, and the P-Control signal is a low level, the n-Control signal is a high level, and this moment, transistor Mp3 turn-offed, the Mp0 conducting.Signal programme is a high level, and this moment, Mn2 ended the Mn5 conducting.Can see the loop that forms a forward by this, path 1 as shown in figure 12.If DataIn is 0, the output DataQ of d type flip flop 1201 is a low level, though the P-Control signal is a high level, the n-Control signal is a low level, make transistor Mp0 turn-off, the Mp3 conducting, but, so just can not form the reverse loop shown in path 2 because the programme signal is that high level ends Mn2.

When write operation begins, at first apply read signal, this moment, EQ was effective, read the current data state of target memory resistor, if the residing initial logic state of target memory resistor is lucky and the data consistent of the output DataQ of d type flip flop 1201, then can produce the WFinish signal, this signal is with d type flip flop 1202 asynchronous resettings, even EN becomes low level, write operation stops.

If the data of the output DataQ of state of memory cells and d type flip flop 1201 are different, then apply a write signal pulse and carry out write operation, apply read signal afterwards, if the data consistent of the output DataQ of residing initial logic state of target memory resistor and d type flip flop 1201 then makes W _FinishSignal effectively stops write operation, if the data of the output DataQ of residing initial logic state of target memory resistor and d type flip flop 1201 are inconsistent, then continues to apply write pulse.

How following surface analysis WFinish signal produces.The WFinish signal is that high level is effective in the present embodiment.Carrying out when the memory resistor state reads, if data to be written are 1, the reference resistance of then choosing low-resistance is as benchmark, according to analyzing as can be known, if the resistance of target memory resistor is less than this reference resistance, then sensor amplifier is output as logical one, otherwise is logical zero.If therefore the state of target memory resistor has been the state of data to be written, then both phase XORs are output as 0, and at this moment WFinish will become high level, and the sign write operation is finished.In like manner can analyze data to be written is 0 o'clock, and the reference resistance of selecting high resistant is as benchmark, if the resistance of target memory resistor greater than this reference resistance, then sensor amplifier is output as 0, otherwise is 1.If therefore the state of target memory resistor has been the state of data to be written, then both phase XORs are output as 0, produce the effective WFinish signal of high level.

Figure 13 provides an embodiment of the accumulator system addressing of adopting the 1TkR storage unit.Here the layer with memory resistor place layer and metal interconnecting wires direct-connected with it place is defined as a composite bed, and the notion in figure middle level is meant a composite bed.As shown in the figure, the effect of three address signals is respectively: signal 1300 is layer address, and signal 1301 is a column address, and signal 1302 is a row address.These three signals are connected respectively to local bitline code translator 801, on column decoder 601 and the line decoder 501.Address signal is coupled on each memory resistor by these three code translators.Carry out addressing by layer address 1300 and local bitline code translator 801, conducting global bit line and corresponding local bitline, the definite layer that will operate, for example, signal wire 1310,1320,1330 is effective, choose layer 1, layer 2, layer 3 to operate respectively, further choose the bit line that is coupled with column address and row address and the corresponding memory resistor in place, point of crossing of local word line to operate.Should be noted that in the present embodiment, the selected different resistance of operation simultaneously can be to be positioned at on one deck, also can be positioned on the different layers.

Figure 14 be among Fig. 8 one by storage unit 600,610, the special case of 620,630 one the 4 line storage unit pieces of forming.When needs operation store resistance 201, desirable current path is: electric current passes through target memory resistor 201 to being flow to com line 301 by the gating device 100 of gating from gating device 802.But as Figure 13, also have other current path, pass through memory resistor 209 from gating device 802 such as electric current, memory resistor 212, memory resistor 204 is to being flow to com line 301 by the gating device 100 of gating.Such current path also has a lot.

The equivalent circuit diagram of reality when Figure 15 (a) shows operation store resistance 201 in Figure 14 example.Electric current at first by gating device 802, a tunnel flow through need operated memory resistor 201, another road flow through earlier choose and be listed as the not memory resistor 205 of selected line, 209,213, be divided into three the tunnel then and flow through the memory resistor 206 that selected line is not chosen row, 207,208; Memory resistor 210,211,212; Memory resistor 214,215,216, and then flow through the memory resistor 202,203,204 that selected line is not chosen row, together flow through gate tube to com line 301 with the electric current that flows through the operated memory resistor 201 of needs at last.Electric current shown in the arrow is that we wish the electric current that flows through at memory cell block among Figure 15 (a), and other electric current that flows through except that memory resistor 201 then is leakage current (sneaking current).At overall erase status, apply identical erasing voltage among Figure 14 on the GBL0 to GBL3, gate tube 802 to 805 all conductings, the problem that does not have leakage current at the condition programming state, has only on the bit lines to apply voltage, can form foregoing leakage current, the operator scheme that we adopt the first overall situation to wipe condition programming when write operation again is exactly in order to make not operated resistance be in high-impedance state at the condition programming state as far as possible, thereby suppresses leakage current, reaches the purpose that reduces the write operation power consumption.

The leakage current that flows through memory resistor 202 to 216 in the equivalent circuit diagram that Figure 15 (a) illustrates can produce voltage drop on memory resistor 202 to 216.If when memory resistor 202 has voltage drop on some memory resistor near the voltage drop on the operated memory resistor 201, maloperation (write disturbe) just may take place in 216.Adopt the first overall situation to wipe the write operation pattern of postcondition programming among the present invention, owing to operate all memory resistor when the overall situation is wiped simultaneously with delegation, there is not leakage current, maloperation problem when therefore only needing the programming of consideration condition considers that promptly situation falls in other memory cell voltages that is in the same memory cell block when the voltage on the operated memory resistor 201 is reduced to program voltage.The present invention adopts the opposed polarity electric signal to carry out the driving circuit of writing of write operation, therefore when considering the maloperation problem, owing to only there is maloperation when the condition programming state applies voltage for the target memory resistor, only the memory resistor that needs consideration originally to be in high resistant is written as the situation of low-resistance by mistake.The operator scheme that the above first overall situation is wiped the postcondition programming and adopted the opposed polarity electric signal to carry out write operation has been relaxed the requirement to a memory cell block array size.

In order to be without loss of generality, consider that line number is Y in a 1TkR memory cell block, k=X, the resistance value when memory resistor is in high-impedance state is R, the resistance value when memory resistor is in low resistance state is r.Definition institute chooses and is listed as not that the memory resistor of selected line is the first order of equivalent resistance network shown in Figure 15 (a), do not choose the memory resistor that is listed as selected line not the second level for equivalent resistance network shown in Figure 15 (a), do not choose the third level of the memory resistor of row institute selected line for equivalent resistance network shown in Figure 15 (a), the second level resistance of equivalent resistance network is maximum, the voltage of assigning to is less, therefore only considers the voltage drop that the memory resistor on the first order and the third level is assigned to.Obtain the maximum voltage drop of memory resistor on the first order easily according to Ohm law $V1=\frac{1}{\frac{(Y-2)+(\mathrm{XY}-Y+2)*\frac{R}{r}}{X*(X-1)*\frac{R}{r}*\frac{R}{r}}+1}\mathrm{Vp},$ The maximum voltage drop of memory resistor on the third level $V3=\frac{1}{\frac{(X-2)+(\mathrm{XY}-X+2)*\frac{R}{r}}{Y*(Y-1)*\frac{R}{r}*\frac{R}{r}}+1}\mathrm{Vp},$ Vp is a program voltage in the formula.For the memory resistor that guarantees the first order and the third level not by maloperation, must satisfy V1＜V _DisturbeAnd V3＜V _Disturbe, V in the formula _DisturbeBe the voltage that minimum may make memory resistor be programmed.So the line number of a 1TkR, k, R/r (on off ratio) must be in certain limit.

Figure 15 (b) has provided line number Y in the memory cell block that is drawn by above-mentioned formula, k, R/r (on off ratio), V _DisturbeBetween relation curve 1501-1504, wherein horizontal ordinate is R/r (on off ratio), ordinate is V _DisturbeWith the ratio of program voltage Vp, these are determined by technological parameter.Point on the curve 1501-1504 can not cause maloperation takes place when writing.Can determine in desirable k of the next memory cell block of specific process conditions and the value of line number Y according to curve 1401-1404.For instance, work as V _Disturbe=0.75Vp, during R/r=2, k is desirable 8, and line number Y desirable 8.Above value just in order to set forth following the example of of a 1TkR array size among the present invention more fully, should not be considered to physical circuit and only limit to this example.

Figure 16 illustrates and adds the waveform synoptic diagram of writing voltage WriteNeg and WritePos among Figure 12.Pulse 1601 among the figure, 1603,1605,1607,1609th, read pulse, amplitude is less, can not change the state of memory resistor, its effect is whether the state of checking memory resistor before at every turn applying write pulse is identical with data to be written, if identical then can make the writefinish signal among Figure 12 effective, this illustrated hereinbefore.Pulse 1602 among the figure, 1604,1606,1608,1610th, write pulse, amplitude is bigger, can change the state of memory resistor, the amplitude of write pulse raises one by one, according to the device property of electric resistance transition memory, use such write pulse algorithm, can improve its erasable number of times (endurance) greatly.

Figure 17 has provided the sequential chart of write operation.This figure describes the embodiment that the first overall situation is wiped postcondition programming WriteMode.At first at overall erase status, erase is a high level, because it is connected to the reset terminal of d type flip flop 1201 among Figure 12, so the output terminal of d type flip flop 1201 always be low level, has nothing to do with the input end DataIn of d type flip flop 1201.The algorithm of the applying method of program voltage for mentioning among Figure 16, when the output that applies amplifier after the checking read pulse with after the output of d type flip flop 1201 is consistent, the Writefinish signal becomes high level, stops the write operation of overall erase status.Secondly at the condition programming state, programme is a high level, the output terminal of d type flip flop 1201 is consistent with the input end DataIn of d type flip flop 1201, after applying write pulse and checking read pulse equally, when the output of amplifier with after the output of d type flip flop 1201 is consistent, the Writefinish signal becomes high level, the write operation of end condition programming state.

Figure 18 has provided an embodiment of the design of sensor amplifier input stage.PMOS pipe 1801,1802, it is right that NMOS pipe 1804,1805 forms cross-couplings, this is the circuit of a positive feedback, after the current potential of node 1810,1811 has less difference, by the right positive feedback effect of cross-couplings, this difference is widened rapidly, so produce SO, the output of two complementations of SON.NMOS pipe 1806, the 1807th, a pair of differential pair tube, INN and INP are input, (when the difference mode signal input is arranged) can produce a difference by the electric current of NMOS pipe 1806 and 1807 when INN and INP are unequal, thereby the current potential imbalance that causes node 1810,1811, the final generation effectively exported.NMOS pipe 1808 provides the current source biasing of differential amplifier, its grid termination enable signal, and when enable signal was effective, amplifier was started working.

Figure 19 has provided and has clamped down on the model experiment curve of electric current to the influence of the electric signal that makes the memory resistor state and change.Curve 110 is not clamped down on I-V performance diagram under the situation for adding electric current, and the memory device initial state is a low resistance state, and when scanning voltage was 1V, memory device became high-impedance state by low resistance state.Curve 111 is with the situation of current clamp built in smaller value, can see that electric current is clamped down in about 1mA, and the state of storage unit does not overturn when voltage is 4V yet.Correlation curve 110, show electric current by embedding built in lower level, it is higher to make state of memory cells change required voltage.Can illustrate that by this phenomenon if it is bigger to flow through the electric current of memory device, then under the less situation of voltage, the upset of state just may take place memory device, this is disadvantageous for reading, and is easy to cause the mistake when reading to write.Should be noted that the data value among Figure 19 is corresponding to concrete device size and process conditions, but under different processes and condition, all has the rule identical with Figure 19.

According to the result of Figure 19, an embodiment of read operation method is provided among Figure 20 (a), the less electric current of clamping down on is set when read operation, in the process that can prevent to read, lower reading under the voltage, maloperation takes place.Should be pointed out that the circuit that the physical circuit clamp down on electric current should not only limit to adopt among the embodiment is set.Among Figure 20 (a), logic state is distinguished in the voltage drop of flowing through reference memory part and the generation of target memory spare by the comparison same current.The grid termination of PMOS pipe 2000 is read enable signal EN, and when the EN signal was low level, sensor amplifier was started working.PMOS pipe 2001 and 2002 constitutes current mirror, the electric current I D1 and the ID2 that flow through memory resistor 201 and reference resistance 217 are equated, thereby produce different voltage drops, amplifier 005 can amplify this potential difference (PD), produces the output of expression logic states of memory unit.In the design of sensing circuit, transistor 2007 its grids connect a clamp voltage, can be used for limiting the maximum current by storage unit, cause the mistake upset of state when avoiding read operation.Should be noted that, as described in Figure 10, in write operation, also need to read in real time the state of storage unit, so write driving circuit and sensing circuit can be shared sensor amplifier.

The state that Figure 20 (b) has provided storage unit that sense amplifier is read exports the embodiment of storer output terminal to.Have the state of 2n storage unit to be read out in the process of memory read simultaneously, promptly have 2n sense amplifier to work simultaneously, the data that also just need the temporary sense amplifier of 2n output state to read are simultaneously waited for the output port that is exported to storer by serial.In the present embodiment, we are divided into two with 2n sense amplifier and 2n output state, and promptly piece 2030 and piece 2040 comprise n sense amplifier in each piece, n output state and n transfer tube, the grid of the transfer tube in same connects same control signal.Specific operation process is as follows: at first sequential control circuit makes the LC signal become high level, and the RC signal becomes low level, and the data of reading in the sense amplifier are by transfer tube 2051,2052 ..., 205n is transferred to output state 2011,2012 ... 201n.Output state 2011 like this, 2012 ... data in buffer can be by the output port that exports to of serial among the 201n, meanwhile sequential control circuit makes the RC signal become high level, the LC signal becomes low level, the data of reading in the sense amplifier are by transfer tube 2061,2062 ... 206n is transferred to output state 2021,2022 ... 202n, going out buffer 2021,2022 ... among the 202n data in buffer can by serial export output port to the time, sequential control circuit makes the LC signal become high level again, the RC signal becomes low level, piece 2030 is started working again, with this alternately back and forth, when the output state of a circuit during from data that sense amplifier obtains reading, another piece circuit exports the data of output state to the output terminal of storer.Owing to need certain hour t1 from sense amplifier to transmission data between the output state, this method of reading can avoid transferring data at sense amplifier that system is in waiting status among the t1 during this period of time of output state, but utilize the output terminal that during this period of time data of another piece circuit is exported to storer, can improve the speed of reading like this.Need to prove, in the present embodiment sense amplifier and output state are divided into 2, can be divided into polylith in the practical application yet, the piece number of division is not a limitation of the present invention.

Figure 21 (a) is with Cu _xThe O storage medium is an example, has provided an embodiment of the relative position of memory resistor and through hole and interconnection line.Copper lead-in wire 2103-top is the copper embolism that is arranged in through hole 2107, and the copper embolism plays the effect that connects upper copper lead-in wire 2103+ and the copper lead-in wire 2103-of lower floor, Cu _xO storage medium 201 is positioned at the below of the top of through hole 2107 and upper copper lead-in wire 2103+, is connected with copper lead-in wire 2103+ as top electrode by barrier metal 2109, is connected by metal closures and copper as the bottom electrode 2103-that goes between.Around lower floor copper lead-in wire 2103-, through hole 2107, the upper copper lead-in wire 2103+ is respectively insulating medium layer 2101a, 2101b and 2101c, between 2101a and the 2101b, be respectively to be used to suppress block layer medium (cap layer) 2105a and the 2105b that electromigration improves reliability between 2101b and the 2101c.There is shown the situation that ground floor copper lead-in wire 2103-is connected with substrate by following embolism 2108, situation as the stacked in vertical direction formation three-dimensional structure of the described multiple layer metal line of this patent, the layer at memory resistor place layer and connected metal wire place is defined as a composite bed, connect by the copper metal closures between every adjacent two-layer composite bed, not shown.

Figure 21 (b) is with Cu _xThe O storage medium is an example, has provided another embodiment of the relative position of memory resistor and through hole and interconnection line.Copper lead-in wire 2103-top is the copper embolism that is arranged in through hole 2107, and the copper embolism plays the effect that connects upper copper lead-in wire 2103+ and the copper lead-in wire 2103-of lower floor, Cu _xO storage medium 201 is positioned at the bottom of through hole 2107 and gos deep into lower floor copper lead-in wire 2103-, and an end is connected with upper copper lead-in wire 2103+ with copper embolism as top electrode by barrier metal 2109, and the other end and lower floor's copper as the bottom electrode 2103-that goes between is connected.Around lower floor copper lead-in wire 2103-, through hole 2107, the upper copper lead-in wire 2103+ is respectively insulating medium layer 2101a, 2101b and 2101c, between 2101a and the 2101b, be respectively to be used to suppress block layer medium (cap layer) 2105a and the 2105b that electromigration improves reliability between 2101b and the 2101c.Provided the situation that embolism 2108 was connected with substrate under ground floor copper lead-in wire 2103-passed through among the figure, situation as the stacked in vertical direction formation three-dimensional structure of the described multiple layer metal line of this patent, the layer at memory resistor place layer and connected metal wire place is defined as a composite bed, connect by the copper metal closures between every adjacent two-layer composite bed, not shown.

More than among two embodiment the common trait of the geometric position of memory resistor be that memory resistor one end is to be connected with metal lead wire material as an electrode by barrier metal, the other end then directly and the metal lead wire material as another electrode be connected.Under the big electric field or the big function of current, there are two kinds of effects to take place, the one, metallic ion can move to the electron motion direction under the electron impact effect, another kind is that metallic ion can move to the electric field force action direction under big electric field action, two kinds of effect coexistences can be preponderated but look concrete condition a kind of effect wherein.Electric signal polarity on the memory resistor has two kinds of connections, a kind of is to connect high level on memory resistor one end that is connected with the restraining barrier, another termination low level, another kind are to connect low level conversely on memory resistor one end that is connected with the restraining barrier, another termination high level.Under preceding a kind of connection, metallic ion migration in storage medium under electric field action is subjected to the restraining barrier and stops, under a kind of connection in back, metallic ion migration in storage medium under the electron impact effect is subjected to the restraining barrier and stops.In the embodiment of the invention, adopt the electric signal of opposite polarity to carry out storage operation, make resistance become the situation of low-resistance, always on memory resistor one end that links to each other with the restraining barrier, connect high level, another termination low level by high resistant; Make resistance become the situation of high resistant by low-resistance, the polarity of electric signal is always connecing low level, another termination high level connecting conversely on an end on restraining barrier.

Should be noted that, when adopting aluminum metal as interconnection line, memory resistor also is to be connected with metal lead wire material as an electrode by barrier metal, the polarity system of selection of the operation electric signal that the present invention proposes also is suitable for, and the change of interconnect material and interconnect material and the combination of which kind of memory resistor should not regarded limitation of the present invention as.

Should also be noted that the gating device among the 1TkR shown in Figure 21 is MOSFET, gating device also can be diode or bipolar transistor, and is not shown.Substrate shown in Figure 21 can be the monocrystalline silicon piece substrate, also can be SOI (silicon on insulator) substrate, can also be thin film semiconductor's substrate, for example amorphous silicon semiconductor film or polycrystalline silicon semiconductor film.

Methods of storage operating described above, the system of selection of write signal polarity when relating to the method for the method of write operation, the method that changes the memory cell data state, read operation and write operation can be selected wherein one or several combination.This should not be considered to limitation of the present invention.

With reference now to Fig. 8 discussion, in the storage unit of 1TkR structure, the restriction that the k value is suffered.In the same as shown in Figure 6 storage unit, the memory resistor bottom electrode of sharing same gating device is interconnective.As shown in Figure 7, composite bed can carry out stacked by metal plug in vertical direction, forms three-dimensional storage array.All-in resistance number in each storage unit can be determined by following formula:

k＝N _LL _total (1)

N wherein _LRepresent in the same storage unit, be positioned at the memory resistor number that is connected with same gating device on every layer of interconnect metallization lines layer, L _TotalThe expression interconnect metallization lines number of plies altogether.On single gating device area, every layer of storage unit number N that is arranged _L, be rule decision by layout design.Make the utilization factor of chip area reach the highest, should follow such principle: promptly meeting under the condition of design rule, on the area of single gating device, arranging storage unit as much as possible.

Can determine two factors that have of k value according to formula (1): the firstth, share the number of the memory resistor of same gating device on every layer of interconnect metallization lines layer; The secondth, the number of plies of metal.Consider the decoded mode of local bitline, the number of sharing the memory resistor of same gating device should meet 2 ⁿ(n is a natural number, equals 1,2,3 ... .), like this can fullest utilize address wire.The occurrence of n is by the number decision that is positioned at the memory resistor on every layer of metal in number of metal and the storage unit, for example, and in each storage unit, the memory resistor that is positioned on every layer of metal has 2, have 8 layers of metal, 16 memory resistor, n=4 are arranged in each storage unit so.Again such as, in each storage unit, the memory resistor that is positioned on every layer of metal has 4, has 8 layers of metal, and 32 memory resistor, n=5 are arranged in each storage unit so.

With reference to Figure 22, an embodiment of system provided by the invention, system 2200 can comprise a controller 2201, input and output (I/O) device 2204, storer 2203, bus 2205.

With reference to Figure 23, another embodiment of system provided by the invention, system 2200 can comprise a controller 2201, input and output (I/O) device 2204, storer 2203, bus 2205 also comprise by bus 2205 wave point 2202 coupled to each other.Should be noted that the embodiment that scope of the present invention is not limited to have any of these parts or has all these parts.

Controller 2201 can comprise one or more microprocessors, digital signal processor, microcontroller etc.The information that storer 2203 storage availability are transferred to system 2200 or are transmitted by system 2200 also can be used for storage instruction.Storer 2203 can be made up of one or more dissimilar storeies, flash memory and/or comprise a kind of memory device illustrated for example as the present invention, its architectural feature is: adopt the above multi-element metal oxide of binary or binary as memory resistor; And several storage unit, all comprise two or more memory resistor in each storage unit, first electrode of each memory resistor all is connected with same gating device, and second electrode is coupled with different bit line, forms the structure that several memory resistor are shared same gating device.The SrZrO that mixes ₃ ^[2], ferroelectric material PbZrTiO ₃ ^[3], ferromagnetic material Pr _1-xCa _xMnO ₃ ^[4], the binary metal oxide material ^[5], organic material ^[6]Deng.Binary metal oxide is (as Cu _xO1＜x≤2 ^[7], WO _xThe oxide of the oxide of 2≤x≤3, titanyl compound, nickel, the oxide of zirconium, aluminium, the oxide of niobium, the oxide of tantalum etc.) A.Beck, J.G.Bednorz, Ch.Gerber, C.Rossel, and D.Widmer, " Reproducible switching effect in thin oxide filmsfor memory applications ", Appl.Phys.Lett.Vol.77, p.139,2000;

List of references

[1]J.Maimon，E.Spall，R.Quinn，S.Schnur，＂Chalcogenide-based?nonvolatile?memory?technology＂，IEEEProceedings?ofAerospace?Conference，p.2289，2001.

[2]C.Y.Liu，P.H.Wu，A.Wang，W.Y.Jang，J.C.Young，K.Y.Chiu，and?T.Y?Tseng，“Bistable?resistiveswitching?of?a?sputter-deposited?Cr-doped?SrZrO3?memory?film”，IEEE?EDL?vol.26，p.351，2005.

[3]J.R.Contreras，H.Kohlstedt，U.Pooppe，R.Waser，C.Buchal，and?N.A.Pertsev，“Resistive?switching?inmetal-ferroelectric-metal?junctions”，Appl.Phys.Lett.vol.83，p.4595，2003.

[4]A.Asamitsu，Y.Tomioka，H.Kuwahara，and?Y.Tokura，“Current?switching?of?resistive?states?inmagnetoresistive?manganites”，Nature(London)vol.388，p.50，1997.

[5]I.G.Baek，M.S.Lee，S.Seo，M.J.Lee，D.H.Seo，.S.Suh，J.C.Park，S.O.Park，H.S.Kim，I.K.Yoo，U-InChung，and?J.T.Moon，“Highly?scalable?non-volatile?resistive?memory?using?simple?binary?oxide?drivenby?asymmetric?unipolar?voltage?pulses”，IEDM?Tech.Dig.p.587(2004).

[6]L.P.Ma，J.Liu，andY.Yang，“Organic?electrical?bistable?devices?and?rewriteable?memory?cells”，Appl.Phys.Lett.vol.80，p.2997，2002；L.D.Bozano，B.W.Kean，V.R.Deline，J.R.Salem，and?J.C.Scott，“Mechanism?for?bistability?in?organic?memory?elements”，Appl.Phys.Lett.vol.84，p.607，2004.

[7]A.Chen，S.Haddad，Y.-C.Wu，”Non-Volatile?Resistive?Switching?for?Advanced?Memory?Applications”inNVSMW，2006

[8]I.G.Baek，D.C.Kim，M.J.Lee ^*，H.-J.Kim，E.K.“Multi-layer?Cross-point?Binary?Oxide?ResistiveMemory(OxRRAM)for?Post-NAND?Storage?Application”，Electron?Devices?Meeting，2005.IEDMTechnical?Digest.IEEE?International.p.750.

[9]K.Kinoshita，C.Yoshida，H.Aso，M.Aoki，and?Y.Sugiyama，Thermal?properties?of?NiOy?resistorpractically?free?from?the‘forming’process，Extended?Abstracts?of?the?2006?International?Conference?onSolid?State?Devices?and?Materials，Yokohama，2006，570-571

[10]Hyunjun?Sim，Hyejung?Choi，Dongsoo?Lee，Man?Chang，Dooho?Choi，Yunik?Son，Eun-Hong?Lee ^*，Wonjoo?Kim ^*，Yoondong?Park ^*，In-Kyeong?Yoo ^*?and?Hyunsang?Hwang，Excellent?Resistance?SwitchingCharacteristics?of?Pt/SrTiO3?Schottky?Junction?for?Multi-bit?Nonvolatile?Memory?Application，IEDM2005

[11]Dongsoo?Lee，Dongjun?Seong，Hye?Jung?Choi，Inhwa?Jo，R.Dong，W.Xiang，Seokjoon?Oh，Myeongbum?Pyun，Sun-ok?Seo，Seongho?Heo，etal.Excellent?uniformity?and?reproducible?resistanceswitching?characteristics?of?doped?binary?metal?oxides?for?non-volatile?resistance?memory?applications.IEDM?2006

[12]S.Seo，M.J.Lee，D.H.Seo，E.J.Jeoung，D.-S.Suh，Y.S.Joung，and?I.K.Yoo，Reproducible?resistanceswitching?in?polycrystalline?NiO?films，APPLIED?PHYSICS?LETTERS?VOLUME?85，NUMBER?23?6DECEMBER?2004

[13]Y.Watanabe，Phys.Rev.B?59，11257，1999.

Claims (10)

1, a kind of high density resistor transit storage adopts the above multi-element metal oxide of binary or binary as memory resistor, it is characterized in that comprising:

M bar word line, 2≤m≤2 ¹⁰,

The n bit lines, 2≤n≤2 ¹⁰, and

Several storage unit, each storage unit are positioned at each zone of intersection of a word line and several bit lines; All comprise two or more above-mentioned memory resistor and a gating device in each storage unit, first electrode of each memory resistor all is connected with above-mentioned same gating device, and is coupled by this gating device and word line; Second electrode of each memory resistor is coupled with different bit lines, forms the structure that several memory resistor are shared above-mentioned same gating device.

2, high density resistor transit storage according to claim 1, it is characterized in that the different memory resistor in the same storage unit are positioned on the multilayer interconnection metal line layer, the layer at each layer interconnect metallization lines layer and the storage medium place that is attached thereto constitutes a composite bed, the different composite layer carries out stacked in vertical direction, connect by the metal closures that is arranged in through hole between adjacent composite bed, form three-dimensional storage array.

3, high density resistor transit storage according to claim 1, it is that second electrode by memory resistor is connected with different gating devices that second electrode that it is characterized in that described each memory resistor and different bit lines are coupled, and further connects with different bit line by these gating devices that are attached thereto and to realize.

4, high density resistor transit storage according to claim 1 is characterized in that the above multi-element metal oxide of described binary or binary is Cu _xO 1＜x≤2, WO _xThe oxide of the oxide of the oxide of the oxide of 2≤x≤3, nickel, titanyl compound, zirconium, the oxide of aluminium, niobium, the oxide of tantalum, hafnium, the oxide of molybdenum, the oxide of zinc, SrZrO ₃, PbZrTiO ₃Or Pr _1-xCa _xMnO ₃

5, a kind of method of the described high density resistor transit storage of claim 1 being carried out storage operation: comprise write operation method and/or read operation method, it is characterized in that:

Described write operation method is: data before the write operation in the pre-read memory cell and the formulation in the Input Data Buffer are gone into data and are compared, if it is identical that data are gone in data in the storage unit and formulation, do not carry out write operation, if it is different that data are gone in data in the storage unit and formulation, then carry out write operation; And/or

Be positioned at the same storage unit that lists and form a memory cell block, when initial all storage unit all are written as high resistant, write operation is unit with the memory cell block, when one in the memory cell block or several memory resistor need be rewritten as high resistant, earlier all memory resistor in the piece all are written as high resistant, choose the memory resistor that does not need to be rewritten as high resistant more one by one, be rewritten into low-resistance one by one; When not having memory resistor to be rewritten as high resistant when having only one or several memory resistor to be rewritten as low-resistance in the memory cell block, choosing one by one needs the memory resistor of rewriting, and is rewritten into low-resistance one by one;

Described read operation method is that the data output state is divided into several parts, when the data in one of them part are sent to data output, and all the other each several part data output states data that then acquisition will be output from sense amplifier.

6, the method for storage operation according to claim 5 is characterized in that when carrying out write operation, adopts the voltage of opposite polarity to carry out by high resistant to low-resistance with by the operation of low-resistance to high resistant.

7, according to the method for claim 5 or 6 described storage operations, for the memory resistor two ends apply a plurality of pulses that write, the amplitude that writes pulse raises step by step when it is characterized in that write operation; Each, the memory resistor two ends verify by read operation whether the resistance value of memory resistor has reached formulation and gone into the desired distribution of resistance scope of data after writing pulse for applying, if reaching formulation goes into the desired resistance value of data then stops write operation, do not go into the desired resistance value of data if reach formulation, then continue as the memory resistor two ends apply amplitude higher write pulse.

8,, select the size of rational memory cell block to prevent that leakage current from not producing maloperation to choosing memory resistor when it is characterized in that carrying out write operation: according to the ratio of memory resistor high-impedance state resistance value R and low resistive state resistance value r according to the method for claim 5 or 6 described storage operations

And the ratio M that may make the voltage of not choosing memory resistor generation maloperation and write operation voltage, in a memory cell block, choose the value of the number k of the value of the line number Y that satisfies following condition and the memory resistor in each storage unit: $\frac{1}{\frac{(Y-2)+(\mathrm{kY}-Y+2)\&times;\frac{R}{r}}{k\&times;(k-1)\&times;\frac{R}{r}\&times;\frac{R}{r}}+1}<M$ And $\frac{1}{\frac{(k-2)+(\mathrm{kY}-k+2)\&times;\frac{R}{r}}{Y\&times;(Y-1)\&times;\frac{R}{r}\&times;\frac{R}{r}}+1}<M.$

9, the method for storage operation according to claim 5 is characterized in that the method for described read operation is: the maximal value of passing through the electric current arrival of storage unit during the restriction read operation.

10, the application of a kind of electric resistance transition memory as claimed in claim 1 in system, this system comprises: a processor, and with the input and output of described processor communication, and the storer that is coupled to this processor; Described storer is the described electric resistance transition memory of claim 1.

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