CN101359503A - Resistance conversing memory and storage operation method thereof - Google Patents
Resistance conversing memory and storage operation method thereof Download PDFInfo
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- CN101359503A CN101359503A CNA2008100409342A CN200810040934A CN101359503A CN 101359503 A CN101359503 A CN 101359503A CN A2008100409342 A CNA2008100409342 A CN A2008100409342A CN 200810040934 A CN200810040934 A CN 200810040934A CN 101359503 A CN101359503 A CN 101359503A
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Abstract
The invention belongs to integrated circuit technical field and in particular relates to a resistance conversion memory and a storage operation method for the memory. The invention takes phase change material (such as Ge2Sb2Te5) or multi-metal Oxides(two or more metals, such as CuxO, x is more than 1 and less than or equal to 2; WOx, x is more than or equal to 2 and less than or equal to 3; titanic oxide, falcial oxide, zirconic oxide, aluminous oxide, niobic oxide, tantalous oxide, etc.) as storing resistors. Each storing unit comprises two storing resistors, the first electrodes of the storing resistors are connected with the same gate apparatus, and the second electrodes are coupled with different bit lines, forming a structure in which a plurality of storing resistors of one storing unit share one gate apparatus. Such memory is not only largely improved in storage integration density and can provide stronger write operation signals.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of electric resistance transition memory and reach the method for sort memory being carried out storage operation.More particularly, the present invention relates to phase-change material (as Ge
2Sb
2Te
5) or the multi-element metal oxide of binary above (comprising binary) (as Cu
xO1＜x≤2, WO
xThe oxide of the oxide of 2≤x≤3, titanyl compound, nickel, the oxide of zirconium, aluminium, the oxide of niobium, the oxide of tantalum etc.) as there being two memory resistor to share the electric resistance transition memory and the methods of storage operating thereof of same gating device in storage medium and the storage unit.
Background technology
Storer occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the share more than 90% is occupied by FLASH.But because the requirement of stored charge, FLASH can not expand with the technology generation development is unrestricted, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.Recently electric resistance transition memory (resistive switching memory) is because its high density, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to, and employed material has phase-change material
[1], the SrZrO that mixes
3 [2], ferroelectric material PbZrTiO
3 [3], ferromagnetic material Pr
1-xCa
xMnO
3 [4], the binary metal oxide material
[5], organic material
[6]Deng.Binary metal oxide is (as Nb
2O
5, Al
2O
3, Ta
2O
5, Ti
xO, Ni
xO
[5], Cu
xO
[7]Deng) because accurately control at component, and ic process compatibility and cost aspect potential advantages especially paid close attention to.
Fig. 1 (a) (b) shows the circuit structure diagram and the physical arrangement diagrammatic cross-section of traditional 1T1R storage unit respectively.A memory resistor 104 and a gating device 100 are arranged in each storage unit 110, and memory resistor 104 directly is connected with an end 102 of gating device 100, and TE and BE represent the top electrode and the bottom electrode of resistance 104 respectively among the figure b.Gating device 100 adopts MOSFET (MOS (metal-oxide-semiconductor) memory) device in the diagram, and the other end of memory resistor 104 links to each other with bit line (being abbreviated as BL) 102.Bit line 102 just chooses the single resistance 104 of infall to carry out storage operation with word line 101 actings in conjunction.Gating device 100 make electric signal only to be coupling in word line-bit line intersect between single resistance operate, do not crosstalk and can not produce to other storage unit.The characteristics of this structure are between the different storage unit, and the phase mutual interference in storage operation is little, but gating device must be produced on the silicon chip substrate, takies silicon area.And 1 gating device can only be controlled a memory resistor.
Yet along with the raising of memory density, the gating device of each storage unit causes the failure to the memory resistor write operation because the restriction of size can't provide enough strong write signal (write operation voltage or write-operation current).At this problem, the present invention proposes corresponding solution.
Summary of the invention
The invention provides a kind of electric resistance transition memory spare and reach corresponding methods of storage operating, can solve gating device can't provide enough strong write operation signal under the situation that memory density improves problem.
The electric resistance transition memory spare that the present invention proposes, with phase-change material (as Ge
2Sb
2Te
5) or the multi-element metal oxide of binary above (comprising binary) as memory resistor, comprise several word lines, several bit lines, and several storage unit, all comprise two memory resistor in each storage unit, first electrode of these memory resistor all is connected with same gating device, this gating device can be bipolar transistor (bipolar transistor) or mos field effect transistor (MOSFET) or diode, and is coupled by this gating device and the lead that is called word line; Second electrode of these memory resistor is coupled with the different leads that is called bit line, is formed on the structure of two shared same gating devices of memory resistor in the same storage unit.
In the said structure, different memory resistor in the same storage unit can be positioned on the multilayer interconnection metal line layer, the layer at each layer interconnect metallization lines layer and the storage medium place that is attached thereto constitutes a composite bed, the different composite layer carries out stacked in vertical direction, connect by the metal closures that is arranged in through hole between adjacent composite bed, form three-dimensional storage array.
In the structure of the present invention, in the same storage unit, the different memory resistor that first electrode links to each other with same gating device, different gating devices in its second electrode and the MUX connect, these gating devices can be bipolar transistor (bipolartransistor) or mos field effect transistor (MOSFET), and further connect, thereby realize memory resistor second electrode and being coupled of corresponding lines not with different bit line by these gating devices that are attached thereto.
Phase-change material of the present invention can be Ge
2Sb
2Te
5Deng.
The above multi-element metal oxide of binary of the present invention or binary can be Cu
xO1＜x≤2, WO
xThe oxide of the oxide of the oxide of the oxide of 2≤x≤3, nickel, titanyl compound, zirconium, the oxide of aluminium, niobium, the oxide of tantalum, hafnium, the oxide of molybdenum, the oxide of zinc, SrZrO
3, PbZrTiO
3, Pr
1-xCa
xMnO
3It is pointed out that for above storage medium material because preparation technology and performance requirement can change to some extent, this should not regard limitation of the present invention as on stoichiometric proportion.Should also be noted that with the oxide material to be Main Ingredients and Appearance, carry out the small amount of impurities element doping therein improving performance,, should not regard limitation of the present invention as in the oxide of the oxide of the oxide of molybdenum or aluminium or zirconium, mixing trace copper.
The present invention proposes above storer is carried out the method for write operation.Data before write operation in the earlier pre-read memory cell are gone into data with the content and the formulation of being read and are compared, and it is identical to go into data as if the data of storage unit and formulation, does not carry out write operation, otherwise does not carry out write operation.
The concrete grammar that changes the data in the said memory cells is: low resistance state and high-impedance state all have distribution range.When will making resistance become high resistant by low-resistance, when the value of target memory resistor minimum value greater than the high resistant distribution range, think that then write operation is successful, when will making resistance become low-resistance by high resistant, when the value of target memory resistor maximal value, then think the write operation success less than the low-resistance distribution range.
In above-mentioned storer, memory resistor is a two terminal device, when carrying out write operation, adopts suitable electric signal to carry out by high resistant to low-resistance operation (reset operation) with by the operation (set operation) of low-resistance to high resistant.
The method that the present invention's proposition is carried out read operation to above storer.When carrying out read operation, on selected neutrality line, add suitable read current, can on selected bit line, produce corresponding read-out voltage like this, the content of relatively amplifying the acquisition storage unit of this read-out voltage and reference voltage process sense amplifier.
The present invention also provides a kind of system that comprises electric resistance transition memory of the present invention, and it comprises a processor, and with the input and output of described processor communication, and the memory device that is coupled to this processor; Said memory device is an electric resistance transition memory spare provided by the invention.Comprise: several storage unit, all comprise two or more memory resistor in each storage unit, first electrode of these memory resistor all is connected with same gating device, these gating devices can be bipolar transistor (bipolar transistor) or mos field effect transistor (MOSFET) or diode, and be coupled by this gating device and the lead that is called word line, second electrode of memory resistor is coupled with the different leads that is called bit line, form several memory resistor and share the structure of same gating device, or the like.
Description of drawings
Fig. 1 is based on traditional 1T1R storage unit, its equivalent circuit diagram (a) and section of structure (b) for the electric resistance transition memory of reporting at present.
Fig. 2 is an embodiment diagram of electric resistance transition memory storage unit of the present invention.
Fig. 3 is the structural profile of 1T2R storage unit embodiment.
Fig. 4 is the partial circuit figure of the storage array of 1T2R storage unit formation.
Fig. 5 is the part diagram of system according to an embodiment of the invention.
Fig. 6 is the part diagram of system according to still another embodiment of the invention.
Number in the figure
The traditional 1T1R storage unit of 110 representatives, 101 represent the control end of gating device, 102 represent the top crown of memory resistor, and 104 represent memory resistor, and 102 represent the bottom crown of memory resistor, 100 represent gating device, 200 representatives 1T2R storage unit proposed by the invention, 201,202 represent memory resistor respectively, and 203 represent the control end of gating device, 801 represent the local bitline code translator, 802 represent gate tube, and on behalf of row decoding, 501 drive, and 702 represent sense amplifier/driver, 500 representative systems, 501 represent controller, and 502 represent wave point, and 504 represent input and output (I/O) device, 503 represent storer, and 505 represent bus.
Embodiment
Describe the present invention in the reference example more completely in conjunction with being shown in hereinafter, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.On the contrary, provide these embodiment, scope of the present invention is passed to those skilled in the relevant art fully so that this openly is completely and completely.
At this reference diagram is the synoptic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure.
Should be appreciated that when claiming an element when " on another element " or " on another element, extending ", this element can be directly at " on another element " or directly " on another element, extending ", or also may have insertion element.On the contrary, when claiming an element, there is not insertion element directly at " on another element " or directly when " on another element, extending ".When claiming an element with " another element is connected " or " coupling " with another element, this element can directly connect or be couple to another element, or also can there be insertion element, on the contrary, when claiming an element, there is not insertion element directly with " another element is connected " or direct " coupling " with another element.
The multi-element metal oxide that the present invention relates to (to comprise binary) with phase-change material or more than the binary is shared the electric resistance transition memory and the methods of storage operating thereof of same gating devices as two memory resistor in storage medium and the storage unit.The notion of storage unit described here is meant gating device and the compound storage unit that memory resistor constituted that is attached thereto.For ease of setting forth, the agreement storage unit is meant this duplex.
1 embodiment of the electric resistance transition memory spare that the present invention proposes is described below with reference to Fig. 2.Fig. 2 shows the equivalent circuit diagram of storage unit 200, comprise 1 gating device 100 and two memory resistor, memory resistor is respectively 201,202, gating device 100 adopts mos field effect transistor (MOSFET) in diagram, this gating device also can be bipolar transistor (bipolar transistor) or diode, first electrode of two memory resistor all directly links to each other with the same end S of gating device 100, and second electrode then is coupled with different bit line BL-0, BL-1 respectively.Gating device and word line WL_0 are coupled, and are that the control end 203 by MOSFET links to each other with word line in the present embodiment.Each intersection of word line-bit line is associated with an independent storage unit.Formed two memory resistor like this and shared the structure of same gating devices, corresponding to traditional 1T1R structure, below we to be called for short this structure be the 1T2R structure.Notice that T represents gating device, rather than specially refers to transistor here.The variation of the kind of gating device should not regarded limitation of the present invention as.Adopt this structure, can under same piece of silicon area situation, increase the size of gating device, improve the driving force of gating gating device.
Fig. 3 has provided the section of structure of the embodiment of 1T2R storage unit, and two memory resistor setting forth in the storage unit by this figure are positioned on the different metal interconnecting wires planes.Two memory resistor 201 in 1 storage unit shown in Fig. 3,202 share the situation of same gating device 100 (being MOSFET among the figure), memory resistor is positioned at the top of through hole and directly is connected with the upper strata metal wire, the layer at memory resistor place layer and connected metal wire place is defined as a composite bed, memory resistor in the same storage unit can be positioned on the different composite beds, two resistance are positioned on two composite beds among Fig. 3, the connected upper strata of the layer metal lead wire layer at memory resistor 201 places constitutes second composite bed, and connected upper strata, the plane metal lead wire layer at memory resistor 202 places constitutes first composite bed.Composite bed is stacked in vertical direction, constitutes three-dimensional structure.The different composite interlayer connects by the metal closures in the through hole.
Fig. 4 has provided the circuit diagram that adopts 1T2R structure storage unit to form the part of electric resistance transition memory array among embodiment of storer of the present invention.The electric resistance transition memory array comprises the bit line that word line that the n bar is parallel to each other and m bar are parallel to each other, and word line is vertical mutually with bit line.The bit line that the m bar is parallel to each other comprises the global bit line GBL0 that the m bar is parallel to each other, GBL1, GBL2 ... the local bitline LBL0 that GBLm and m bar are parallel to each other, LBL1, LBL2 ... LBLm, global bit line and local bitline are connected to the two ends of gate tube respectively, and the control end of gate tube is connected to local bitline code translator 801, global bit line GBL0 and local bitline LBL0 are connected to the two ends of gate tube 802 as shown in the figure, and the control end of gate tube 802 is connected to local bitline code translator 801.Storage unit is positioned at the zone of intersection of a word line and two local bitline, and middle as shown storage unit 200 is positioned at word line WL0 and local bitline LBL0, the zone of intersection that LBL1 forms.Each word line-corresponding memory resistor of local bitline intersection.So that being operating as example, memory resistor 201 describes, gating device 100 drives conducting under the control of 501 output signals at row decoding, local bitline code translator 801 is deciphered, 801 output is opened gating device 802, thereby the path of operating current is: gating device 802, target memory resistor 201, gating device 100.Operate with regard to the resistance 201 of selected word line WL0 and local bitline LBL0 point of crossing correspondence like this.
Identical to the read-write operation of storage unit with the method for traditional electric resistance transition memory.With the example that is operating as to memory resistor 201, when carrying out write operation, choose the memory resistor 201 (the system of selection front is by the agency of) in the array earlier, on the global bit line of memory resistor 201 correspondences, apply the electric signal (writing voltage or write current) of write operation then by the sense amplifier/driver among Fig. 4 702, because in this invention, two memory resistor are shared a gating device, the size of this gating device just can be more greatly, the twice that is about gating device size in the classic method, the resistance that gating device shows will be a little bit smaller, the dividing potential drop of gating device can be corresponding a little bit smaller, the electric current of whole path also can be greatly corresponding, therefore finally by the memory resistor write current or drop on the voltage of writing at memory resistor two ends can be greatly corresponding, the write operation possibility of success is can corresponding increase a lot.When carrying out read operation, choose the memory resistor 201 in the array earlier, on the global bit line of memory resistor 201 correspondences, apply suitable read current by the sense amplifier/driver among Fig. 4 702 then, because Memister is different in the resistance value of different conditions, therefore corresponding global bit line will show different read-out voltage values, utilize sense amplifier/driver 702 that this read-out voltage and reference voltage (size is between two kinds of resistance states read-out voltages) are relatively amplified, obtain the content of selected memory resistor.
With reference to figure 5, an embodiment of system provided by the invention, system 500 can comprise a controller 501, input and output (I/O) device 504, storer 503, bus 505.
With reference to figure 6, another embodiment of system provided by the invention, system 500 can comprise a controller 501, input and output (I/O) device 504, storer 503, bus 505 also comprise by bus 505 wave point 502 coupled to each other.Should be noted that the embodiment that scope of the present invention is not limited to have any of these parts or has all these parts.
List of references
[1]J.Maimon，E.Spall，R.Quinn，S.Schnur，″Chalcogenide-based?nonvolatile?memory?technology″，IEEEProceedings?of?Aerospace?Conference，p.2289，2001.
[2]C.Y.Liu，P.H.Wu，A.Wang，W.Y.Jang，J.C.Young，K.Y.Chiu，and?T.Y?Tseng，“Bistable?resistiveswitching?of?a?sputter-deposited?Cr-doped?SrZrO3?memory?film”，IEEE?EDL?vol.26，p.351，2005.
[3]J.R.Contreras，H.Kohlstedt，U.Pooppe，R.Waser，C.Buchal，and?N.A.Pertsev，“Resistive?switching?inmetal-ferroelectric-metal?junctions”，Appl.Phys.Lett.vol.83，p.4595，2003.
[4]A.Asamitsu，Y.Tomioka，H.Kuwahara，and?Y.Tokura，“Current?switching?of?resistive?states?inmagnetoresistive?manganites”，Nature(London)vol.388，p.50，1997.
[5]I.G.Baek，M.S.Lee，S.Seo，M.J.Lee，D.H.Seo，.S.Suh，J.C.Park，S.O.Park，H.S.Kim，I.K.Yoo，U-InChung，and?J.T.Moon，“Highly?scalable?non-volatile?resistive?memory?using?simple?binary?oxide?drivenby?asymmetric?unipolar?voltage?pulses”，IEDM?Tech.Dig.p.587(2004).
[6]L.P.Ma，J.Liu，and?Y.Yang，“Organic?electrical?bistable?devices?and?rewriteable?memory?cells”，Appl.Phys.Lett.vol.80，p.2997，2002；L.D.Bozano，B.W.Kean，V.R.Deline，J.R.Salem，and?J.C.Scott，“Mechanism?for?bistability?in?organic?memory?elements”，Appl.Phys.Lett.vol.84，p.607，2004.
[7]A.Chen，S.Haddad，Y.-C.Wu，”Non-Volatile?Resistive?Switching?for?Advanced?Memory?Applications”inNVSMW，2006.
Claims (10)
1, a kind of electric resistance transition memory spare, the multi-element metal oxide that adopts phase-change material or binary above (comprising binary) is characterized in that comprising as memory resistor:
Several word lines,
Several bit lines, and
Several storage unit, each storage unit are positioned at each zone of intersection of a word line and two bit lines.All comprise two memory resistor and a gating device in each storage unit, first electrode of each memory resistor all is connected with above-mentioned same gating device, and is coupled by this gating device and word line; Second electrode of each memory resistor is coupled with different bit lines, forms the structure that two memory resistor are shared above-mentioned same gating device.
2, electric resistance transition memory spare according to claim 1, it is characterized in that: the different memory resistor in the same storage unit are positioned on the multilayer interconnection metal line layer, the layer at each layer interconnect metallization lines layer and the storage medium place that is attached thereto constitutes a composite bed, the different composite layer carries out stacked in vertical direction, connect by the metal closures that is arranged in through hole between adjacent composite bed, form three-dimensional storage array.
3, electric resistance transition memory spare according to claim 1, it is characterized in that: it is that second electrode by memory resistor is connected with different gating devices that second electrode of described each memory resistor and different bit lines are coupled, and further connects with different bit line by these gating devices that are attached thereto and to realize.
4,, it is characterized in that described gating device is bipolar transistor or mos field effect transistor or diode according to claim 1 electric resistance transition memory spare.
5,, it is characterized in that described gating device is bipolar transistor or mos field effect transistor according to claim 3 electric resistance transition memory spare.
6, electric resistance transition memory spare according to claim 1 is characterized in that: described phase-change material can be Ge
2Sb
2Te
5
7, electric resistance transition memory spare according to claim 1 is characterized in that: the above multi-element metal oxide of described binary or binary can be Cu
xO1＜x≤2, WO
xThe oxide of the oxide of the oxide of the oxide of 2≤x≤3, nickel, titanyl compound, zirconium, the oxide of aluminium, niobium, the oxide of tantalum, hafnium, the oxide of molybdenum, the oxide of zinc, SrZrO
3, PbZrTiO
3, Pr
1-xCa
xMnO
3
8, a kind of method of the described electric resistance transition memory spare of claim 1 being carried out write operation: data before the write operation in the pre-read memory cell and the formulation in the Input Data Buffer are gone into data and are compared, if it is identical that data are gone in data in the storage unit and formulation, do not carry out write operation, if it is different that data are gone in data in the storage unit and formulation, then carry out write operation.
9, a kind of method that the described electric resistance transition memory spare of claim 1 is carried out read operation: on the bit line of being chosen, add suitable electric current, the voltage of this bit line and reference voltage are relatively amplified output through sense amplifier.
10, the application of the described electric resistance transition memory of a kind of claim 1 in system, this system comprises: a processor, and with the input and output of described processor communication, and the memory device that is coupled to this processor; Described memory device is the described electric resistance transition memory spare of claim 1.
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|---|---|---|---|---|
| CN101593765B (en) * | 2009-06-26 | 2011-01-26 | 中国科学院上海微系统与信息技术研究所 | Chip integrating various resistance conversion memory modules and method for manufacturing same |
| CN110718569A (en) * | 2019-09-02 | 2020-01-21 | 北京大学 | 1T2R memory cell based on resistive random access memory and preparation method thereof |
| CN110739012A (en) * | 2019-09-12 | 2020-01-31 | 浙江省北大信息技术高等研究院 | Memory array block and semiconductor memory |
| CN114783486A (en) * | 2022-06-21 | 2022-07-22 | 北京大学 | Memory computing accelerator based on 1T2R resistive random access memory array and application thereof |
| TWI779657B (en) * | 2020-06-29 | 2022-10-01 | 台灣積體電路製造股份有限公司 | Memory device and methods of manufacture |
| WO2023221220A1 (en) * | 2022-05-18 | 2023-11-23 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11948616B2 (en) | 2021-11-12 | 2024-04-02 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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2008
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101593765B (en) * | 2009-06-26 | 2011-01-26 | 中国科学院上海微系统与信息技术研究所 | Chip integrating various resistance conversion memory modules and method for manufacturing same |
| CN110718569A (en) * | 2019-09-02 | 2020-01-21 | 北京大学 | 1T2R memory cell based on resistive random access memory and preparation method thereof |
| CN110739012A (en) * | 2019-09-12 | 2020-01-31 | 浙江省北大信息技术高等研究院 | Memory array block and semiconductor memory |
| TWI779657B (en) * | 2020-06-29 | 2022-10-01 | 台灣積體電路製造股份有限公司 | Memory device and methods of manufacture |
| US11729997B2 (en) | 2020-06-29 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3D stackable memory and methods of manufacture |
| US11948616B2 (en) | 2021-11-12 | 2024-04-02 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| WO2023221220A1 (en) * | 2022-05-18 | 2023-11-23 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN114783486A (en) * | 2022-06-21 | 2022-07-22 | 北京大学 | Memory computing accelerator based on 1T2R resistive random access memory array and application thereof |
| CN114783486B (en) * | 2022-06-21 | 2022-08-26 | 北京大学 | Memory computing accelerator based on 1T2R resistive random access memory array and application thereof |
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