CN101419953B - 用于一封装装置的接合结构 - Google Patents

用于一封装装置的接合结构 Download PDF

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CN101419953B
CN101419953B CN2007101670176A CN200710167017A CN101419953B CN 101419953 B CN101419953 B CN 101419953B CN 2007101670176 A CN2007101670176 A CN 2007101670176A CN 200710167017 A CN200710167017 A CN 200710167017A CN 101419953 B CN101419953 B CN 101419953B
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CN101419953A (zh
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林鸿村
陈煜仁
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Chipmos Technologies Inc
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
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Abstract

本发明是一种用于一半导体封装件的接合结构，藉由在一基板与一半导体芯片之间提供一凸起结构，使该基板与该半导体芯片可保持一间距。

Description

用于一封装装置的接合结构
技术领域
本发明涉及一种用于一封装装置的接合结构；特别涉及一种于基板与芯片间，提供均匀的实质间距的接合结构。
背景技术
先进半导体封装技术已越来越普遍，例如mini-BGA(ball-grid array)技术、FBGA(fine pitch BGA)技术等等。此类封装技术，将一半导体芯片藉由一接合层与一基板，或称导线架(leadframe)，进行粘合。随着封装的趋势逐渐朝向薄型封装发展，芯片的厚度也日趋薄型化。在薄型封装过程中，有时芯片在接合至基板时，过度挤压接合层，导致接合层的液态材料越过芯片侧壁，而粘附于一非预期的区域，例如不与接合层接触的芯片另一表面，此即所谓的爬胶现象。
由于不与接合层接触的芯片另一表面，可能具有一导线结构，以与基板或外部元件电性连结，因此当爬胶现象产生时，若接合层具有导电性，则可能会破坏上述电性连结架构，产生短路或者阻抗干扰等等不良效果。因此除非使用非导电胶作为接合层的材料，否则上述现象即成为封装工艺的严重缺失。以下进一步说明。
图1例示一已知封装装置1，其包含一基板11、一芯片12、一接合层13及一导线结构14，其中接合层13因为爬胶现象，而与导线结构14连结。因此当接合层13由导电胶所制成时，爬胶现象会破坏导线结构14的电性连结，产生短路或者阻抗干扰等等不良效果。
为改善上述不良效果，有些已知技术采用非导电胶作为接合层13的材料，然而非导电胶的散热能力逊于导电胶，因此容易导致封装装置于运作时过热的问题。
有鉴于此，在半导体结构中，提供一用于一封装装置的接合结构，以改善爬胶现象，同时又能具有良好散热能力，乃为此一业界亟待解决的问题。
发明内容
本发明的一目的在于提供一种用于一封装装置的接合结构，该封装装置包含一芯片及一基板，该接合结构包含一接合层及一凸起结构。藉由该凸起结构，使该芯片与该基板之间，定义出一实质间距。
为达上述目的，本发明揭露一种用于上述接合结构的凸起结构，藉由于该基板上形成具有一定高度的多个个凸块，使该芯片与该基板接合时，基本上接触到该多个个凸块的顶端，而与该基板保持一实质间距。
本发明的另一目的在于提供一种用于一封装装置的接合结构，该封装装置包含一芯片及一基板，该基板具有一穿孔区域，该接合结构不形成于该穿孔区域内，该接合结构包含一接合层及一凸起结构。藉由该凸起结构，使该芯片与该基板之间，定义出一实质间距。
为达上述目的，本发明揭露一种用于上述接合结构的凸起结构，藉由于该基板上，该穿孔区域以外，形成具有一定高度的多个个凸块，使该芯片与该基板接合时，基本上接触到该多个个凸块的顶端，而与该基板保持一实质间距。
为让本发明的上述目的、技术特征、和优点能更明显易懂，下文以较佳实施例配合附图进行详细说明。
附图说明
图1为现有技术的封装装置示意图；
图2为应用本发明的封装装置实施例示意图；
图3a为应用本发明的另一封装装置实施例示意图；
图3b为图3a所示的封装装置的基板的上视示意图；以及
图4为本发明的接合结构的凸起结构实施例示意图。
主要元件符号说明：
1：封装装置             11：基板
12：芯片                13：接合层
14：导线结构            2：封装装置
21：基板                22：芯片
23：接合结构            24：导线结构
211：第一区域           212：第二区域
231：凸起结构           232：接合层
231a、231b、231c：凸块  3：封装装置
31：基板                 32：芯片
33：接合结构             34：导线结构
311：第一区域            312：第二区域
313：穿孔区域            331：凸起结构
332：接合层              331a、331b、331c：凸块
41：基板                 411：第一区域
401、402、403：凹陷      431：凸起结构
431a、431b、431c：凸块
具体实施方式
以下将通过实施例来解释本发明内容，其关于具有较佳接合的接合结构。然而，本发明的实施例并非用以限制本发明需在如实施例所述的任何特定的环境、应用或特殊方式方能实施。因此，关于实施例的说明仅为阐释本发明的目的，而非用以限制本发明。需说明者，以下实施例及附图中，与本发明无关的元件已省略而未绘示，且附图中所绘示的元件间尺寸比例关系，为说明实施例的目的，并非实际制作元件时的限制。
图2绘示本发明的接合结构23用于一封装装置2的实施例，封装装置2包含一基板21及一芯片22。基板21具有一第一区域211及一第二区域212，芯片22通过接合结构23与基板21的第一区域211结合，而芯片22则通过一导电结构24与基板21的第二区域212电性连结。此封装装置2适合应用于使用mini BGA工艺的产品。
接合结构23包含一凸起结构231及一接合层232。在本实施例中，凸起结构231包含多个凸块，图中仅例示凸块231a、231b及231c，此等凸块皆形成于基板21的第一区域211上。凸起结构231形成于基板21上的接合层232中，使芯片22与基板21的第一区域211间，定义出一实质间距D1。接合层232则形成于芯片22与基板21的一第一区域211间，用以接合芯片22与基板21。藉由凸起结构231，芯片22与基板21接合时，将略微接触凸起结构231的上缘，以使芯片22保持与基板21的实质间距D1。为使实质间距D1适当地区隔芯片22与基板21，凸起结构具有基本上介于10微米(micrometer)至75微米的一平均高度。
接合层232并未形成于第二区域212之内，仅于对应芯片22封装的第一区域211之内形成。藉由形成凸起结构231，芯片22与基板21接合时，将可保持固定的间距，同时避免接合层232因芯片22与基板21的接合间距过小，而产生爬胶现象。
在本实施例中，凸起结构231由金属所制成，以提供芯片22与基板21间的间距D1同时改善接合结构23的散热能力。在其他实施例中，凸起结构231亦可由非金属所制成。接合层232的材料选自导电胶、非导电胶及其组合的材料群组中，以提供接合芯片22与基板21的能力。需特别说明的是，藉由形成凸起结构231改善爬胶现象，在使用薄型芯片的场合，亦可使用导电胶做为接合层232的材料。
图3a绘示本发明的另一实施例，为接合结构33用于一封装装置3的实施例，封装装置3包含一基板31及一芯片32，接合结构33包含一凸起结构331及一接合层332，凸起结构331包含多个凸块，图中仅例示凸块331a、331b及331c。与前一实施例不同处为，基板31除具有一第一区域311及一第二区域312外，更具有一穿孔区域313。请一并参考图3b，其绘示此封装装置3的基板31的上视图，其中图3a的基板31代表图3b中，基板31沿AA’剖面线的剖面，在本实施例中，穿孔区域313设置于第一区域311中。
芯片32通过接合结构33与基板31的第一区域311结合，而芯片32则通过一导电结构34，经由基板31的穿孔区域313，与基板31的第一区域311电性连结。此封装装置2适合应用于使用FBGA工艺的产品。
在本实施例中，与前实施例主要不同处在于导电结构24通过穿孔区域313与基板电性连结。藉由凸起结构331，以使芯片32保持与基板31的实质间距D2。为使实质间距D2适当地区隔芯片32与基板31，凸起结构具有基本上介于10微米(micrometer)至75微米的一平均高度。
在本实施例中，凸起结构331同样可由金属或非金属所制成。同时接合层332的材料选自导电胶、非导电胶及其组合的材料群组中，在使用薄型芯片的场合，亦可使用导电胶做为接合层332的材料。
图4例示凸起结构与基板的一变形例，其中基板41于设定与芯片接合的第一区域411中，设有至少一凹陷。在本实施例中，基板41于第一区域411中设有多个凹陷，图中例示凹陷401、402及403。凸起结构431包含多个凸块，图中例示凸块431a、431b及431c，分别形成于凹陷401、402及403内。上述各凸块具有一基本上介于10微米至75微米的一高度，意即各凸块突出基板表面的高度基本上介于前述范围内，以适当地区隔将与基板41接合的芯片与基板41。同样地，凸起结构431同样可由金属或非金属所制成。
需注意者，图4所绘示的变形例，可适用于前述所有的实施例中，以达成本发明提供均匀的基板与芯片接合区隔，俾改善爬胶现象。本发明的接合结构用以于基板与芯片间，提供均匀的接合间距或区隔，以避免导电结构的导电性减损或破坏。
上述的实施例仅用来例举本发明的实施态样，以及阐释本发明的技术特征，并非用来限制本发明的保护范畴。任何熟悉此技术者可轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利保护范围应以权利要求书为准。

Claims (12)

1.一种用于一封装装置的接合结构，该封装装置包含一芯片及一基板，该基板具有一第一区域及一第二区域，该芯片通过该接合结构与该基板的该第一区域结合，而该芯片则通过一导电结构与该基板的该第二区域电性连结；该接合结构包含：
一接合层，形成于该芯片及该基板的该第一区域间；以及
一凸起结构，形成于该基板上的接合层中，使该芯片与该基板的该第一区域间，定义出一实质间距。
2.如权利要求1所述的接合结构，其特征在于，该接合层的材料选自导电胶、非导电胶及其组合的材料群组中。
3.如权利要求1所述的接合结构，其特征在于，该凸起结构包含多个凸块，形成于该基板的该第一区域上。
4.如权利要求1所述的接合结构，其特征在于，该基板的该第一区域设有至少一凹陷，该凸起结构形成于该至少一凹陷内。
5.如权利要求3所述的接合结构，其特征在于，该基板的该第一区域设有多个凹陷，该多个凸块对应形成于至少部份该多个凹陷内。
6.如权利要求1所述的接合结构，其特征在于，该凸起结构由金属所制成，以改善该接合结构的散热能力。
7.一种用于一封装装置的接合结构，该封装装置包含一芯片及一基板，该基板具有一第一区域、一第二区域及一穿孔区域，该芯片通过该接合结构与该基板的该第一区域结合，而该芯片则通过一导电结构，经由该基板的该穿孔区域，与该基板的该第一区域电性连结；该接合结构包含：
一接合层，形成于该芯片及该基板的该第一区域间；以及
一凸起结构，形成于该基板上的接合层中，使该芯片与该基板的该第一区域间，定义出一实质间距。
8.如权利要求7所述的接合结构，其特征在于，该接合层的材料选自导电胶、非导电胶及其组合的材料群组中。
9.如权利要求7所述的接合结构，其特征在于，该凸起结构包含多个凸块，形成于该基板的该第一区域上。
10.如权利要求7所述的接合结构，其特征在于，该基板的该第一区域设有至少一凹陷，该凸起结构形成于该至少一凹陷内。
11.如权利要求7所述的接合结构，其特征在于，该基板的该穿孔区域设于该第一区域之中。
12.如权利要求7所述的接合结构，其特征在于，该凸起结构由金属所制成，以改善该接合结构的散热能力。
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