CN101419570A - Memory device addressing apparatus and method - Google Patents
Memory device addressing apparatus and method Download PDFInfo
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- CN101419570A CN101419570A CNA2007101673475A CN200710167347A CN101419570A CN 101419570 A CN101419570 A CN 101419570A CN A2007101673475 A CNA2007101673475 A CN A2007101673475A CN 200710167347 A CN200710167347 A CN 200710167347A CN 101419570 A CN101419570 A CN 101419570A
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Abstract
The invention discloses an addressing device and a method thereof. The device and the method can cause an electronic device with minor addressing capability to address a memory device with larger storage space so as to lower the manufacturing cost of an electronic system. The addressing device comprises an address decoding unit and an address conversion unit; the address decoding unit receives a first access address in a smaller address space, and decides whether to map the first access address to the memory device, and the address conversion unit is coupled to the address decoding unit. When the first access address is mapped to the memory device, the address conversion unit converts the first access address into a second access address in the larger storage space according to an adjustable base address.
Description
Technical field
What the present invention relates to is a kind of addressing of memory storage, refers to a kind of device for addressing and method that makes the microcontroller with less memory address ability can use big internal memory especially.
Background technology
In electronic system, use microcontroller (micro controller) (or microprocessor (micro processor)) when coming executive routine or deal with data, internal memory need be used or buffer comes temporal data, generally speaking, microcontroller only has deposits addressing capability within limited, deposit addressing capability within the microcontroller and limited the memory size that described microcontroller can use, for example, if when depositing addressing capability within the microcontroller and being the 64K size, just can't directly address greater than depositing within the 64K byte.When the function of system is increasingly sophisticated, just deposits within microcontroller can use and not apply use.
Yet, use microcontroller if change with big internal memory addressing capability, because it costs an arm and a leg, can cause the manufacturing cost of electronic system to heighten again, be unfavorable for the price competitiveness of manufacturer.
Summary of the invention
In view of this, a purpose of the present invention is to provide a kind of device for addressing and method, allows the electronic installation addressable with less addressing capability have the memory storage of storage area greatly, to reduce the manufacturing cost of electronic system.
The present invention discloses a kind of device for addressing, in order to have the memory storage of a storage area according to an address space (address space) addressing.Described device for addressing comprises address decoding unit and address conversioning unit.Address decoding unit receives first access address in the described address space, and whether decision videos first access address to described memory storage.Address conversioning unit is coupled to address decoding unit.When first access address was mapped to described memory storage, address conversioning unit was converted to first access address second access address of described storage area according to adjustable first base address (base address).
The present invention discloses a kind of addressing method in addition, in order to have the memory storage of a storage area according to an address space addressing.Described addressing method comprises the following step: receive first access address in the described address space; Whether decision videos first access address to described memory storage; And when first access address is mapped to described memory storage, according to adjustable first base address, first access address is converted to second access address in the described storage area.
Description of drawings
Fig. 1 is the calcspar of an embodiment of device for addressing of the present invention;
Fig. 2 is the reflection relation of the address space and the storage area in the memory storage of displayed map 1;
Fig. 3 is the process flow diagram of an embodiment of addressing method of the present invention;
Description of reference numerals: 10-device for addressing; The 11-address decoding unit; 111,112-comparer; The 12-address conversioning unit; The 13-memory storage; The 20-address space; Space, 21-first subaddressing; Space, 22-second subaddressing; The 23-storage area; All the other spaces, subaddressing of 24-; The flow process of one embodiment of 30～33-addressing method.
Embodiment
Below in conjunction with accompanying drawing, be described in more detail with other technical characterictic and advantage the present invention is above-mentioned.
Fig. 1 is the calcspar of an embodiment of device for addressing of the present invention, and wherein, device for addressing 10 can be according to addressing of address one memory storage 13 of address space.Address space can be considered the set that comprises a plurality of addresses, and the quantity of address is the size of address space.Number of addresses is many more, and address space is also big more, and anti-is also right.The size of address space is represented the power of addressing capability, addressing capability is strong more, the storage area of expression institute energy addressing is big more, for example, the address space of a 64K size has 64K address and can be used to carry out addressing, and if the storage area of the corresponding byte in each address, then the addressable storage area of the address space of described 64K is the 64K byte.In a preferred embodiment, address space can addressing the storage area be less than the storage area in the memory storage 13, also, the size of the storage area in the memory storage 13 surpasses the addressing capability of address space.For example, address space may be 64K size (0000 to FFFF that the address that it comprised can 16 carries represent), and the storage area of memory storage 13 may be 64M byte-sized (16 carry addresses be 0000000 to 3FFFFFF).Change speech, device for addressing 10 can come addressing to have the memory storage 13 of big storage area according to less address space.Memory storage 13 can comprise DRAM (Dynamic Random Access Memory) (DRAM) or flash memory (flashmemory) etc.Fig. 2 is reflection (mapping) relation of the storage area 23 of explicit address space 20 and memory storage 13.As shown in Figure 2, address space 20 comprises space, non-overlapping first subaddressing 21 and space, second subaddressing 22.Space, first subaddressing 21 is mapped to that first base address and first base address add first unit value between the two in the storage area 23, and space, second subaddressing 22 is mapped to that second base address and second base address add second unit value between the two in the storage area 23.First base address and second base address can be that unit adjusts with first unit value and second unit value respectively.Therefore, with regard to space, first subaddressing 21, storage area 23 is distinguished into plural number page or leaf (page), and every page size is first unit value, in like manner, also is so with regard to space, second subaddressing 22, and the size that is every page is second unit value.Change speech, by adjusting first base address and second base address, device for addressing 10 can make video respectively to the storage area each address section of 23 of space, first subaddressing 21 and space, second subaddressing 22, so can allow electronic installation with less addressing capability reach the effect of the big storage area of addressing.
In addition, though space, first subaddressing 21 and space, second subaddressing 22 non-overlappings own, but, the address section of the storage area 23 that space, first subaddressing 21 and space, second subaddressing 22 videoed is overlapped each other by first base address and second base address are transferred closely.Change speech, by the different space, subaddressing of address space 20, but the data of identical address in the access storage area 23, to reach the effect of data sharing.
In a preferred embodiment, second unit value is less than first unit value, and so storage area 23 can fully be used.For example, if first unit value is 64K, and space 21, first subaddressing is less than 64K, and then when space, first subaddressing 21 is videoed to storage area 23, every page (size is the first unit value 64K) just has partial section and be not mapped in the storage area 23.At this moment, if use less second unit value (as 4K), just second base address can be adjusted to the aforementioned interval that is not mapped to, it is videoed by space, second subaddressing 22, so, just can come access original, and fully use storage area 23 by space, second subaddressing 22 not by the interval of space, first subaddressing 21 reflections.
Refer again to Fig. 1.Device for addressing 10 comprises an address decoding unit 11 and an address conversioning unit 12.First access address in the address decoding unit 11 receiver address spaces 20, and whether decision videos first access address to memory storage 13.Address conversioning unit 12 is coupled to address decoding unit 11.When first access address was mapped to memory storage 13, address conversioning unit 12 can be converted to first access address second access address in the storage area 23.
When first access address belongs to space 21, first subaddressing, address conversioning unit 12 is according to first base address, first access address is converted to second access address, for example, second access address is that first base address adds first access address or its some (as a plurality of lowest orders (least significant bit) of first access address); When first access address belonged to space 22, second subaddressing, address conversioning unit 12 was converted to second access address according to second base address with first access address, and for example, second access address is that second base address adds first access address or its some.
In one embodiment, first access address is to be provided by microcontroller (figure does not a show) institute with addressing address space 20 abilities, and 13 of memory storages comprise a dynamic random access memory controller (DRAM controller) and a DRAM (Dynamic Random Access Memory) (figure does not show).In address space 20, except videoing to the space, first subaddressing 21 and space, second subaddressing 22 of memory storage 13, address translation need not be carried out in 24 in remaining space, subaddressing, directly address is to other function square, as the static random access memory (SRAM) of microcontroller inside or the buffer of the every running information of storage system (for example, depositing first and second base address, first and second LLA and first and second HLA).Therefore, address decoding unit 11 can judge that first access address that microcontroller is sent into is which block (space, first subaddressing 21, space, second subaddressing 22 or space, subaddressing 24) that belongs to address space 20, carries out corresponding addressing action again.In addition, access to produce the physical address of DRAM (Dynamic Random Access Memory), is carried out to DRAM (Dynamic Random Access Memory) in second access address that dynamic random access memory controller is then provided according to address conversioning unit 12.
Fig. 3 is the process flow diagram of an embodiment of addressing method of the present invention.Described addressing method can be according to addressing of address one memory storage of address space.The addressable storage area of address space is less than the storage area in the described memory storage, and address space comprises non-overlapping space, first subaddressing and space, second subaddressing.Described addressing method comprises the following step:
Step 30: first access address in the receiver address space.
Step 31: when first access address belongs to space, first subaddressing or space, second subaddressing, videoed to described memory storage in first access address.
Step 32: when first access address belongs to space, first subaddressing,, first access address is converted to second access address of the storage area of described memory storage according to adjustable first base address.
Step 33: when first access address belongs to space, second subaddressing,, first access address is converted to second access address of the storage area of described memory storage according to adjustable second base address.
First base address is to adjust according to first unit value, and second base address is to adjust according to second unit value.Second unit value is less than first unit value.
In one embodiment, step 32 is that first base address is added first access address or its some (as a plurality of lowest orders of first access address), to produce second access address; Step 33 is that second base address is added first access address or its some, to produce second access address.
The above is to utilize preferred embodiment to describe the present invention in detail, but not limits the scope of the invention.Allly know this type of skill personage and can both understand, can make many may the variation, still do not break away from the spirit and scope of the present invention according to the announcement of above embodiment.
Claims (21)
1, a kind of device for addressing, in order to foundation one address space addressing one memory storage, described memory storage has a storage area, it is characterized in that: described device for addressing comprises:
One address decoding unit receives one first access address in the described address space, and whether decision videos described first access address to described memory storage; And
One address conversioning unit, be coupled to described address decoding unit, when described first access address is mapped to described memory storage, described address conversioning unit is converted to described first access address one second access address of described storage area according to adjustable first base address.
2, device for addressing according to claim 1 is characterized in that: the storage area of described address space addressing is less than the storage area of described memory storage.
3, device for addressing according to claim 1 is characterized in that: described first base address is to adjust according to a unit value.
4, device for addressing according to claim 1 is characterized in that: described second access address is the part that described first base address adds described first access address or described first access address.
5, device for addressing according to claim 1, it is characterized in that: described address space comprises space, one first subaddressing, when described first access address belonged to space, described first subaddressing, described address decoding unit can make described first access address reflection to described memory storage.
6, device for addressing according to claim 5 is characterized in that: described address decoding unit comprises:
One comparer compares respectively in order to a lower limit address and a HLA with described first access address and space, described first subaddressing.
7, device for addressing according to claim 1, it is characterized in that: described address space comprises non-overlapping space, one first subaddressing and space, one second subaddressing, when described first access address belonged to described space, first subaddressing or space, described second subaddressing, described address decoding unit can make described first access address reflection to described memory storage.
8, device for addressing according to claim 7, it is characterized in that: when described first access address belongs to space, described first subaddressing, described address conversioning unit is converted to described second access address according to described first base address with described first access address; When described first access address belonged to space, described second subaddressing, described address conversioning unit was converted to described second access address according to adjustable second base address with described first access address.
9, device for addressing according to claim 8, it is characterized in that: when described first access address belonged to space, described first subaddressing, described second access address was the part that described first base address adds described first access address or described first access address; When described first access address belonged to space, described second subaddressing, described second access address was the part that described second base address adds described first access address or described first access address.
10, device for addressing according to claim 8 is characterized in that: described first base address is to adjust according to one first unit value, and described second base address is to adjust according to one second unit value.
11, device for addressing according to claim 10 is characterized in that: described second unit value is less than described first unit value.
12, device for addressing according to claim 7 is characterized in that: described address decoding unit comprises:
One first comparer compares respectively in order to a lower limit address and a HLA with described first access address and space, described first subaddressing; And
One second comparer compares respectively in order to a lower limit address and a HLA with described first access address and space, described second subaddressing.
13, a kind of addressing method, in order to have the memory storage of a storage area according to an address space addressing one, it is characterized in that: described addressing method comprises the following step:
Receive one first access address in the described address space;
Whether decision videos described first access address to described memory storage; And
When described first access address is mapped to described memory storage,, described first access address is converted to one second access address of described storage area according to adjustable first base address.
14, addressing method according to claim 13 is characterized in that: the storage area of described address space addressing is less than the storage area of described memory storage.
15, addressing method according to claim 13 is characterized in that: described first base address is to adjust according to a unit value.
16, addressing method according to claim 13 is characterized in that: described second access address is the part that overlapping described first base address adds described first access address or described first access address.
17, addressing method according to claim 13, it is characterized in that: described address space comprises the not space, one first subaddressing and the space, one second subaddressing of phase, when described first access address belonged to described space, first subaddressing or space, described second subaddressing, described first access address was mapped to described memory storage.
18, addressing method according to claim 17, it is characterized in that: when described first access address belongs to space, described first subaddressing, described address translation step is converted to described second access address according to described first base address with described first access address; When described first access address belonged to space, described second subaddressing, described address translation step was converted to described second access address according to adjustable second base address with described first access address.
19, addressing method according to claim 18, it is characterized in that: when described first access address belonged to space, described first subaddressing, described second access address was the part that described first base address adds described first access address or described first access address; When described first access address belonged to space, described second subaddressing, described second access address was the part that described second base address adds described first access address or described first access address.
20, addressing method according to claim 18 is characterized in that: described first base address is to adjust according to one first unit value, and described second base address is to adjust according to one second unit value.
21, addressing method according to claim 20 is characterized in that: described second unit value is less than described first unit value.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101673475A CN101419570B (en) | 2007-10-25 | 2007-10-25 | Memory device addressing apparatus and method |
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| CN2007101673475A CN101419570B (en) | 2007-10-25 | 2007-10-25 | Memory device addressing apparatus and method |
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| CN101419570B CN101419570B (en) | 2012-07-04 |
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| CN2007101673475A Expired - Fee Related CN101419570B (en) | 2007-10-25 | 2007-10-25 | Memory device addressing apparatus and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279811A (en) * | 2010-06-09 | 2011-12-14 | 联咏科技股份有限公司 | Adaptive address conversion method and controller applied to high-bandwidth low-voltage system |
| CN106294187A (en) * | 2015-05-15 | 2017-01-04 | 比亚迪股份有限公司 | The control method of position accessing operation function and device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1149185A (en) * | 1995-10-13 | 1997-05-07 | 合泰半导体股份有限公司 | Method and device for extending memory |
| JP2006293663A (en) * | 2005-04-11 | 2006-10-26 | Sanyo Electric Co Ltd | Device for generating memory address and processor with same, and method of generating memory address |
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2007
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279811A (en) * | 2010-06-09 | 2011-12-14 | 联咏科技股份有限公司 | Adaptive address conversion method and controller applied to high-bandwidth low-voltage system |
| CN102279811B (en) * | 2010-06-09 | 2014-07-09 | 联咏科技股份有限公司 | Adaptive address conversion method and controller applied to high-bandwidth low-voltage system |
| CN106294187A (en) * | 2015-05-15 | 2017-01-04 | 比亚迪股份有限公司 | The control method of position accessing operation function and device |
| CN106294187B (en) * | 2015-05-15 | 2019-11-08 | 比亚迪股份有限公司 | The control method and device of position accessing operation function |
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| CN101419570B (en) | 2012-07-04 |
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Effective date of registration: 20200416 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Patentee after: MEDIATEK Inc. Address before: Hsinchu County, Taiwan, China Patentee before: MSTAR SEMICONDUCTOR Inc. |
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