CN101414088B - Liquid crystal display panel - Google Patents
Liquid crystal display panel Download PDFInfo
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- CN101414088B CN101414088B CN2008101766690A CN200810176669A CN101414088B CN 101414088 B CN101414088 B CN 101414088B CN 2008101766690 A CN2008101766690 A CN 2008101766690A CN 200810176669 A CN200810176669 A CN 200810176669A CN 101414088 B CN101414088 B CN 101414088B
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Abstract
The invention provides a liquid crystal display panel which comprises a display space, a surrounding circuit zone, a seaming reserve zone, a plurality of first testing thin film transistors, a plurality of second testing thin film transistors, a plurality of first signal wires, a plurality of second signal wires, a blank interval and at least a first adjustment thin film transistor. The first testing thin film transistors and the second testing thin film transistors are all provided with a transistor width which is distributed on the seaming reserve zone according to a fixed interval. The width of the blank interval is not less than twice as much as the sum of the fixed interval and the transistor width; and at least the first adjustment thin film transistor is distributed in the blank interval. Therefore, the liquid crystal display panel can effectively the problem of ribbon stains generated in testing the liquid crystal display panel.
Description
Technical field
The present invention relates to a kind of display panels; In more detail, relate to a kind of display panels of avoiding when test, producing banded color spot (Band Mura).
Background technology
In recent years, the development of flat-panel screens is more and more rapider, has replaced traditional cathode-ray tube display gradually.LCD is the main flow of flat-panel screens.And along with application such as automobile, mobile product increase day by day, in, the demand of small size panel also constantly increases fast.In the manufacturing, during the small size display panels, manufacturer usually can be in backend process (back end of the line; BEOL) in, import a voltage signal to display panels through short bar (shorting bar) design by a testing circuit, whether normal with the Presentation Function that detects display panels.After the detection of backend process was finished, manufacturer made in the display panels immediately with laser cutting short bar circuit, presents separate state between each bar sweep trace, data line and the testing circuit, and then make display panels be able to normal running.And owing to simplify the demand of technology, manufacturer little by little uses thin film transistor (TFT) to replace aforesaid short bar circuit, whether inputs to display panels with the voltage signal of control detection circuit.
Whether known display panels promptly electrically connects each bar sweep trace, data line and testing circuit with a plurality of thin film transistor (TFT)s, and normal by the Presentation Function of thin film transistor (TFT) and testing circuit detection display panels.When manufacturer carries out the detection of display panels, will make these thin film transistor (TFT) conductings via testing circuit.Subsequently, by these thin film transistor (TFT)s, the voltage signal of testing circuit will be input to each bar sweep trace, the data line of display panels, so as to carrying out the detection of display panels.After the detection for the treatment of display panels is finished, then testing circuit is connected to a voltage source,, makes these thin film transistor (TFT)s be maintained at the state that opens circuit by this voltage source.Thus, come the voltage signal of control detection circuit whether to input to display panels, can simplify backend process in certain degree ground by thin film transistor (TFT).
Yet, because it is not whole unanimities that these thin film transistor (TFT)s are arranged at the density position of display panels, to cause in manufacturing process, causing the difference on the thin film transistor (TFT) because of load effect (loading effect), and then make when detecting, be input to each bar sweep trace of display panels via thin film transistor (TFT) when the voltage signal of testing circuit, during data line, because each thin film transistor (TFT) electrical property difference, particularly contiguous clear area is bigger with electrical property difference away from the thin film transistor (TFT) of clear area, and then causes display panels banded color spot (Band Mura) to occur.Thus, manufacturer judges display panels by accident because of banded color spot and will greatly increase for the probability of the product that damages when detecting display panels.
Therefore, avoid its viewing area the problem of banded color spot to occur how when detecting display panels, and then reduce the probability of erroneous judgement display panels for the product that damages, be the display panel manufacturer target that still need make great efforts to solve now.
Summary of the invention
For overcoming the defective of prior art, fundamental purpose of the present invention is to provide a kind of display panels, and it comprises a viewing area, a periphery circuit district, engages between trough, a plurality of first testing film transistor, a plurality of second testing film transistor, a plurality of first signal wire, a plurality of secondary signal line, a clear area and at least one adjustment thin film transistor (TFT).The periphery circuit district is positioned at the periphery of viewing area.Engage trough and be positioned at the periphery circuit district.Described a plurality of first testing film transistor is formed between one first test section, have one first relative side and one second side between this first test section, the described first testing film transistor all has a transistor width, be distributed on the joint trough according to fixed intervals, wherein the two first adjacent testing film transistors have a spacing, and the width of spacing is the summation of transistor width and fixed intervals.Described a plurality of second testing film transistor is formed between one second test section, have one the 3rd relative side and one the 4th side between this second test section, the described second testing film transistor all has transistor width, be distributed on the joint trough according to fixed intervals, wherein the two second adjacent testing film transistors have spacing.One end of first signal wire be electrically connected to respectively corresponding first testing film transistorized one of them, simultaneously, the other end of first signal wire then is electrically connected to the viewing area respectively.One end of secondary signal line be electrically connected to respectively corresponding second testing film transistorized one of them, simultaneously, the other end of secondary signal line then is electrically connected to the viewing area respectively.Have a width between the clear area, and be formed between the first testing film transistor AND gate, the second testing film transistor, and in abutting connection with second side between this first test section and the 3rd side between this second test section.At least one adjustment thin film transistor (TFT) then is laid between the clear area.Width between the clear area is not less than the summation of twice fixed intervals and transistor width.
In sum, by the setting of adjusting thin film transistor (TFT) and adjusting signal wire, display panels provided by the invention can solve display panels very easily produces banded color spot when detecting problem effectively.
Behind the embodiment of consulting accompanying drawing and describing subsequently, affiliated technical field those of ordinary skill just can be understood other purpose of the present invention, advantage and technological means of the present invention and embodiment.
Description of drawings
Fig. 1 is the synoptic diagram of display panels of the present invention;
Fig. 2 is the synoptic diagram of the preferred embodiment of display panels of the present invention;
Fig. 3 is the transistorized synoptic diagram of first testing film of display panels of the present invention; And
Fig. 4 to Fig. 8 is the synoptic diagram of other preferred embodiment of display panels of the present invention.
Description of reference numerals in the above-mentioned accompanying drawing is as follows:
4: display panels 41: viewing area
43: periphery circuit district 45: engage trough
405: grid test contact pin 407a, 407b: the first test contact pin
409a, 409b: signal wire is adjusted in the second test contact pin at 411: the first
The adjustment signal wire was adjusted signal wire in 415: the three in 413: the second
Between 451: the first test sections between 453: the second test sections
451a: the first side 451b between first test section: second side between first test section
453c: the 3rd side 453d between second test section: the 4th side between second test section
455: c between the clear area: the first testing film transistor
D: the second testing film transistor e: first adjusts thin film transistor (TFT)
F: second adjusts thin film transistor (TFT) g: the 3rd adjusts thin film transistor (TFT)
C1: the first testing film transistor drain
C2: the transistorized source electrode of first testing film
C3: the transistorized grid of first testing film
C4: the transistorized separation layer of first testing film
P: spacing W: the width between the clear area
X: fixed intervals Y: transistor width
Embodiment
Below will explain content of the present invention, the present invention relates to a kind of display panels by embodiment.Explanation about embodiment only is explaination purpose of the present invention, but not in order to restriction the present invention.It should be noted that, in following examples and the accompanying drawing, omitted all with the non-directly related element of the present invention and not shown; And each interelement size relationship is only for asking easy understanding in the accompanying drawing, and is non-in order to the restriction actual ratio.
Fig. 1 is the synoptic diagram of a display panels 4, and its display panels 4 comprises a viewing area 41, a periphery circuit district 43 and engages trough 45.Viewing area 41 is the picture-display-region territory of display panels 4.Periphery circuit district 43 is positioned at the periphery of viewing area 41.Engage 45 of troughs and be positioned at periphery circuit district 43, joint trough 45 can be the reserved area in the periphery circuit district 43, is engaged in this for wafer.Fig. 2 then illustrates an embodiment of display panels, a plurality of first testing film transistor c, a plurality of second testing film transistor d, a plurality of first signal wire 401, a plurality of secondary signal line 403, grid test contact pin 405, at least one first test contact pin 407a, 407b and at least one second test contact pin 409a, 409b.Each first signal wire 401 electrically connects with corresponding first testing film transistor c and viewing area 41 respectively; Each secondary signal line 403 electrically connects with corresponding second testing film transistor d and viewing area 41 respectively.Respectively by the first test contact pin 407a, 407b and the second test contact pin 409a, 409b, whether whether the first testing film transistor c and the second testing film transistor d may command voltage signal input to the viewing area 41 of display panels 4, unusual for the test fluid LCD panel.
Specifically, the voltage signal of at least one first test contact pin 407a, 407b inputs to viewing area 41 by the first testing film transistor c and corresponding first signal wire 401 thereof; The voltage signal of at least one second test contact pin 409a, 409b then inputs to viewing area 41 by the second testing film transistor d and corresponding secondary signal line 403 thereof.In the preferred embodiment, the number of the first test contact pin can be a plurality of, and the first test contact pin 407a and the first test contact pin 407b can be connected to the first testing film transistor c alternately respectively; And that the number of the second test contact pin can be is a plurality of, and the second test contact pin 409a and the second test contact pin 409b can be connected to the second testing film transistor d alternately respectively.The mode of utilizing the first test contact pin 407a, 407b to be cross-linked, and provide the two first adjacent signal wires 401 to have the signal source of phase differential, when display panels has defective, help to judge which first signal wire 401 is defective be from.Similarly, the mode of utilizing the second test contact pin 409a, 409b to be cross-linked, and provide two adjacent second signal lines 403 to have the signal source of phase differential, when display panels has defective, help to judge which secondary signal line 403 is defective be from.Shown in the number of the first test contact pin (or second test contact pin) is not limited on the figure, can adjust required number according to actual conditions, for example can have three first test contact pin is cross-linked to the first testing film transistor, and the person of an ordinary skill in the technical field can be directly acquainted with its annexation and distribution based on the description of leading portion, so do not repeat them here.
Be distributed on the joint trough 45 (being shown in Fig. 1) with a fixed intervals X with reference to figure 2, the first testing film transistor c and the second testing film transistor d.The first testing film transistor c can form between one first test section between 451, the first test sections 451 and have one first relative side 451a and one second side 451b; Similarly, the second testing film transistor d can form between one second test section between 453, the second test sections 453 and has one the 3rd relative side 453c and one the 4th side 453d.Have the first testing film transistor c of fixed intervals X and have and then form between a clear area 455 between the second testing film transistor d of fixed intervals X, be adjacent between first test section between 451 the second side 451b and second test section 453 the 3rd side 453c, and 455 have a width W between the clear area.
Fig. 3 then illustrates the structural representation of the first testing film transistor c.Each first testing film transistor c has drain electrode c1, an one source pole c2 and a grid c3.And the first testing film transistor c has a transistor width Y.Drain electrode c1 is electrically connected at first signal wire 401 respectively, and source electrode c2 is electrically connected to the first test contact pin 407a, 407b respectively, and grid c3 is electrically connected at grid test contact pin 405.The two first adjacent testing film transistor c then have a spacing (pitch) P, and this spacing P is the summation of transistor width Y and fixed intervals X.Each first testing film transistor c has a separation layer c4, in order between isolated gate c3, the source electrode c2 and between grid c3, the drain electrode c1.The second testing film transistor d is close with the first testing film transistor c notion, so do not repeat them here.
With reference to figure 2 and Fig. 3, it should be noted that to be not less than the summation of twice fixed intervals X and transistor width Y (be W 〉=Y+2X) to 455 width W between the clear area.In the preferred embodiment, 455 width W in fact can be greater than 1.4 times of the width of spacing P between the clear area, 455 width W in fact can be greater than 18 microns between the clear area, the scope of the width of the spacing P of the first testing film transistor c and the second testing film transistor d can be 12 microns to 17 microns in fact, for instance, if the width of spacing P is 16 microns, and fixed intervals X is 8 microns, when 455 width W between the clear area is 24 microns, can lays one first and adjust thin film transistor (TFT) e.The invention is not restricted to this, also can be according to the actual demand adjustment.
Specifically, because grid test contact pin 405 is electrically connected at the grid c3 of the first testing film transistor c and the grid d3 of the second testing film transistor d, therefore grid test contact pin 405 is the switch of the may command first testing film transistor c and the second testing film transistor d, also be its conducting whether.
With reference to figure 2 and Fig. 3.Because to be not less than the summation of twice fixed intervals X and transistor width Y (be W 〉=Y+2X) to 455 width W between the clear area, at least one first adjusts thin film transistor (TFT) e is laid between this clear area, to eliminate 455 pairs of the white spaces banded color spot phenomenon that display panels was caused.At least one first adjusts thin film transistor (TFT) e can be a plurality of first and adjusts thin film transistor (TFT) e, and between the clear area in 455, but then fixed intervals X is laid with a plurality of first and adjusts thin film transistor (TFT) e.Wherein, the laying mode can be laid first with fixed intervals X to central authorities by 455 two ends between the clear area (promptly between first test section between 451 the second side 451b and second test section 453 the 3rd side 453c) according to the width W size and adjust thin film transistor (TFT) e, till can't laying.In other words, promptly beginning between the clear area 455 central authorities with 455 both sides between the clear area lays first and adjusts thin film transistor (TFT) e, first adjusts thin film transistor (TFT) e lays with fixed intervals X in twos, laying can no longer be laid to the remaining area of 455 central authorities between the clear area summation less than twice fixed intervals X and transistor width Y.
In addition, the present invention can have a plurality of first end of adjusting signal wires 411 and is electrically connected to corresponding first respectively and adjusts thin film transistor (TFT) e.And first other end of adjusting signal wire 411 is connected to each other forming a sealing abutting end, and then avoids static discharge (Electrostatic Discharge; ESD), reduce component wear.Be noted that the present invention does not limit first other end of adjusting signal wire 411 must be interconnected into a sealing abutting end, it can not be the form that connects according to the actual demand adjustment yet.Simultaneously, the present invention does not limit the length of the first adjustment signal wire 411 yet, it is along the edge of first signal wire 401 and secondary signal line 403 and adjust, with Fig. 2 is example, first length of adjusting signal wire 411 is adjusted along the edge of first signal wire 401 and secondary signal line 403, thereby the sealing abutting end presents trapezoidal profile; If first signal wire 401 and secondary signal line 403 are electrically connected to viewing area 41 with parallel construction, first length of adjusting signal wire 411 is adjusted along the edge of first signal wire 401 and secondary signal line 403, thereby the sealing abutting end presents rectangular distribution (as shown in Figure 8).
Be noted that, the present invention does not limit the number of the first adjustment thin film transistor (TFT) e, can lay first with fixed intervals X to central authorities by 455 two ends between the clear area (promptly between first test section between 451 the second side 451b and second test section 453 the 3rd side 453c) according to 455 width W sizes between the clear area and adjust thin film transistor (TFT) e, till can't laying.In addition, first number of adjusting signal wire 411 can corresponding first be adjusted the number of thin film transistor (TFT) e.
First adjust thin film transistor (TFT) e except what lay in 455 between the clear area, display panels 4 shown in Fig. 2 also can comprise one second and adjust thin film transistor (TFT) f, it is adjacent between first test section 451 the first side 451a, and one second end of adjusting signal wire 413 is connected to second and adjusts thin film transistor (TFT) f.Display panels 4 shown in Fig. 2 also can comprise one the 3rd and adjust thin film transistor (TFT) g, and it is adjacent between second test section 453 the 4th side 453d, and one the 3rd end of adjusting signal wire 415 then is connected to the 3rd and adjusts thin film transistor (TFT) g.Second number of adjusting thin film transistor (TFT) f and the 3rd adjustment thin film transistor (TFT) g only is for example, also can be according to the actual demand adjustment.Second adjusts signal wire 413 and the 3rd adjusts the number that the corresponding respectively second adjustment thin film transistor (TFT) f of number and the 3rd of signal wire 415 adjusts thin film transistor (TFT) g.
It should be noted that, except wherein a kind of embodiment of the display panels shown in Fig. 24.Fig. 4 to Fig. 8 illustrates other different types of embodiment of display panels 4.Fig. 4 illustrates the embodiment that only has the first adjustment thin film transistor (TFT) e; Fig. 5 illustrates has the embodiment that the first adjustment thin film transistor (TFT) e and first adjusts signal wire 411; Fig. 6 illustrates only has the embodiment that the first adjustment thin film transistor (TFT) e, second adjusts thin film transistor (TFT) f and the 3rd adjustment thin film transistor (TFT) g; Fig. 7 illustrates has the embodiment that the first adjustment thin film transistor (TFT) e, second adjusts thin film transistor (TFT) f, the 3rd adjustment thin film transistor (TFT) g and the first adjustment signal wire 411.First signal wire 401 and secondary signal line 403 that Fig. 8 then illustrates display panels 4 are electrically connected to viewing area 41 with parallel construction.And the first adjustment signal wire 411 also is electrically connected at the first adjustment thin film transistor (TFT) e with parallel construction.The palpus expositor, preferred embodiment is the display panels shown in Fig. 24.
In sum, when carrying out the detection of viewing area 41 of display panels 4 by grid test contact pin 405, the first test contact pin 407a, 407b and the second test contact pin 409a, 409b, grid test contact pin 405 will make win the testing film transistor c and the second testing film transistor d conducting.Subsequently, by the first testing film transistor c and the second testing film transistor d, the voltage signal of the first test contact pin 407a, 407b and the second test contact pin 409a, 409b will be input to viewing area 41 via first signal wire 401 and secondary signal line 403 respectively, and carry out the detection of display panels 4.
Simultaneously, owing to can be provided with first between the clear area of display panels 4 in 455 and adjust thin film transistor (TFT) e, second and adjust thin film transistor (TFT) f and the 3rd and adjust thin film transistor (TFT) g.As the first test contact pin 407a, the voltage signal of 407b is via the first testing film transistor c and first signal wire 401 and the second test contact pin 409a, when the voltage signal of 409b is input to viewing area 41 via the second testing film transistor d and secondary signal line 403, to be avoided different and to avoid different adjacent to the load effect between 455 the second testing film transistor d between 455 the second testing film transistor d between the clear area and other non-adjacent clear area adjacent to the load effect between 455 the first testing film transistor c between 455 the first testing film transistor c between the clear area and other non-adjacent clear area, make its electrical property difference more approaching, and then avoid occurring in the viewing area 41 banded color spot.Thus, when detecting display panels, judge display panels by accident because of banded color spot and will reduce widely, also promoted the production efficiency of display panels for the probability of the product that damages.
The above embodiments only are used for exemplifying embodiments of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting protection scope of the present invention.Any those skilled in the art can unlabored change or the arrangement of the identity property scope that all belongs to the present invention and advocated, and the scope of the present invention should be as the criterion with claim.
Claims (14)
1. display panels comprises:
One viewing area;
One periphery circuit district is positioned at the periphery of this viewing area;
One engages trough, is positioned at this periphery circuit district;
A plurality of first testing film transistors, be formed between one first test section, have one first relative side and one second side between this first test section, described a plurality of first testing film transistor all has a transistor width, be distributed on this joint trough according to fixed intervals, wherein two adjacent described a plurality of first testing film transistors have a spacing, and the width of this spacing is the summation of this transistor width and these fixed intervals;
A plurality of second testing film transistors, be formed between one second test section, have one the 3rd relative side and one the 4th side between this second test section, described a plurality of second testing film transistor all has this transistor width, be distributed on this joint trough according to these fixed intervals, wherein two adjacent described a plurality of second testing film transistors have this spacing;
A plurality of first signal wires, an end of described a plurality of first signal wires, be electrically connected to respectively corresponding described a plurality of first testing films transistorized one of them, the other end of described a plurality of first signal wires is electrically connected to this viewing area respectively;
A plurality of secondary signal lines, an end of described a plurality of secondary signal lines, be electrically connected to respectively corresponding described a plurality of second testing films transistorized one of them, the other end of described a plurality of secondary signal lines is electrically connected to this viewing area respectively;
Between one clear area, have a width, be formed between this clear area between the described a plurality of second testing film transistors of described a plurality of first testing film transistor AND gate, and in abutting connection with second side between this first test section and the 3rd side between this second test section; And
At least one first adjusts thin film transistor (TFT), is laid between this clear area;
Wherein, the width between this clear area is not less than the twice of these fixed intervals and the summation of this transistor width.
2. display panels as claimed in claim 1, also comprise grid test contact pin, be electrically connected at described transistorized grid of a plurality of first testing films and the transistorized grid of described a plurality of second testing films, in order to control the transistorized switch of described a plurality of second testing films of described a plurality of first testing film transistor AND gate.
3. display panels as claimed in claim 1, also comprise at least one first test contact pin and at least one second test contact pin, wherein, described at least one first test contact pin is electrically connected at the transistorized source electrode of described a plurality of first testing films, and described at least one second test contact pin is electrically connected at the transistorized source electrode of described a plurality of second testing films.
4. display panels as claimed in claim 3, wherein said at least one first test contact pin is a plurality of first test contact pin, described a plurality of first test contact pin is electrically connected at the transistorized source electrode of described a plurality of first testing films alternately, described at least one second test contact pin is a plurality of second test contact pin, and described a plurality of second test contact pin are electrically connected at the transistorized source electrode of described a plurality of second testing films alternately.
5. display panels as claimed in claim 1, wherein said at least one first adjustment thin film transistor (TFT) is a plurality of first adjustment thin film transistor (TFT)s.
6. display panels as claimed in claim 5, described a plurality of first adjusts thin film transistor (TFT) is laid between this clear area with these fixed intervals.
7. display panels as claimed in claim 5 also comprises a plurality of first and adjusts signal wire, and wherein, each first end of adjusting signal wire is electrically connected to one of them of corresponding described a plurality of first adjustment thin film transistor (TFT)s respectively.
8. display panels as claimed in claim 7, wherein, each first other end of adjusting signal wire is connected to each other to form a sealing abutting end.
9. display panels as claimed in claim 1 also comprises at least one second and adjusts thin film transistor (TFT), and wherein, described at least one second adjusts thin film transistor (TFT) in abutting connection with this first side between this first test section.
10. display panels as claimed in claim 9 also comprises at least one second and adjusts signal wire, and wherein, described at least one second end of adjusting signal wire is connected to described at least one second and adjusts thin film transistor (TFT).
11. display panels as claimed in claim 1 also comprises at least one the 3rd and adjusts thin film transistor (TFT), wherein, the described at least one the 3rd adjusts thin film transistor (TFT) in abutting connection with the 4th side between this second test section.
12. display panels as claimed in claim 11 also comprises at least one the 3rd and adjusts signal wire, wherein, described at least one the 3rd end of adjusting signal wire is connected to the described at least one the 3rd and adjusts thin film transistor (TFT).
13. display panels as claimed in claim 1, wherein the width between this clear area is in fact greater than 18 microns.
14. display panels as claimed in claim 1, wherein the scope of the width of this spacing is essentially 12 microns to 17 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101766690A CN101414088B (en) | 2008-11-14 | 2008-11-14 | Liquid crystal display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101766690A CN101414088B (en) | 2008-11-14 | 2008-11-14 | Liquid crystal display panel |
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| CN101414088A CN101414088A (en) | 2009-04-22 |
| CN101414088B true CN101414088B (en) | 2010-12-29 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101963714B (en) * | 2009-07-22 | 2012-07-04 | 群康科技(深圳)有限公司 | Liquid crystal panel and manufacturing method thereof |
| CN106910446B (en) * | 2017-04-19 | 2020-12-18 | 惠科股份有限公司 | Display panel |
| WO2019153299A1 (en) * | 2018-02-11 | 2019-08-15 | 华为技术有限公司 | Display screen and terminal device |
| CN109830197B (en) * | 2019-01-17 | 2022-03-15 | 昆山国显光电有限公司 | Test wire typesetting structure, display panel and display device |
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