Summary of the invention
According to the present invention, provide a kind of combination of adopting pulse frequency modulated and pulse width modulation to control the switched-mode power supply controller of mains switch equipment, this controller has: receive the input of the feedback signal relevant with output voltage; The output of driving said power switching device; And controller; In response to said feedback signal from said input; To said output switch controlling signal is provided, said switch controlling signal has the switch periods that comprises the ON part that is used to connect said mains switch equipment, wherein; Said controller is configured to use the pulse width values of at least one storage to select one of a plurality of discrete pulse width to the said ON part of said switch periods, and changes the duration of said switch periods in response to said feedback signal.
Can in the hardwire configuration of controller hardware, store the discrete pulse width; Perhaps can be with the discrete pulse width as storage (being non-volatile alternatively) in look-up table; Perhaps can pulse duration be stored in the controller through a plurality of pulse generators are provided, each in a plurality of pulse generators all is configured to provide the pulse with different fixed or preset width.
Alternatively; The pulse duration of at least one storage can comprise maximum pulse at least; Can confirm other discrete pulse width according to this maximum pulse then, for example through interior the inserting between this maximum pulse value and the minimum pulse width value (possibly be 0).Preferably, in this embodiment, controller is configured to use the minimum and maximum pulse width values of storage to select one of ON a plurality of discrete pulse width (having defined one group of available pulse duration) partly to said switch periods.Therefore, controller can basis and output voltage dependent feedback signal (perhaps more briefly doing, according to demand) increase/minimizing between the discrete pulse width value.Can use the silicon area littler to realize the embodiment of this type device than look-up table.
The discrete pulse width is to operate than similar mode with the gear of gear box.In some cases, for example in embodiment, for example a few gear possibly only is provided, for example less than 20,10 or 5 based on look-up table.In other cases, the discrete pulse width value can be very intensive, and many values are available.For the analogy of interrupted gear case, these embodiment are similar to the continuous variable transmission more.Gear is upgraded or lowers category, that is, incremented/decremented between the discrete pulse width, this can comprise that incremented/decremented is fixed or predetermined number (for example digital integer) or fixed fraction.Alternatively, can pulse duration/frequency correspondingly be adjusted compensation increment (or decrement), for example between predetermined minimum and maximum value.Preferably, store in the minimum and maximum pulse duration one or both.To be understood that, in an embodiment, the register of user-accessible can be provided, in order to store in these maximums and/or the minimum value one or more, for example maximum and/or minimum pulse width value can be user-accessibles; In other embodiments, can carry out hard coded (hardcoded) to these values.
In an embodiment; The power-supply device switch controlling signal has defined the ON part in the power-supply device switch periods; Following the OFF part of switch periods thereafter; The ON in this cycle part define by one of a plurality of pulse durations discrete or storage institute, and partly ending of the OFF in this cycle (and ON subsequently partly restart) is defined by feedback signal.This feedback signal provides information (the power-supply device switching information about SMPS output; Be Cycle by Cycle alternatively); Be preferably the variable value signal; Variable value signal and fiducial value are compared (for example), to confirm the timing that restarts of OFF ending/switch periods partly by means of voltage reference and comparator.
The technical staff will understand, and the embodiment of above-mentioned SMPS controller can be used in the large-scale SMPS configuration, include but is not limited to flyback converter, directly the be coupled boost converter and the step-down controller that directly is coupled.Comprise at SMPS under the situation of the transformer that is driven by mains switch equipment, can from the primary side of transformer (as said in a preferred embodiment the literary composition of back), or from the primary side of transformer, or derive feedback signal from the auxiliary winding of transformer.Replacing with inductor in the SMPS device of transformer, can derive feedback signal from primary side, primary side or the auxiliary winding of inductor similarly.
In a preferred embodiment; The controller configuration is used to confirm that (measurement) receives the duration of the switch periods of feedback signal control; For example through when switch periods begins, counter being resetted, and, the feedback signal indication confirms counting when should restarting switch periods.Yet on the traditional sense, controller comprises and is used to the system clock that counter provides clock, can define pulse duration discrete or storage like this according to the periodicity of this system clock.Then, can select pulse duration discrete or storage, thereby the control of Cycle by Cycle is provided in response to the duration in determined each mains switch cycle.
Preferably; This controller has a plurality of operational power range, wherein each operational power range can by the pulse duration of discrete or storage and for example, the combination of the scope of switch periods duration between lower-frequency limit and the upper frequency limit (can comprise the lower-frequency limit that is substantially zero) at minimum pulse width define.For controlled SMPS, each in these operational power range preferably defined the average power that each switch periods is transmitted by SMPS mains switch equipment.Preferably, defining operation power bracket (through pulse duration/combination of frequency) makes them that crossover take place, thereby the hysteresis to a certain degree that helps to forbid the hunting between the different capacity scope is provided.
In order to select power bracket, preferably controller is configured to select the pulse duration that increases less than lower threshold value in response to the duration of determined switch periods, and selects the pulse duration that reduces in response to the determined duration greater than upper threshold value.In other words, generally speaking, when switching frequency reduced, power supply lowered category gear, and when frequency raise, power supply upgraded gear.Recall, switching frequency in a preferred embodiment makes selected " gear " (pulse duration) depend on output loading by this way in response to output loading (more specifically being output voltage).Can define upper threshold value and lower threshold value according to duration or frequency, and preferably it is stored in the controller, for example be stored in other look-up table or one or more register; Alternatively, the selected pulse width values to different can adopt different upper threshold values and/or lower threshold value.
The embodiment of said system also make it possible to definition to most applications (except pulse duration for it is optional, the situation of the minimum value of predetermined value) the minimum operation frequency.Preferably, this minimum operation (switch periods) frequency is outside normal human auditory's scope, for example greater than 5KHz, 10KHz, 15KHz or be preferably 20KHz.Preferably, this frequency is scheduled to, and for example is stored in the controller.
Preferably; Controller comprises the data storage of one or more value that is used for storing n, m and p; One or more register for example; Wherein n has defined the duration of switch periods, and m has defined the number of the pulse duration of the storage that is used to select, and p has defined the minimum duration of pulse duration.Alternatively, definition is used for confirming the additional parameter q of maximum pulse.Preferably, these parameters define with the number of the system clock pulse counted.In an embodiment, m pulse duration changed between the maximum of the individual system clock cycle of q (or n/2) in the minimum ON time of p system clock cycle, and total switch periods is n system clock cycle at least.In a preferred embodiment, from feedback signal, derive timing signal (FBD), when the change of this feedback signal (transformation) indication output (voltage) value drops to below the threshold value and the beginning mains switch cycle.Be close together in these transformations position of (short FBD pulse) define the minimum duration of n the system clock pulse of counting, and has defined the maximum duty cycle of power-supply device switch controlling signal, for example is 50% in the present embodiment.
In related fields; The invention provides a kind of method of the combination of employing pulse frequency modulated and pulse width modulation with the switched-mode power supply controller of control mains switch equipment that be used to operate, this controller has: receive the input of the feedback signal relevant with output voltage; The output of driving said power switching device; And controller; In response to said feedback signal from said input; To said output switch controlling signal is provided; Said switch controlling signal has the switch periods that comprises the ON part that is used to connect said mains switch equipment, and said method comprises: use the pulse duration of at least one storage to select one of a plurality of discrete pulse width to the said ON part of said switch periods; And change duration of said switch periods in response to said feedback signal, to regulate the output of said switched-mode power supply.
The present invention also provides the processor control routine that is used to realize this method, specifically on mounting medium.Mounting medium can comprise dish, program storage or the data medium such as CD, electrical signal carrier.This code can comprise traditional calculating machine program code and/or be used to be provided with or control the code of ASIC or FPGA, or such as RTL (register transfer layer) code, Verilog
TM, or the code that is used for hardware description language of SystemC and so on.
The present invention also provides a kind of switched-mode power supply controller that comprises the device that is used to realize said method.
On the other hand; The invention provides a kind of combination of adopting pulse frequency modulated and pulse width modulation and control the switched-mode power supply controller of mains switch equipment; This controller has a plurality of operational power range; Each scope definition by the scope of said mains switch equipment in the average power of each switch periods transmission, each said scope is defined by following combination: the scope of the duration of one of a plurality of predetermined pulse width and said switch periods.
On the other hand, the invention provides the switched-mode power supply controller that mains switch equipment is controlled in a kind of combination of adopting pulse frequency modulated and pulse width modulation, this controller has: receive the input of exporting relevant feedback signal with power supply; The output of driving said power switching device; And digitial controller; In response to said feedback signal from said input; From said output switch controlling signal is provided, said switch controlling signal has the switch periods that comprises the ON part that is used to connect said mains switch equipment, wherein; Follow after the said ON part of said switch periods and be useful on the OFF part of breaking off said power-supply device; Wherein, said controller is configured to finish in response to said feedback signal the said OFF part of said switch periods, and restarts the said ON part of said switch periods; And said feedback signal comprises the variable value signal, and said controller is configured to said feedback signal value and fiducial value are compared, with the timing of confirming that said switch periods is restarted.
The present invention also provides a kind of combination of adopting pulse frequency modulated and pulse width modulation to control the switched-mode power supply controller of mains switch equipment, and this controller has: receive the input of the feedback signal relevant with output voltage; The output of driving said power switching device; And digitial controller, the said feedback signal in response to from said input provides switch controlling signal from said output; And wherein, said controller is configured to said pulse frequency and pulse duration are changed together, thereby keeps said pulse frequency greater than audio frequency in said pulse duration during greater than minimum pulse width.
On the other hand, the invention provides the switched-mode power supply controller that mains switch equipment is controlled in a kind of combination of adopting pulse frequency modulated and pulse width modulation, this controller has: receive the input of exporting relevant feedback signal with power supply; The output of driving said power switching device; And digitial controller, the said feedback signal in response to from said input provides switch controlling signal from said output; And wherein, said controller comprises: system counter is coupled to said input; Output pulse generator is coupled to the output and the said output of said system counter; Pulse duration look-up table, its output are coupled to the pulse duration control input of said output pulse generator; And pulse-width controller, be coupled to said system counter output and said pulse duration look-up table, select pulse duration to use said look-up table to said pulse generator.
On the other hand; The invention provides a kind of pulse duration and frequency modulation(FM) (PWFM) SMPS (switched-mode power supply) controller; Be configured to the feedback signal in response to the output condition of said SMPS is made a response; Control the drive signal of the mains switch equipment of said SMPS through PWFM, wherein, said controller has variable gear ratio; Said gear has been confirmed the operational power range of said SMPS than the scope of the available pulse duration of the said PWFM that has confirmed to join with the frequency dependence of said PWFM.
In a preferred embodiment, controller configuration is used for the control gear ratio, makes when frequency reduces, gear is used for the scope of available pulse duration of the operational power range that reduces of definite switched-mode power supply with selection than adjustment, and vice versa.In some preferred embodiments, with controller configuration be used to use the scope that is selected from said available pulse duration pulse duration, control said frequency in response to said feedback signal.The pairing output condition of this feedback signal can comprise the output current of power supply, the output voltage of power supply or the output loading of power supply.
In an embodiment, variable gear ratio comprises a plurality of fixing basically gear ratios; In other embodiments, gear is than comprising the gear ratio of continuous variable basically.In some preferred embodiments, further confirm than the scope of determined available pulse duration by gear by the pulse duration of at least one storage.
The present invention also provides a kind of switched-mode power supply that comprises aforesaid controller.
Embodiment
With reference to Fig. 1, this shows the illustrative switch mode power circuit 100 with domestic network supply input 102 and DC output 104.Power network input 102 is carried out rectification so that be that circuit 106a, b provide direct current; Circuit 106a, b supply power to NE BY ENERGY TRANSFER equipment (in this equipment, being transformer 108) through switchgear (be power IGBT (igbt) 110 in this example, be shown the part of power-supply controller of electric integrated circuit here).
Auxiliary winding 108b is provided for the direct current into 114 power supplies of SMPS controller on circuit 112, SMPS controller 114 provides drive signal to IGBT110, so that this equipment is carried out switching manipulation.When this switchgear was connected, energy was stored in the magnetic field of transformer 108, and when this switch breaks off, with the primary side that NE BY ENERGY TRANSFER is given transformer, energy was carried out rectification with level and smooth, thereby direct current output 104 is provided.
In the example shown, through through the optical isolator 116 that resistor 118 is driven the primary side feedback being offered reference voltage circuit 120 by VD.The transistor 116b of optical isolator 116 offers the feedback input (FB) on the controller 114 to the feedback signal on the circuit 122.SMPS operates in discontinuous conduction mode; Wherein be when switchgear breaks off, to stablize period output voltage afterwards and begin to descend (at this some place like what further specify after a while; Transformer begins to form loop circuit (ring), thereby gets into so-called oscillation phase).In the circuit of Fig. 1, when this switchgear is connection, give capacitor 124 chargings, and likewise charge to capacitor 128 through diode 130 through diode 126.In oscillation phase, diode 126 and 130 is for ending, and transistor 116b and pull-down-resistor 132 through optical isolator come from capacitor 124 guiding electric charges.Electric current through optical isolator is in according to output voltage or changes the fall off rate of the voltage at its control capacitance device 124 two ends less than the target on the primary side.Voltage on the feedback line 122 descends with identical speed basically, so the voltage on the circuit 122 is directly proportional with the SMPS output voltage basically, and by power-up period make a response.
Resistor 134 among the direct current supply line 106b is as current-sense resistor (typically less than 1 ohm); Thereby current sense (CS) input (reverse, because circuit 136 slave controllers 114 are connected to the other end of resistor 134) of controller 114 is provided on circuit 136.Can adopt this signal that current limliting is provided according to traditional approach.Circuit 138 provides guiding (BS) input of controller 114, can use this guiding input with controller V
DD Main line 140 rises to its operational voltage value, to realize quick startup.
Referring now to Fig. 2, it shows the details of the controller 114 among Fig. 1.Controller 114 comprises the digital pulse width/frequency control system 300 as hereinafter further describing.Block diagram among Fig. 2 about the principal character of control system 300 is, derives digital feedback signal (FBD) 140 through using comparator 144 that voltage on the feedback line 122 and reference voltage (being 2V in the embodiment shown) from voltage reference 142 are compared.Other optional circuit block can be provided, realize overcurrent protection (OCP), about V
DDOvervoltage protection (OVD), about V
DDUnder-voltage protection (UVD), overvoltage (high-voltage side) protection (OVP), overheat protector (OTP), system failure latch (FLI); And sleep controll block can be provided; To be provided at the out-of-work optional standby operating mode of some of them circuit (what for example, those annotate to go up asterisk may power down).Preferably, also comprise system clock 146, to be provided for power-up period digital system clock regularly definite as that the back literary composition further describes.In an embodiment, can adopt the system clock frequency in 1MHz to the 100MHz scope, for example 16MHz.In addition or alternatively, the external clock input can be provided.
Referring now to Fig. 3, it shows the more detailed block diagram of the numerical control system 300 among Fig. 2.Put it briefly; Control system 300 is provided for the driving pulse stream of control switch equipment (IGBT110) from exporting 302, so that the direct voltage that uses a value and adjustable power-up period switching frequency in one group of fixed pulse width value (" gear than ") to regulate output 104 places of the SMPS power supply among Fig. 1.
We are the integrated operation of illustrative system at first.
Digitial controller 300 has been realized Cycle by Cycle power supply plan as required.Each power-up period has the minimum duration that comprises n digital dock cycle.Power-up period has from p to q (for example, n/2) fixing one of turn-on time (on-time) (pulse duration) in individual digital dock cycle do not wait m, and the opening time (off-time) that is directed against the minimum value of the remaining time in n cycle.The value of m, n, p and optional q selects input CLKSEL [1:0] to confirm by the mains switch peak frequency.
Preferably, controller 300 uses not (undivided) internal digital clock of frequency division all the time, 16MHz for example, and do not consider the setting of CLKSEL, wherein CLKSEL has confirmed maximum electrical source switch frequency, shown in following table 1:
CLKSEL |
CLK frequency (MHz) |
Maximum switching frequency |
11 |
16 |
500kHz |
10 |
16 |
250kHz |
01 |
16 |
125kHz |
00 |
16 |
62.5kHz |
Table 1:CLKSEL confirms maximum switching frequency setting
SMPS adjusting through pulse frequency modulated (PFM) is to realize through prolonging appropriate amount (being confirmed by system feedback) opening time.When accomplishing a power-up period, prolong opening time, drop to till 0 up to the FBD signal, this indication SMPS output voltage has dropped to below its desired value and should begin new power-up period.Alternatively, can add less Cycle by Cycle frequency modulation(FM), to help the spread spectrum RF emission.
Second control loop monitoring actual switch frequency is so that hold it in the frequency place that can avoid the SMPS switching manipulation to fall into the audio-frequency noise frequency band.If switching frequency drops to f
CHANGE_DOWN, then pulse width mode (PWM) control successively decreases 1 with the PWM_MODE value.This selects next minimum PULSE_WIDTH value from pulse duration look-up table (LUT).
The PFM control loop compensates the pulse duration that reduces through the opening time that reduces between the power-up period, and this has the effect that increases switching frequency.When the power demands to SMPS reduced, this process continued, till reaching minimum pulse width q.Utilize this minimum pulse width, switching frequency is adjusted into as needed that kind low, regulate to realize SMPS.
On the contrary, if switching frequency is increased to f
CHANGE_UP, then pulse width mode control increases progressively 1 with the PWM_MODE value.This selects next maximum PULSE_WIDTH value from pulse duration look-up table (LUT).
The PFM control loop is through increasing the pulse duration that compensates increase opening time between the power-up period, and this has the effect that reduces switching frequency.When the power demands to SMPS improved, this process continued, till reaching maximum pulse n/2.Utilize this maximum pulse, switching frequency is adjusted, be its maximum permissible value to the maximum, regulate so that realize output.f
CHANGE_UPThe selection of value is following: f
CHANGE_UPValue is should be enough high to guarantee there is crossover between the power bracket that adjacent PULSE_WIDTH value can transmit, and therefore adjusting need not produce hunting (hunting) between two different pulse durations; And f
CHANGE_UPValue should be use up the low of actual capabilities, is intended to minimize switching loss and makes maximizing efficiency.
The electric weight that is transmitted in cycle at each mains switch is by confirming with the combination of switching frequency the turn-on time (pulse duration) of power-supply device, and switching frequency is confirmed by the interval between the power-up period.To the arbitrary collection of input voltage and loading condition, controller is confirmed suitable pulse duration, and the adjustment switching frequency, so that SMPS output is remained on expectation voltage.In fact, because the switch period must be always the integral multiple in digital dock cycle, therefore will there be little measurement to the Cycle by Cycle frequency variation.
Preferably, between the performance number scope that each pulse width values can be transmitted, there is the crossover of having a mind to.This provides hysteresis, prevents the continuous jump between a pulse width values and the next one.
In following table 2, provided exemplary pwm pulse width look-up table:
Table 2: pulse duration look-up table
In following table 3, provided the adjust frequency exemplary collection of threshold value of pulse duration:
CLKSEL[1:0] |
11 |
10 |
01 |
00 |
f
CHANGE_UP |
50KHz |
50KHz |
50KHz |
50KHz |
f
CHANGE_DOWN |
20.82KHz |
20.82KHz |
20.82KHz |
20.82KHz |
Table 3: the pulse duration threshold value of adjusting frequency
Refer again to Fig. 3, functional input and output are following:
Input:
FBD |
Feedback |
OCP |
Overcurrent protection |
OTP |
Overheat protector |
OVT |
Overvoltage protection |
FLI |
The input of fault latch device |
SLEEP_N |
(effectively low) resets |
CLK |
System clock |
CLKSEL[1:0] |
The mains switch peak frequency is selected |
Output:
DRIVE |
To the IGBT gate driver circuit |
The FBD signal is illustrated; The DRIVE signal provides the switch controlling signal of IGBT gate driver circuit, IGBT is carried out switching manipulation (in other systems, can adopt other power-supply device).Other signal is run over as follows:
If SLEEP_N (chip reset signal) is effective, positive closing DRIVE signal asynchronously then.When basic counter begins to increase progressively, DRIVE is driven to high.The DRIVE signal remains height, reaches the turn-on time (pulse_width) by pulse duration look-up table value defined up to this counter.This counter continues, till it reaches time minimum period.Then, this counter continues to increase progressively, and begins till the new mains switch cycle up to the request of answering the DEMAND_int signal or when reaching its maximum.
The electric current that OCP forwards its effective high state indication integrated power supply equipment (IGBT) to has surpassed the electric current restriction.To the remaining time in current switch cycle, make the DRIVE invalidating signal immediately, but begin the place this DRIVE signal is asserted that again (re-assert) is for normal at next cycle.In order to guarantee the fastest possible response, this is input as asynchronous.
OVP forwards its effective high state to and indicates the voltage that is reflected to surpass voltage limit.To the remaining time in current switch cycle, make the DRIVE invalidating signal immediately, but begin the place this DRIVE signal is asserted as normally again at next cycle.In order to guarantee the fastest possible response, this is input as asynchronous.
Overheat protector is by the OTP signal controlling, when detecting the excess temperature condition, with the OTP home position signal.Ending place in the current mains switch cycle remains 0 with DEMAND_int, thereby prevents to begin the new mains switch cycle.
Preferably, for system designer is made preparation, to add extra failure detector circuit, such as the circuit that is used to monitor the PCB temperature.When detecting this external fault, system moves the CS pin>=3.0V to, this will cause the set of fault latch device (CS work in usually 0V down to approximately-zone of 500mV in).This has activated the FLI_N signal, thereby prevents that digitial controller from beginning the new mains switch cycle.Can this fault latch device be resetted through chip being carried out the periodicity power supply.
Next each functional block among Fig. 3 will be described in order:
System counter 304:
This comprises counter on the single binary system, and its just edge at system clock increases progressively, and makes zero at the place that begins of each switch periods.
In a preferred embodiment, system counter 304 comprises 10 bit counter, and its output (X_COUNT) is used by other piece, to confirm the correct timing of its operation.This counter uses with following dual mode: be used for timing is carried out in the operation in mains switch cycle, it has predetermined turn-on time (pulse duration) and opening time, has accomplished n digital dock cycle altogether.Then, this counter continues counting, till the next mains switch cycle begins.When the indication of DEMAND_int signal should begin new mains switch during the cycle, through allowing PFM to be provided control with this counter reset to 0.The beginning in the mains switch cycle that the indication of STRAT signal is new.In a preferred embodiment, do not allow this counter rollover (roll-over).
Just before the new mains switch cycle began, X_COUNT indicated the value of the period of adjacent switch between the cycle.According to this information, pulse width mode controll block 310 can be confirmed actual switching frequency, and determines whether to answer pulse-width adjustment.
Demand or door 305:
This comprises the single or door that produces output DEMAND=OTP|OVP|FLI|FBD.
DEMAND SYNC [1:0] piece 306:
(re-clocked) output when this generation resets, DEMAND_INT=DEMAND.Accordingly, in a preferred embodiment, this piece obtains logic OR anti-of asynchronous OVP, OTP, FLI and FBD input, and through two triggers that inside (system) clock zone of itself and controller is synchronous.Its output (DEMAND_int) by basic counter in order to initiate the beginning in new mains switch cycle.
Drive-pulse generator 308:
This generation and output DRIVE and DRIVE_OP5 signal, this signal are the pulses that has by input PULSE_WIDTH and the defined length of X_COUNT.Just edge at system clock provides clock for DRIVE, is that DRIVE_OP5 provides clock in negative edge.
In a preferred embodiment, this comprises the piece based on latch, and it provides " primary " with required width gate driving pulse.With the X_COUNT zero clearing time, the output (DRIVE_raw) of drive-pulse generator 308 is set to effectively.Then, to the pulse_width duration by the appropriate value defined in the pulse bandwidth look-up table 312, it remains height.For the extremely refined control of pulse-width is provided, preferably when needs non-integer PULSE_WIDTH value, produce the version of the DRIVE_raw that postpones 1/2 clock cycle.It is carried out the logic OR computing with DRIVE_raw clocklike, to obtain being accurate to the pulse duration in immediate 1/2 digital dock cycle.
Pulse width mode control 310:
This produces output valve PWM_MODE (being equal to gear selector) according to X_COUNT<CHANGE_UP (being raised to bigger pulse duration) and X_COUNT>CHANGE_DOWN (dropping to littler pulse duration).
In a preferred embodiment, this comprise have on/4 bits of underflow protection on/following counter.The value (PWM_WIDTH_M1) of this counter is sent to pulse duration look-up table 312, therein this value is used to select suitable pulse duration.Only if be in its maximum permissible value, otherwise surpassed restriction f in the value indicator cock frequency of X_COUNT
CHANGE_UPThe time, PWM_MODE is increased progressively.On the contrary, only if be in its minimum value, otherwise dropped to restriction f in the value indicator cock frequency of X_COUNT
CHANGE_DOWNWhen following, PWM_MODE is successively decreased.Have only when the START signal is indicated the beginning of new switch periods, just adjust PWM_MODE.In an embodiment, maximum permissible value is confirmed by the CLKSEL value.
Pulse duration look-up table (LUT) 312:
This produces output valve PULSE_WIDTH (being similar to " gear box is than (gearbox ratio) ") according to PWM_MODE and CLKSEL.
In a preferred embodiment, this piece is divided selector (CLKSEL) with the PWM_MODE value of 4 bits together with clock and is converted into pulse duration (or turn-on time) value, for example as above shown in the table 2.Provide to help good output adjusting according to the table clause that maximum switching speed is selected, and help to reduce audio-frequency noise.To drive-pulse generator 308 7 bits outputs (PULSE_WIDTH) are provided.
Maximum switching frequency look-up table 314:
Segment value output (MIN_PERIOD) when this provides (10 bit) minimum switch, this output can be confirmed (in look-up table, quoting) by the CLKSEL value.In other embodiments, can adopt different frameworks that MIN_PERIOD is provided.
Pulse width variation frequency look-up table 316:
This provides and the top f that mentions
CHANGE_UPAnd f
CHANGE_DOWNSegment value CHANGE_UP and CHANGE_DOWN when frequency is distinguished corresponding (10 bit) switch periods.Here described framework (look-up table that CLKSEL quoted) allows these values to confirm that by the CLKSEL value although in the example of superincumbent table 3, same value is used for all four CLKSEL values.In other embodiments, can adopt different frameworks.
OCP/OVP drives cancellation piece 318:
OP_x& (DRIVE_RAW&DRIVE_OP5).In a preferred embodiment, this comprises and receives primary gate drive signal (DRIVE_raw), and uses the OP_x error signal that latchs to its asynchronous Boolean logic of modulating.Therefore, in an embodiment, its output DRIVE is substantially equal to DRIVE_raw, only if there is error condition, existing under the situation of error condition, to the remaining time of (current) switch periods, possibly force this signal to make zero.
Overcurrent/pressure protection piece 320:
This produces output OP_x=OVP|OCP.In a preferred embodiment, this comprise produce output OP_x based on asynchronous of latch, as long as overcurrent or overpressure condition occur, OP_x becomes effectively.Preferably, remove this OP_x signal at the place that begins in next mains switch cycle.
Now, further specify the operation of numerical control system 300 with reference to the sequential chart among the figure 4.
Connect feedback input FB with the configuration shown in Fig. 1, the data about the Cycle by Cycle of SMPS output state wherein are provided.Fig. 4 shows the relation between the key signal in this controlling schemes.
As discussed previously, when power-supply device 110 broke off, flyback (fly-back) action made FB circuit 122 be raised to constant voltage (for example, through transformer 108, diode, capacitor and optical coupler 116).Keep this voltage then, till the flyback oscillation phase, this moment, this voltage began to descend.Discharge rate is by optical coupler 116 management, and optical coupler 116 is controlled by the analog integration (analog integral) of output voltage error itself.Analog comparator 144 compares the voltage of FB and voltage from fixed reference 142, so that provide output 140 (FBD) to digital control module 300.Soon, the new mains switch cycle begins after FBD becomes zero.
Fig. 4 shows the relation between above-mentioned DRIVE, CS, FB, FBD, SYSCLK (system clock) and the X_COUNT signal.Along 400 places, when X_COUNT reaches pulse width values (from LUT 312), forbidding (disconnection) DRIVE, and FBD changes 1 (becoming effectively) into.After FB begins to descend a period of time, reach threshold value (voltage reference), this moment, FBD changed 0 (it is invalid to become) into, and this has defined along 402.Edge 404 is corresponding with edge 402, but by 306 delays of DEMAND_SYNC [1:0] piece.Along 404 places, X_COUNT is reset to zero (become invalid (promptly closing) afterwards at DRIVE, X_COUNT continues counting, to confirm the duration of current period, the i.e. switching frequency of current period).
As discussed previously, numerical control system 300 is realized the power supply plan as required of Cycle by Cycle.Each power-up period has the minimum duration that comprises n digital dock cycle, and this has confirmed the switching frequency of maximum possible.Power-up period has individual fixedly one of turn-on time (pulse duration, DRIVE is effective) of m that a digital dock cycle is not waited from p to q, and the opening time that is directed against the minimum value of the remaining time in n cycle.The value of m, n, p and q for example can be selected by routine experiment, so that the optimum performance to given application is provided.
Fig. 5 shows the operation of the embodiment of control system, and wherein m=4, so this control algolithm can change pulse duration on 4 fixed value pulse durations.To the condition of little load, the short pulse width of selective value p.This system is through selecting suitable opening time, therefore regulating SMPS for switching frequency.To medium load, select one of intermediate pulse width value, and adjust opening time so that correspondingly regulate SMPS.If switching frequency is too high or too low, then will select the different pulse width value.For maximum load, select maximum pulse q (be n/2 in this example, this has provided 50% duty ratio).In this case, be reduced to 0 the opening time that prolongs, and SMPS carries out switching manipulation with its peak frequency, the cycle is n.
In order to solve the different application of a plurality of targets, this framework preferably allows on single circuit, to realize the set of a plurality of m, n, p and q parameter.For example, can programme through tablet, to fuse or inner hardwired the proper parameters set is set.The exemplary set of these values is combined in the following table 4 and provides:
CLKSEL |
m |
n |
p |
q |
00 |
13 |
31 |
1 |
15 |
01 |
10 |
63 |
1 |
31 |
10 |
10 |
127 |
1 |
63 |
11 |
8 |
255 |
1 |
127 |
Table 4
Shown in above-mentioned example, realize regulating through the SMPS of pulse frequency modulated (PFM) through prolonging opening time by the determined amount of system feedback.
When a power-up period is accomplished, prolong opening time, drop to till zero up to the FBD signal, this indication SMPS output voltage has dropped to it below desired value, and should begin new power-up period.
Second control loop monitoring actual switch frequency is intended to avoid the SMPS switching manipulation to fall into the frequency place of audio-frequency noise frequency band so that it is remained in.Preferably, if switching frequency descends towards the zone that possibly produce audio-frequency noise, then select shorter turn-on time.
The PFM control loop compensates the pulse duration that reduces through the opening time that reduces between the power-up period, and this has the effect that increases switching frequency.When the power demands for SMPS reduced, this process continued, till reaching minimum pulse width p.Utilize this minimum pulse width, it is low preferably this switching frequency to be adjusted into needed that kind, regulates to realize SMPS.On the contrary, if switching frequency increases to not certain value of effective work as actual capabilities ground of SMPS, then can select longer turn-on time.
The PFM control loop is through increasing the pulse duration that compensates increase opening time between the power-up period, and this has the effect that reduces switching frequency.When the power demands for SMPS improved, this process continued, till reaching maximum pulse q.Utilize this maximum pulse, increase switching frequency (going up), regulate to realize output to its maximum permissible value like required strategic point.
(on average) electric weight that is transmitted in cycle at each mains switch is by confirming with the combination of switching frequency the turn-on time (pulse duration) of power-supply device, and switching frequency is confirmed by the interval between the power-up period.To the specific collection of input voltage and loading condition, controller will be confirmed suitable pulse duration, and the adjustment switching frequency, so that SMPS output is remained on the expectation voltage.Therefore, the adjusting of short-term is adjusted the switch periods frequency through adjustment opening time, and more long-term adjusting adjustment pulse duration.
Fig. 6 shows the diagram with the relation of the output power value of largest percentage and mains switch period frequency.The notion of " power layer (power strata) " that this has schemed illustration shows at CLKSEL and selects the maximum switching frequency of 500KHz to be directed against the power and the switching frequency scope of the realization with 9 pulse width values when (to this exemplary embodiment).
In the example of Fig. 6, controller remains on 20kHz (generally accepted human auditory's threshold value) between the 40KHz with switching frequency.Back one digital maintained switch speed is low, and the useful value of the hysteresis between the pulse width values still is provided simultaneously.No thoroughfare that pulse width modulation realizes that short-term is regulated for this.
We have described the SMPS controlling schemes, and it has realized that based on multiple initial conditions, output load condition and power reguirements the control of stable output voltage, in good time transient response and good audio-frequency noise suppress in an embodiment.Particularly, this controlling schemes is used PWM " gearcase " to raise the efficiency and is suppressed audio-frequency noise, prolongs opening time as required to realize adjusting.The embodiment of SMPS reponse system provides real-time Cycle by Cycle feedback response.Therefore, the embodiment of controller can utilize evenly spaced basically pulse and be operated under " power supply as required " operator scheme.
The technical staff can expect multiple other effective alternative undoubtedly.To be understood that the present invention is not limited to described embodiment, and have been comprised the spirit that is positioned at accompanying claims of the present invention that it will be apparent to those skilled in the art that and the modification of scope.